JPH11196142A - Baud timing synchronization system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve interpolation position accuracy in a detector for supplying through interpolation a symbol sample synchronized with a baud timing from the oversample sequence of PSK signals sampled asynchronously with the baud timing. SOLUTION: From an output waveform of a clock extraction means 131, a zero-crossing phase is estimated in a linear interpolation part 132c of a phase estimation means 132, and phase difference data are outputted. Stored value of an approximate correction ROM 133a for storing an error amount of linear approximation is added to the above phase difference data and a linear interpolation coefficient ROM 134 is referred to.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a baud timing synchronization system which is used in a demodulation circuit of a digital phase modulation signal and is particularly suitable for a demodulation circuit of a digital signal processing type.

[0002]

2. Description of the Related Art As one type of digital signal processing type demodulation circuit for a digital phase modulation signal, a baud timing phase is estimated from a sample sequence sampled asynchronously with a baud timing, and a sample at an identification time is calculated by interpolation. Getting done is done. (References, IEICE Transactions Vol. J72-BI No. 9, pp. 754-761, 1989
The above is a method suitable for accumulating and demodulating packet communication at a time. The maximum spectrum of the clock component is calculated by using DFT (Discrete Fourier Transform) to estimate the phase, and an interpolation formula called a mixed spline is calculated. Is used to interpolate symbol values.

[0003] Another document (IEICE Transactions V
ol. According to J79-B-II No.11, pp.968-971, November 1996), interpolation may be used to estimate the baud timing phase. This is a method that can be applied to a case where a continuous signal is sequentially demodulated. The time at which the reproduced clock crosses the zero level (hereinafter referred to as zero cross) is obtained by linear interpolation of successive sampling values of the clock component extracted by the filter means.

The concept of the latter example will be described with reference to the drawings.
FIG. 9 is a diagram illustrating the zero-cross phase. 4 asynchronous oversamples per symbol transmitted at baud rate
If it is doubled, the sample interval becomes x2-x1 = π / 2 [radian]. Assuming that the sample values of the clock component are y1 and y2, the occurrence of the zero crossing means that y2 × y1 is not a positive value and y2
Detected when> 0 holds. At this time, the phase error θE of the sample point from the original zero crossing is given by considering the clock component as a sine wave signal.

[0005]

(Equation 1)

Can be obtained by using an arctangent function. However, when implementing in a demodulation circuit, a table for calculating the arc tangent is required. If the required accuracy of phase error estimation is high, the table size increases.

Therefore, as shown in FIG.
As shown in FIG. 9, the zero cross phase is estimated by approximation by linear interpolation. The estimation formula in this case is

[0008]

(Equation 2)

## EQU1 ## As is clear from comparing the difference between the two equations with the phase estimation characteristic in FIG. 10, it can be seen that in this case, an error of about 4 degrees occurs at the maximum in the approximate estimation by linear interpolation.

[0010]

In digital phase modulation in recent years, narrowing of the band and multi-leveling have been studied, and there is a demand for further reducing the timing phase error. However, when an ideal arctangent function is used, taking into account the error when the zero-cross phase is obtained by linear interpolation, the required memory capacity increases. The problem to be solved by the present invention is to improve the accuracy without requiring a large increase in the memory.

[0011]

SUMMARY OF THE INVENTION In order to achieve the object of the present invention, sampling is performed asynchronously with a baud timing time.
Clock extracting means for extracting a baud rate frequency clock component from an oversampled sequence of in-phase and quadrature-phase components of a digital phase modulation signal, and detecting a zero-level crossing of the clock component to estimate a phase difference between the crossing point and a sampling point. Where the crossing point in the estimation is a phase estimating means that uses a linear approximation defined by the intersection of a straight line connecting two consecutive sample values and the zero level, and a phase output by the phase estimating means. A first storage unit that is addressed by the phase difference data and stores correction data for correcting the approximation error of the linear approximation; a value stored in the first storage unit;
Identification of a received symbol from the oversampled sequence using a second storage means addressed by the added data obtained by adding the phase difference data and storing a linear interpolation coefficient, and an interpolation coefficient output from the second storage means; Interpolation means for interpolating and outputting the time sample data is provided.

It is assumed that interpolation of received symbols is performed at a resolution obtained by equally dividing the sample interval by a predetermined number of divisions. The interpolation coefficient different for each zero-cross phase is not calculated each time, but the previously calculated interpolation coefficient is stored in the second storage means.

The correction value of the linear interpolation error in estimating the zero-crossing phase of the clock may be prepared corresponding to a discrete position for symbol interpolation, and the size of the first storage means is the predetermined number of divisions. In minutes.

In another means for achieving the same object, a decoding means for outputting an error-corrected second phase difference data for the phase difference data in place of the first and second storage means. And storage means for accessing the decoded output and storing linear interpolation coefficients for discrete phase positions. The interpolation means uses the interpolation coefficients output from the storage means.

Still another means is provided in place of the first and second storage means, in order to correct an error of a linear approximation which is accessed with the phase difference data and is not uniform with respect to discrete phase positions. Storage means for storing non-linear interpolation coefficients for the discrete phase positions, and the interpolation means uses the interpolation coefficients output from the storage means.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a PSK signal delay detection circuit according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of an example. In FIG. 1, 10a and 10b are mixers, 10c is a π / 2 phase shifter, 10d is a fixed oscillator, 11a and 11b are roll-off filters, and 12a and 12b are A / D.
A converter, 130 is an interpolation unit, 14 is a delay detection unit, and 15 is a frequency compensation unit. Further, 131 is a clock extracting means.
1b is a multiplier, 131c is an adder, 131d is a BPF (bandpass filter), 132 is a phase estimating means, 132a is a shift register having two stages, 132b is a zero-cross detector, and 132c is a linear interpolator. 133a is an approximate correction ROM, 133b is an adder, and 134 is a linear interpolation coefficient ROM. In this embodiment, the A / D converters 12a and 12b are PS
It is assumed that oversampling is performed at four times the baud rate frequency of the K signal. It is assumed that the sample value is handled as a signed 16-bit fixed point. First, the overall operation will be described.

The input PSK signal is subjected to quasi-synchronous detection using the free-running carrier frequency output from the fixed oscillator 10d.
A quadrature component is output from a mixer 10b that mixes the in-phase component from the mixer 10a and a signal obtained by shifting the carrier frequency by π / 2, and an I signal and a Q signal are obtained via roll-off filters 11a and 11b, respectively. The I and Q signals are converted to A / D converters 12a and 12a.
Sample at 4 times per symbol with b. This sampling is performed asynchronously with the transmission baud timing.

The determination of the received symbol requires a sample at the time when the eye is opened in synchronization with the baud timing.
This synchronous sample is obtained by the interpolation unit 130 for asynchronous sampling.

The interpolator 130 outputs a sample interpolated at the reception symbol period, and uses the sample to obtain a demodulated signal at the delay detector 14. The delay detection unit 14 accumulates the interpolation sample value of one symbol before, and performs delay detection by multiplying this complex conjugate value by the current interpolation sample.

The delayed detection output includes a stationary phase rotation due to a deviation between the fixed oscillator 10d and the carrier frequency of the PSK signal. The received symbol output Is and Qs signals are obtained.

In order to obtain a synchronous sample in the interpolation unit 130, for example, an interpolation filter operation having a FIR (finite impulse response) structure (shown in FIG. 3) described later is performed. The tap coefficient of this filter differs for each position to be interpolated. Therefore, the position to be interpolated to determine the coefficient is
It is necessary to obtain from the sample sequence of the received I and Q signals. This process is described below.

First, the clock component spectrum of the baud rate frequency is emphasized from the I and Q signal data by a non-linear operation. This is performed by squaring each of them by the multipliers 131a and 131b. In order to emphasize the clock component, the square value is further added by the adder 131c, and a sine waveform output of the clock component is obtained by the BPF 131d. The BPF 131d is a high-Q filter centered on the clock frequency, and simultaneously adjusts the gain so that the clock output does not saturate. This clock component waveform becomes the output of the clock extracting means 131 and is input to the phase estimating means 132. The input waveform samples are sequentially stored in the shift register 132a. Here, the number of stages of the shift register 132a is two, the bit length is 16 bits, the former stage is called B0, and the latter stage is called B1. This shift register 132a stores two consecutive samples. Using these two samples B0 and B1, the zero-cross detecting means 132b detects the zero-cross of the clock.
The zero-cross detecting means 132b determines that the result of B0 × B1 is not a positive sign and that B0 is positive as a zero-cross, and outputs zero-cross detection.

The linear interpolation means 132c calculates B0 / (B0-B1) upon detecting the zero-cross detection. Since B0 <B0−B1 except when B1 = 0, fractional division can be relatively easily realized by repeatedly using subtraction with carry of a DSP (digital signal processor). The result of the division is represented by a signed 16-bit fixed point, like the sample value. This determines the interpolation position from the phase difference data θ. Now, assume that the accuracy of finding the interpolation position is 1/64 of the sample interval. The sample interval is 90 degrees because the sample is 4 times oversampled. In this case, the sampling interval is 1/64, and the accuracy is about 1.4 degrees. At this time, the interpolation position may be obtained by reading the upper 6 bits excluding the sign bit of the phase data. However, since the phase difference data θ is a value obtained by approximating a sine wave with a straight line as described above, an error is included (about 4 degrees at the maximum). This is as explained in FIG. 5 in the conventional example, and the error amount differs depending on the zero cross position. Therefore, this phase difference data θ is approximately corrected.
The correction is performed by the ROM 133a and the adder 133b. Approximate correction ROM1 because the interpolation position is determined with an accuracy of 1/64 of the sample interval
33a may store the correction value accessed with the upper 6 bits excluding the sign bit of the phase difference data with 16-bit precision. Table 1 shows the values stored in the approximation correction ROM 132a.

[0025]

[Table 1]

The correction value and the phase difference data are added by the adder 133b, and the upper 6 bits excluding the sign bit may be used as new interpolation position data.

The interpolation means 130 performs interpolation by referring to the value of the linear interpolation coefficient ROM calculated in advance with the interpolation position data.

The interpolation operation will be described below. FIG. 2 is a diagram illustrating an interpolation operation. Figure 2 shows an example of the sample sequence of the clock extraction waveform, and the I of the received symbol sequence to be interpolated.
An example of a signal sample sequence is shown. As shown in the figure, a zero cross occurs between B1 and B0 of the sample of the clock waveform. At this time, it is detected by the phase estimating means 132 and its correcting means 133a, b that the sampling phase is sampled with a delay of θ from the baud timing phase.

Therefore, the I signal may be obtained by interpolating data at a time preceding by θ. Normally, the position where the eye opens with respect to the zero cross is the position two samples before in the case of a 4 × sample. However, in the process of obtaining the zero cross, the clock component passes through the BPF 131d, so that the clock component has a phase delay. In the present embodiment, the B
If the PF131d is an IIR (infinite impulse response) digital filter of order 2, the delay amount is one sample (90 degrees). Therefore, the eye opening point is three samples before the zero crossing, and falls between I4 and I3 in FIG.

In the case of this embodiment, the interpolation formula used here is I
A second-order Lagrange interpolation is used to interpolate the symbol before θ using the three points 2, 3, and 4. Assuming that the interpolation coefficients for the samples I2, I3, and I4 are h0, h1, and h2, the interpolation coefficients corresponding to the interpolation position data are as shown in Table 2 and FIG.

[0031]

[Table 2]

Symbol interpolation is performed using these coefficients. FIG. 4 is a diagram illustrating an example of the configuration of the interpolation unit 130.

In FIG. 4, 130a and 130b are FIR filters, 130c is a symbol buffer shift register, and 130d and 130d.
130e and 130f are multipliers, 130g is an adder, and 130h is a coefficient register.

The FIR filter unit 130a reads out the I signal data from the symbol buffer register 130c,
Performs cumulative addition with the stored value of 130h and outputs the interpolated value.

The storage in the coefficient register 130h is performed by the interpolation means 13
When 0 knows the zero-cross detection, the coefficient value specified by the interpolation position data at that time is read.

The symbol buffer shift register 130c
Has 5 stages to interpolate the position three samples earlier. Here, every time an I signal sample is input to I0, data is shifted by one stage.

Therefore, a sequence of I signal samples is input for each quadruple sample, and an interpolated sample is output at a zero-cross detection cycle.

The operation is exactly the same for the Q signal, and a description thereof will be omitted.

As described above, according to the present embodiment, the error using linear interpolation for zero-cross detection is used to reduce the size of the approximate correction ROM 1 of 64 words in size.
Since the correction can be performed by the adder 33a and the adder 133b, the accuracy of the interpolation position of the received symbol is improved.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram illustrating a configuration of the second exemplary embodiment of the present invention. Portions equivalent to those in the first embodiment are denoted by the same reference numerals. A feature of the second embodiment is that an address conversion decoder 133c is provided for correcting a linear interpolation error.

The upper 6 bits excluding the sign bit of the phase difference data output from the phase estimating means 132 are input to the address conversion decoder 133c. Here, when the error of the linear interpolation is corrected, it is decoded to another address data closest to the address data. The decoding address is input to the linear interpolation coefficient ROM 134 to refer to coefficient data.

In the case of this embodiment, the decoding rules are as shown in the conversion table of Table 3.

[0043]

[Table 3]

FIG. 6 shows the phase estimation characteristics in this case.

It can be seen that the accuracy of the interpolation position is improved as in the first embodiment.

Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram illustrating a configuration of the third exemplary embodiment of the present invention. Portions equivalent to those in the first embodiment are denoted by the same reference numerals. The feature of the third embodiment is that the interpolation coefficient can be directly referred to by the phase difference data output from the phase estimation means 132.
This is in that the stored value itself of the interpolation coefficient ROM is corrected.

That is, the contents of the ROM are replaced in place of the address conversion operation of the second embodiment. In this case, an interpolation coefficient is given in a non-linear relationship to the input phase position.
This is shown in FIG. 7 as M135. The complementing unit 130 is configured to refer to the non-linear interpolation coefficient ROM 135.

FIG. 8 shows an example of the values stored in the nonlinear interpolation coefficient ROM 135. The secondary Lagrange interpolation coefficients used in the first and second embodiments are indicated by line segments for comparison.

According to this embodiment, there is an advantage that the interpolation position accuracy can be improved only by rewriting the contents of the ROM.

[0050]

As described above, according to the present invention, a clock phase is estimated from a sample sequence of an asynchronously sampled PSK signal, and symbol samples synchronized with the baud timing are interpolated to provide a symbol sample synchronized with the baud timing. This has the effect of improving position accuracy.

In particular, compared with the case where the zero cross of the clock component is approximated by linear interpolation, there is an effect that the accuracy can be improved without a large increase in the circuit scale and the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an interpolation operation.

FIG. 3 is an example of an interpolation coefficient according to the first embodiment.

FIG. 4 is a diagram showing an example of a configuration of an interpolation unit 130.

FIG. 5 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 6 shows phase characteristics when an address conversion decoder 133c is interposed.

FIG. 7 is a block diagram illustrating a configuration of a third exemplary embodiment of the present invention.

FIG. 8 is an example of an interpolation coefficient of a non-linear interpolation coefficient ROM 135 according to the third embodiment.

FIG. 9 is a diagram illustrating a zero-cross phase.

FIG. 10 shows phase estimation characteristics (of Equations 1 and 2).

[Explanation of symbols]

10a, 10b: mixer, 10c: π / 2 phase shifter, 10d: fixed oscillator, 11a, 11b: roll-off filter, 12a, 12b
: A / D converter, 130: interpolation unit, 130a, 130b: FIR filter unit, 130c: symbol buffer shift register,
130d, 130e, 130f: Multiplier, 130g: Adder, 130h:
Coefficient register, 14: delay detector, 15: frequency compensator, 131: clock extraction means, 131a, 131b: multiplier,
131c: adder, 131d: BPF (bandpass filter),
132: phase estimation means, 132a: shift register, 132
b: Zero cross detection unit, 132c: Linear interpolation unit, 133a:
Approximation correction ROM, 133b: adder, 133c: address conversion decoder, 134: linear interpolation coefficient ROM, 135: nonlinear interpolation coefficient ROM,

Claims (3)

[Claims] 1. Clock extraction means for extracting a clock component of a baud rate frequency from an oversampled sequence of in-phase and quadrature-phase components of a digital phase modulation signal sampled asynchronously with a baud timing time, and said clock component. Is a phase estimator that detects the zero-level crossing of, and estimates the phase difference between the crossing and the sample point. The crossing in the estimation is defined as the intersection of a straight line connecting two consecutive sampled values and the zero level Phase estimation means using linear approximation, first storage means addressed by the phase difference data output from the phase estimation means and storing correction data for correcting an approximation error of the linear approximation; first storage means And a second storage unit that is addressed by an added data obtained by adding the stored value of the phase difference data and stores a linear interpolation coefficient. Characterized in that it comprises interpolating means for interpolating the output sample data of the identification time of the received symbol from the over-sample sequence by using an output interpolating coefficients, baud timing synchronization method of the digital phase-modulated signal. 2. The clock extracting means and the phase estimating means according to claim 1, and decoding means for decoding the phase difference data output from the phase estimating means into second phase difference data in which the approximation error of the linear approximation has been corrected. And storage means for storing a linear interpolation coefficient addressed by the decoded output, and using the interpolation coefficient output from the storage means to interpolate the sample data of the identification time of the received symbol from the oversampled sequence described in one item. A baud timing synchronization method for a digital phase modulation signal, comprising an interpolation means for outputting. 3. A clock extracting means and a phase estimating means according to claim 1, and an address specified by using phase difference data output from the phase estimating means, and a non-linear interpolation coefficient for the input phase difference is stored. Storage means, and interpolation means for interpolating and outputting sample data at the identification time of the received symbol from the oversampled sequence described in the paragraph using the interpolation coefficient output from the storage means. Baud timing synchronization method.