JPH11195930A - Phase comparator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure stability of a control loop against a control dead band and to prevent wrong-synchronization in a reverse phase. SOLUTION: A Main-IF signal is branched into two a distributor 1 which are given to mixers 5, 6. A Sub-IF signal is branched into two by a π/2 phase shifter 3 and a distributor 2, and given to the mixer 6 via the mixer 5 and a π/2 phase shifter 4. An output of the mixer 5 is given to comparators 9, 10 via a detector 7. The comparator 9 is used for detecting a lead phase and the comparator 10 is used for detecting a lag phase. The output of the mixer 6 is given to a comparator 11 via a detector 8. When a signal from the comparator 9 is given to an UP terminal, a counter 13 counts up the received signals. When a signal from an OR circuit 12 is given to a DOWN terminal, the counter 13 counts down the received signals. The output of the comparator 11 is given to the couture 13 via the OR circuit 12 to forcibly make the counter 13 count down when the signal is inverted in phase in a dead band state. The output of the counter is outputted via a D/A converter 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for receiving a signal from a main antenna (hereinafter, referred to as a Main signal) and a signal from a sub antenna (hereinafter, referred to as a Sub signal), and for receiving one of the received signals. The present invention relates to a phase comparison circuit suitable for a radio apparatus having space diversity for synthesizing a Main signal and a Sub signal by adjusting the other phase by a phase control loop including a phase comparison circuit, a phase shifter, and a mixer.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional phase comparator of this type. In FIG. 6, the mixer 72 includes Ma
The IF signal of the in signal and the IF signal of the Sub signal are π / 2
A signal delayed by π / 2 (90 deg) by the phase shifter 71 is input. The output of the mixer 72 is detected by a detector 73, converted to a low-frequency output, and input to a comparator 74 and a comparator 75.

Here, the comparator 74 and the comparator 75 have different threshold values and different determination polarities. That is, the comparator 74 is a comparator for detecting a leading phase, and the comparator 75 is a comparator for detecting a lagging phase. The output of the comparator 74 is input to the UP terminal of the counter 76, and the output of the comparator 75 is input to the DOWN terminal of the counter 76.

A counter 76 is an up-down counter, which receives a phase advance detection signal from a comparator 74,
It counts up during the phase advance, and on the other hand, inputs the phase shift delay detection signal from the comparator 75 and counts down while the phase is delayed. The output of the counter 76 is converted into an analog amount by a D / A converter 77, which is a digital-analog converter, and output as a phase comparison result.

Next, the operation of FIG. 6 will be described with reference to FIG. FIG. 7 shows the Main-IF signal and Su
The correspondence between the output waveform of the detector 73 when there is a phase difference in the b-IF signal and the comparison threshold in the comparators 74 and 75 in the subsequent stage is shown.

[0006] When the output of the detector 73> a1 ... Sub-
IF phase advance (phase <φ1) or Sub-IF phase delay (phase> φ4) When output of detector 73 <a2 ... Sub-IF phase delay (φ2 <phase <φ3) a2 ≦ output of detector 73 ≦ a1 When ... In-phase (φ1 ≦
In-phase range ≦ φ2) or opposite phase (φ3 ≦ anti-phase range ≦ φ
4) Here, the range of a1 to a2 of the output of the detector 73 is defined as the in-phase range, that is, the control dead zone.
This is to provide a dead zone to suppress sensitive responses and stabilize control.

[0007]

SUMMARY OF THE INVENTION Main signal and Sub signal
A radio having space diversity for receiving signals and adjusting the phase of one of the received signals by the phase control loop including a phase comparison circuit, a phase shifter, and a mixer to combine the Main signal and the Sub signal. When the phase shift comparison circuit of FIG. 6 is used for the device, the detector 7
When the amplitude range of No. 3 is at the level of a1 to a2, it is determined that the phase is in the synchronized state.
In any of the cases of φ2 and φ3 to φ4, a phase-locked state is achieved. However, the former φ1 and φ2 correspond to the same phase, while the latter φ3 and φ4 correspond to the opposite phase. When the synchronization is established in the state of the opposite phase, S is applied to the Main signal.
There is a disadvantage that the ub signals are combined in opposite phases and cancel each other out, so that the function as space diversity cannot be achieved.

That is, in the conventional phase comparison circuit, since the detector 73 cannot discriminate between the same phase and the opposite phase, there is a possibility that an erroneous synchronization state with the opposite phase occurs. In order to reduce erroneous synchronization in the conventional configuration, it can be solved to some extent by making the dead zone of the control as narrow as possible. However, there is a disadvantage that stability of the phase control loop is impaired.

It is an object of the present invention to provide a phase comparison circuit which can simultaneously satisfy the stability of the control loop due to the dead zone of the control and the fact that it does not erroneously synchronize with the opposite phase.

[0010]

SUMMARY OF THE INVENTION According to the present invention, in a phase control loop having a plurality of stable phases, a means for distinguishing a desired stable phase from an undesired stable phase and a phase synchronization by the undesired stable phase are provided. A means for inhibiting the phase and synchronizing the phase with a desired stable phase is provided. Specifically, it is characterized by comprising an anti-phase detecting means for detecting a phase synchronization state due to an anti-phase, and a means for inhibiting output of a signal indicating the phase synchronization state in the case of an anti-phase.

Further, according to the present invention, a Main signal and a Sub signal are respectively received, and one of the received signals is phase-adjusted by a phase control loop including a phase comparator, a phase shifter, and a mixer. In a wireless device having space diversity for combining a Main signal and a Sub signal, the phase comparator is configured so that the phase control loops are synchronized in phase and in opposite phases. And a synchronization prevention circuit for preventing establishment of synchronization. By this, Main
It is possible to avoid a disadvantage that the Sub signal is combined with the signal in the opposite phase and cancels each other.

A phase comparison circuit according to the present invention comprises a comparator for detecting a phase advance, a counter for counting the amount of phase shift (phase shift) by respective outputs of the comparator for detecting a phase delay, and an analog output of the counter. A D / A converter that converts the amount into a quantity and outputs the result as a phase comparison result; an anti-phase detection circuit that detects an anti-phase state; and a detection result of the anti-phase detection circuit as one of the control inputs of the counter. This prevents the synchronization from being established.

Further, the phase comparison circuit of the present invention is a means for preventing a phenomenon in which a phase advance signal and a phase delay signal compete with each other, which may occur due to the provision of the anti-synchronization establishment means. It is characterized by having.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, I of the Main signal
The F signal is split by the splitter 1 into two parts, one of which is
And the other is input to the mixer 6. The IF signal of the Sub signal is delayed by π / 2 (90 deg) by the π / 2 phase shifter 3 and then input to the distributor 2.
The other is input to the mixer 6 via the π / 2 phase shifter 4. The output of the mixer 5 is converted into a low frequency as a detection output by the detector 7 and input to the comparator 9 and the comparator 10.
The comparator 9 and the comparator 10 have different threshold values and different determination polarities. That is, the comparator 9 is a lead phase detection comparator, and the comparator 10 is a delay phase detection comparator.

On the other hand, the output of the mixer 6 is detected by a detector 8 and input to a comparator 11. The π / 2 phase shifter 4, the mixer 6, the detector 8, and the comparator 11 provide an anti-phase detector 1
5. The output of the comparator 9 is U
Input to P terminal. The output of the comparator 10 and the output of the comparator 11 are ORed by the OR circuit 12 and input to the DOWN terminal of the counter 13.

The counter 13 is an up-down counter. When a phase advance detection signal from the comparator 9 is input to the UP terminal, the counter 13 counts up during the phase advance. On the other hand,
The input from the OR circuit 12 of the counter 13 is a delay phase detection signal. When this phase delay detection signal is input to the DOWN terminal, the countdown is performed while the phase is delayed.
The output of the comparator 11 is input to the counter 13 via the OR circuit 12, whereby the counter 13 is forcibly operated while in the opposite phase and in the dead zone state. The output of the counter is a D / A converter 1 which is a digital-analog converter.
The signal is converted into an analog quantity by 4 and output as a phase comparison result.

Next, the circuit operation of the present invention will be described with reference to FIGS. Note that FIG. 2 shows the output waveforms of the detectors 7 and 8 when there is a phase difference between the Main-IF signal and the Sub-IF signal and the comparators 9 and 10 at the subsequent stage, similarly to FIG. Shows the correspondence of the comparison threshold values.

When the output of the detector 7> a1, Sub-I
F phase advance (phase <φ1) or Sub-IF phase delay (phase> φ4) When output of detector 7 <a2 ... Sub-IF phase delay (φ2 <phase <φ3) a2 ≦ output of detector 7 ≦ a1 When ... In-phase (φ1 ≦ In-phase range ≦ φ2) or Out-of-phase (φ3 ≦ Inverse phase range ≦ φ
4) As in FIG. 6, the range of a1 to a2 of the output of the detector 7 is set as the in-phase range, that is, as a dead zone for control, sensitive response is suppressed, and control is stabilized. Therefore,
The phase ranges for the levels a1 to a2 determined as the same phase range are φ1 to φ2 and φ3 to φ4. The former φ1 and φ2 correspond to the same phase, while the latter φ3
Since φ4 corresponds to the opposite phase, the detector 7 cannot distinguish between the same phase and the opposite phase.

On the other hand, the output of the detector 8 has a waveform shifted by π / 2 from the output of the detector 7. The phases corresponding to b of the output of the detector 8 are φ5 and φ6. Therefore,
By setting the detector 8 to φ5 when the detector 7 is φ3, and to φ6 when the detector 7 is φ4,
Phase comparator 11 so that φ3 = φ5 and φ4 = φ6.
Thus, by detecting the level of the detector 8 equal to or higher than b, it is possible to detect the opposite phase. And this phase comparator 11
Of the counter 13 through the OR circuit 12
By supplying it to the terminal, when the phase is reversed, it is processed as a phase delay state.

FIG. 3 is a block diagram showing an application example of the phase comparator of the present invention. In FIG. 3, a Main signal in a radio frequency band (hereinafter, Main-RF signal) is input to a mixer 21 together with an output of a local oscillator 23, and is converted into a signal in an intermediate frequency band. On the other hand, Sub in the radio frequency band
The signal (hereinafter referred to as Sub-RF signal) is similarly transmitted to the infinite phase shifter 24.
The signal is then input to the mixer 22 together with the output of the local oscillator 23 that has passed (hereinafter referred to as EPS 24), and converted into a signal in the intermediate frequency band.

The signals of the two intermediate frequency bands are supplied to one Main signal side through a band-pass filter 25 and then to a splitter 25.
And is branched into two. One of the two branched signals is input to a combiner 32, and the other is input to an AGC-AMP 29 which is an automatic gain control amplifier. Similarly, on the Sub signal side of the intermediate frequency band, one is input to the synthesizer 32,
The other is input to AGC-AMP30. The combiner 32 combines the Main signal and the Sub signal in the intermediate frequency band,
It is output as a space diversity (SD) composite signal.

The input of the Main-IF signal and the input of the Sub-IF signal of the phase comparison circuit 31 need to be at the same level, and the AGC-AMP 29 and the AGC-AMP 30 amplify the input to a certain level. Each is input to the phase comparison circuit 31 as an -IF signal. Here, as the phase comparison circuit 31, FIG.
Is used. The phase comparison output of the phase comparison circuit 31 is input to the EPS 24.

In the EPS 24, the signal from the local oscillator 23 is controlled by the control signal from the phase comparator 23 to control the amount of phase shift and output to the mixer 22. This allows the synthesizer 32
, The main signal and the sub signal can be combined in the same carrier phase.

In FIG. 1, the Main signal and the Su signal
Although the phase comparison of the b signal is performed by the mixer 5 and the mixer 6, in the case of the phase comparison by the mixer, since the characteristics are multiplied, when the Main signal and the Sub signal are directly compared, π / 2
Synchronization occurs out of phase. Therefore, in the embodiment of FIG. 1, the phase of the Sub-IF input is shifted by π / 2 in advance. As a result, at the input stage of the synthesizer 32 shown in FIG.
The system of FIG. 3 is controlled so that the phases of the Main signal and the Sub signal are the same.

In the above-described embodiment, as shown in FIG. 2, the opposite phase ranges φ3 to φ4 of the phase detection for synchronization and the opposite phase detection ranges φ5 to φ6 are the same. In an actual circuit, the range of φ5 to φ6 needs to be wider than the range of φ3 to φ4 due to imperfections such as setting errors. In this case, since the detection of φ3 to φ4 and the detection of φ5 to φ6, that is, the output of the comparator 9 and the comparator 10 and the output of the comparator 11 in FIG. 1 may conflict, it is necessary to provide a conflict inhibiting circuit.

FIG. 4 is a block diagram showing another embodiment of the present invention. In FIG. 4, distributors 51, 52, π
/ 2 phase shifters 53 and 54, mixers 55 and 56, detector 5
7, 58, comparators 59, 60, 61, an OR circuit 62, a counter 63, and a D / A converter 64 correspond to the distributors 1, 2, the π / 2 phase shifters 3, 4, and the mixer 5 of FIG. ,
6, detectors 7, 8, comparators 9, 10, 11, OR circuit 1
2, the counter 13 and the D / A converter 14, and their basic operations are the same as those in FIG.

In this embodiment, an inhibit circuit 66 is provided between the output of the comparator 61 and the OR circuit 62, and the output of the comparator 61 is inhibited by the output of the comparator 59. .

That is, as shown in FIG. 5, when the phase difference between the Main signal and the Sub signal exceeds φ4, the comparator 5
9 outputs a count-up signal to the counter 63 and outputs a prohibition signal to the prohibition circuit 66. On the other hand, the reverse phase detection range φ5
When the phase difference φ4 is included in φ6, a countdown signal is output from the comparator 61 to the counter 63.
Are blocked by the inhibit signal output to the inhibit circuit 66 and are not output to the counter 63, so that the counter 63 counts up by inputting only the count-up signal from the comparator 59. Therefore, the conflict can be prevented.

[0029]

According to the present invention, an anti-phase detection circuit is provided in addition to the phase detection circuit for phase synchronization, and the establishment of anti-phase synchronization is inhibited by the output of the anti-phase detection circuit. Phase synchronization, that is, erroneous synchronization can be prevented.

Also, the reverse phase range, that is, a dead zone region for control in the reverse phase when the reverse phase detection circuit does not operate (FIG. 3)
(The range of φ3 to φ4) can be set to a large value, the synchronization can be inhibited in that range, so that the in-phase range, that is, the dead zone of control can be set to an arbitrary width.

Further, when means for preventing competition between the phase advance signal and the phase delay signal is provided, it is possible to allow variations in the dead zone.

[0032]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG.

FIG. 3 is a diagram showing an application example of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a waveform chart for explaining the operation of FIG. 4;

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a waveform diagram for explaining the operation of the conventional example.

[Explanation of symbols]

1, 2, 51, 52 Distributor 3, 4, 53, 54, 71 π / 2 phase shifter 5, 6, 55, 56, 72 Mixer 7, 8, 57, 58, 73 Detector 9, 10, 11, 59, 60, 61, 74, 75 Comparator 12, 62 OR circuit 13, 63, 76 Counter 14, 64, 77 D / A converter 15, 65 Out-of-phase detector 21, 22 Mixer 23 Local oscillator 24 Infinity Phase shifter 25, 26 Band-pass filter 27, 28 Distributor 29, 30 AGC-AMP 31 Phase comparator 32 Synthesizer 66 Prohibition circuit

Claims (6)

[Claims] A phase comparison circuit used in a phase control loop having a plurality of stable phases, means for distinguishing a desired stable phase from an undesired stable phase, and prohibiting phase synchronization by the undesired stable phase. And a means for synchronizing the phase to a desired stable phase. 2. The phase comparison circuit according to claim 1, wherein the undesired stable phase is a phase in which the phase difference is opposite. 3. The method according to claim 1, wherein the first input signal and the second input signal are 9
First phase difference detecting means for mixing a signal shifted by 0 ° and outputting a signal having a level corresponding to a phase shift difference between the two signals; and outputting the first input signal and the second input signal to each other. °
A second phase difference detection unit that mixes the phase-shifted signal and outputs a signal having a level corresponding to the phase difference between the two, and that an output of the first phase difference detection unit is equal to or higher than a predetermined level. The first which detects and outputs a count-up signal
A second comparator for detecting that the output of the first phase difference detecting means is equal to or lower than a predetermined level, and outputting a countdown signal.
A third comparator for detecting that the output of the second phase difference detecting means is equal to or higher than a predetermined level, and outputting a countdown signal.
And outputs of the second and third comparators, and
An OR circuit that outputs the OR signal; a counter that counts up upon receiving a count-up signal output from the first comparator, and counts down upon receiving a count-down signal output from the OR circuit; And a D / A converter that converts the count value into an analog signal and outputs the analog signal. 4. The apparatus according to claim 3, further comprising a prohibition circuit for prohibiting the output from the third comparator when the count-up signal is being output from the first comparator. Phase comparison circuit. 5. A main signal from the main antenna and a sub signal from the sub-antenna are received, respectively, and one of the received signals is converted to the other by a phase control loop including a phase comparison circuit, a phase shifter, and a mixer. After adjusting the phase,
A wireless device having space diversity for combining an ain signal and a Sub signal, wherein the phase comparison circuit according to claim 3 is used as the phase comparison circuit. 6. A main signal from the main antenna and a sub signal from the sub-antenna are respectively received, and one of the received signals is converted to the other by a phase control loop including a phase comparison circuit, a phase shifter, and a mixer. After adjusting the phase,
A radio apparatus having space diversity for combining an ain signal and a Sub signal, wherein the phase comparison circuit according to claim 4 is used as the phase comparison circuit.