JPH02237324A - In-phase synthesis space diversity receiver - Google Patents

In-phase synthesis space diversity receiver

Info

Publication number
JPH02237324A
JPH02237324A JP1059001A JP5900189A JPH02237324A JP H02237324 A JPH02237324 A JP H02237324A JP 1059001 A JP1059001 A JP 1059001A JP 5900189 A JP5900189 A JP 5900189A JP H02237324 A JPH02237324 A JP H02237324A
Authority
JP
Japan
Prior art keywords
phase
dead zone
voltage
input signals
received input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1059001A
Other languages
Japanese (ja)
Other versions
JPH0758929B2 (en
Inventor
Hirosada Atsuta
熱田 裕貞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1059001A priority Critical patent/JPH0758929B2/en
Publication of JPH02237324A publication Critical patent/JPH02237324A/en
Publication of JPH0758929B2 publication Critical patent/JPH0758929B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To always synthesize around in-phase point by devising the receiver such that the phase hardly enters a dead zone near an opposite phase and a phase error from an in-phase point is decreased near in-phase. CONSTITUTION:The receiver is devised such that the phase hardly enters a dead zone when the relation of phases of two reception inputs is nearly in an opposite phase and a phase error from the in-phase point is decreased near in-phase relation. When the relation of phases of the two reception input signals is at the outside of dead zone of phase control, the width of dead band is decreased, and when the relation of the phases exists within the dead zone, the width of dead zone is increased. Thus, the phase control is stopped in the case of in-phase synthesis and phase control is applied within a range where the phase error is very small from the in-phase point (phase difference is 0 deg.) at the outside in the vicinity of the in-phase. Moreover, the two reception input signals are always synthesized near the in-phase and the deterioration to be caused by controlling an endless phase shifter in an unnecessary way is minimized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は位相比較器において2つの受信入力信号の位相
差を検出し、その出力から受信入力信号間での位相の進
み又は遅れを判定して受信入力信号の位相差を制御する
同相合成スペースダイバーシティ受信装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention detects the phase difference between two received input signals in a phase comparator, and determines the phase lead or lag between the received input signals from the output thereof. The present invention relates to an in-phase synthesis space diversity receiver that controls the phase difference of received input signals.

〔従来の技術〕[Conventional technology]

従来の受信装置における同相合成スペースダイバーシテ
ィ受信装置の実施例のブロック図を第3図に示す。同図
において、受信入力信号S2は無限移相器(EPS)1
によって位相が制御され、電力合成器2において受信入
力信号S1と常に同相で合成が行われる。この合成信号
は図外の復調器(DEM)へ送られてベースバンド信号
に復調される。
A block diagram of an embodiment of an in-phase combining space diversity receiver in a conventional receiver is shown in FIG. In the figure, the received input signal S2 is input to an infinite phase shifter (EPS) 1.
The phase is controlled by the power combiner 2 so that the signal is always combined in phase with the received input signal S1. This composite signal is sent to a demodulator (DEM) (not shown) and demodulated into a baseband signal.

一方、前記電力合成器2への2つの入力信号はともに分
岐されて夫々バンドパスフィルタ34及び自動利得制御
(AGC)増幅器5.6を通った後、位相比較器7に入
力される。前記バンドバスフィルタ3.4は変調波の中
心周波数付近の成分のみを取り出すための狭帯域バンド
バスフィルタ(BPF)であり、自動利得制御増幅器5
,6ば信号レヘルを常に一定に保つように機能する。
Meanwhile, the two input signals to the power combiner 2 are branched together and passed through a band pass filter 34 and an automatic gain control (AGC) amplifier 5.6, respectively, and then input to a phase comparator 7. The bandpass filter 3.4 is a narrowband bandpass filter (BPF) for extracting only the components near the center frequency of the modulated wave, and the automatic gain control amplifier 5
, 6 function to always keep the signal level constant.

また、一方の信号、ここでは受信入力信号S2側のみ9
0゜位相を変化させるための90’移相器8を通してい
る。
Also, one signal, here only the received input signal S2 side, is 9
It passes through a 90' phase shifter 8 for changing the phase by 0°.

そして、位相比較器7では、第4図(a)のように、比
較する2つの信号が同相のときにその出力がOとなるよ
うな特性を有しており、この特性で前記2つの信号を比
較する。この位相比較器7の出力電圧V。は、夫々異な
る値に固定したしきい値電圧を持つ2つの電圧比較器9
及び10に人力され、第4図(b)及び(c)のような
一方の入力位相の遅れの検出信号と一方の人力位相の進
みの検出信号とを得ている。この位相情報を持つ2つの
制御信号により、無限移相器制御回路11は前記の無限
移相器1で受信入力信号S2の位相を制御して同相合成
を行っている。
As shown in FIG. 4(a), the phase comparator 7 has a characteristic such that its output becomes O when the two signals to be compared are in phase, and with this characteristic, the two signals Compare. The output voltage V of this phase comparator 7. are two voltage comparators 9 each having a threshold voltage fixed to a different value.
and 10, to obtain one input phase delay detection signal and one input phase advance detection signal as shown in FIGS. 4(b) and 4(c). Using the two control signals having this phase information, the infinite phase shifter control circuit 11 controls the phase of the received input signal S2 in the infinite phase shifter 1 to perform in-phase synthesis.

〔発明が解決しようとする課題〕 上述した従来の同相合成スペースダイハーシティ受信装
置では、第4図に示したように位相比較器7の出力電圧
V。がVl >Vo>V2のときには、2つの電圧比較
器9及び10で位相の進み及び遅れを全く検出しない位
相差の範囲が存在し、位相制御を行わない不感帯となっ
ている。これは同相合成時において不感帯を設けないと
、受信入力信号S2は常に無限移相器1により位相制御
されるため、その合成波に対して雑音の要因となり、或
いは位相のゆらぎとして受信装置全体の誤り率特性を劣
化させる要因となる場合があるためであり、不感帯を設
けることによってこれを防止していた。
[Problems to be Solved by the Invention] In the conventional in-phase synthesis space diharsity receiver described above, the output voltage V of the phase comparator 7 as shown in FIG. When Vl>Vo>V2, there is a phase difference range in which the two voltage comparators 9 and 10 do not detect any phase lead or lag, and this is a dead zone in which no phase control is performed. This is because if a dead band is not provided during in-phase synthesis, the received input signal S2 will always be phase-controlled by the infinite phase shifter 1, which will cause noise to the synthesized wave, or cause phase fluctuations in the entire receiving device. This is because it may cause deterioration of error rate characteristics, and this has been prevented by providing a dead zone.

しかし、従来のように位相比較器7の出力電圧に対して
2つの電圧比較器9および10の固定の不感帯を設定す
るだけの方式では2つの受信入力信号が同相のときのみ
ならず逆相のときにもその2つの受信入力信号の位相差
において不感帯が生じてしまう。このため、何らかのき
っかけで受信入力の位相関係が逆相付近の不感帯へ飛び
込むと逆相合成状態のまま位相制御が止まってしまうと
いう問題があった。
However, in the conventional method of simply setting a fixed dead zone of the two voltage comparators 9 and 10 with respect to the output voltage of the phase comparator 7, it is difficult not only when the two received input signals are in phase but also when they are in opposite phase. Sometimes, a dead zone occurs due to the phase difference between the two received input signals. For this reason, there is a problem in that if the phase relationship of the received input jumps into a dead zone near the opposite phase for some reason, the phase control will stop while remaining in the opposite phase combination state.

本発明は逆相付近では不感帯に入り難く、かつ同相付近
では同相点からの位相誤差が小さくなるようにして常に
同相付近での合成を可能にした同相合成スペースダイバ
ーシティ受信装置を提供することを目的とする。
An object of the present invention is to provide an in-phase synthesis space diversity receiver that is difficult to enter a dead zone near the opposite phase, and that makes it possible to always perform synthesis near the in-phase by reducing the phase error from the in-phase point near the in-phase. shall be.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の同相合成スペースダイバーシティ受信装置は、
2つのアンテナから夫々入力される2つの受信入力信号
の位相を比較する位相比較器と、この位相比較器の出力
から2つの受信入力信号間の位相の遅れを検出する第1
の電圧比較器と、同様に位相の進みを検出する第2の電
圧比較器と、これら電圧比較器の出力として得られる位
相制御情報により前記2つの受信入力信号の位相差を制
御する制御回路とを備えた受信装置において、第1およ
び第2の電圧比較器には夫々前記位相制御情報によって
出力電圧が変化される基準電圧発生器を付設しており、
この基準電圧発生器の出力電圧により第1及び第2の電
圧比較器の各しきい値電圧にヒステリシス特性を持たせ
ている。
The in-phase synthesis space diversity receiving device of the present invention includes:
a phase comparator that compares the phases of two received input signals respectively input from two antennas; and a first phase comparator that detects a phase delay between the two received input signals from the output of the phase comparator.
a voltage comparator, a second voltage comparator that similarly detects a phase lead, and a control circuit that controls the phase difference between the two received input signals using phase control information obtained as the output of these voltage comparators. In the receiving device, the first and second voltage comparators are each provided with a reference voltage generator whose output voltage is changed according to the phase control information,
The output voltage of this reference voltage generator gives each threshold voltage of the first and second voltage comparators a hysteresis characteristic.

〔作用〕[Effect]

上述した構成では、2つの受信入力信号の位相関係が位
相制御の不感帯外にある場合には不感帯幅が小さくなり
、不感帯内にある場合には不感帯幅が大きくなる。した
がって、同相合成時には位相制御を止め、同相付近以外
の時には同相点からの位相誤差の極めて小さい範囲内に
位相制御を行なう。
In the configuration described above, when the phase relationship between the two received input signals is outside the phase control dead zone, the dead zone width becomes small, and when it is within the dead zone, the dead zone width becomes large. Therefore, phase control is stopped during in-phase synthesis, and when the phase is not near the in-phase, phase control is performed within a range where the phase error from the in-phase point is extremely small.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図であり、第3図
に示した従来装置と同一部分には同一符号を附し、その
詳細な説明は省略している。
FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those of the conventional device shown in FIG. 3 are given the same reference numerals, and detailed explanation thereof is omitted.

この装置では、位相比較器7の出力電圧を判定するため
の電圧比較器9及び電圧比較器10の各しきい値電圧に
ヒステリシス特性をもたせるために、基準電圧発生回路
12及び基準電圧発生回路13を設け、電圧比較器9及
び10の出力レベルに応じてしきい値電圧を変えるよう
に構成している。
In this device, a reference voltage generation circuit 12 and a reference voltage generation circuit 13 are used to provide a hysteresis characteristic to each threshold voltage of a voltage comparator 9 and a voltage comparator 10 for determining the output voltage of a phase comparator 7. is provided, and the threshold voltage is changed according to the output levels of the voltage comparators 9 and 10.

このように構成すれば、第2図(a)及び(b)に示す
ように、基準電圧発生回路12及び基準電圧発生回路1
3は、2つの受信入力信号間の位相差Δθ+90゜を位
相比較器7で′位相比較した出力電圧により入力位相の
遅れ及び進みを判定する電圧比較器9及び電圧比較器1
0の各しきい値電圧V,,V2を制御する。そして、2
つの受信入力信号間の位相差Δθ+90゜が0゜又は1
80゜付近である場合の不感帯Iの幅V2’  Vl’
が、それ以外の位相差の領域での不感帯■の幅■2″■
,″に比べ狭くなるような制御を行っている。
With this configuration, as shown in FIGS. 2(a) and 2(b), the reference voltage generation circuit 12 and the reference voltage generation circuit 1
Reference numeral 3 denotes a voltage comparator 9 and a voltage comparator 1 that determine whether the input phase is delayed or advanced based on the output voltage obtained by comparing the phase difference Δθ+90° between the two received input signals with the phase comparator 7.
The threshold voltages V, , V2 of 0 are controlled. And 2
The phase difference Δθ+90° between the two received input signals is 0° or 1
Width of dead zone I when it is around 80° V2'Vl'
However, the width of the dead zone ■2''■ in other phase difference regions
,'' is controlled so that it is narrower than .

ここで、■,′は入力位相が不感帯■内から出たときの
電圧比較器9のしきい値電圧、■2′は入力位相が不感
帯■内から出たときの電圧比較器10のしきい値電圧、
■1″は入力位相が不感帯I内に入ったときの電圧比較
器9のしきい値電圧、■2″は入力位相が不惑帯I内に
入ったときの電圧比較器10のしきい値電圧である。
Here, ■,' are the threshold voltages of the voltage comparator 9 when the input phase comes out of the dead zone ■, and ■2' is the threshold voltage of the voltage comparator 10 when the input phase comes out of the dead zone ■. value voltage,
■1'' is the threshold voltage of voltage comparator 9 when the input phase falls within dead zone I; ■2'' is the threshold voltage of voltage comparator 10 when the input phase falls within dead zone I It is.

即ち、2つの受信入力の位相関係が逆相付近では不感帯
に入りにくく、同相付近では同相点からの位相誤差が小
さくなるようにしている。
That is, when the phase relationship between the two reception inputs is near opposite phases, it is difficult to enter a dead zone, and when near the same phase, the phase error from the in-phase point is made small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、2つの受信入力信号の位
相関係が位相制御の不感帯外にある場合には不感帯幅が
小さくなり、不感帯内にある場合には不惑帯幅が大きく
なることによって、同相合成時には位相制御を止め、同
相付近以外の時には同相点(位相差が0゜)からの位相
誤差の極めて小さい範囲内に位相制御を行ない、しかも
2つの受信入力信号が常に同相付近で合成され無限移相
器を不必要に制御することによる劣化を最小限に抑える
ことができる効果がある。
As explained above, in the present invention, when the phase relationship between two received input signals is outside the dead zone of phase control, the dead zone width becomes small, and when it is within the dead zone, the dead zone width becomes large. During in-phase synthesis, phase control is stopped, and when the signal is not in the vicinity of the same phase, the phase control is performed within an extremely small range of phase error from the in-phase point (phase difference is 0°), and the two received input signals are always combined in the vicinity of the same phase. This has the effect of minimizing deterioration caused by unnecessary control of the infinite phase shifter.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図(a)
及び(b)は第1図の装置における位相比較特性を示す
図、第3図は従来の同相合成スペースダイバーシティ受
信装置のブロック図、第4図の(a)乃至(C)は第3
図の装置におけ・る位相比較特性とその出力特性図であ
る。 1・・・無限移相器、2・・・電力合成器、3,4・・
・狭帯域バンドパスフィルタ、5.6・・・自動利得制
御増幅器、7・・・移相比較器、8・・・90゜移相器
、9,10・・・電圧比較器、11・・・無限移相器制
御回路、12.13・・・基準電圧発生回路。 繞81ト目 誇ぐ瞥
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
and (b) are diagrams showing the phase comparison characteristics of the device in FIG. 1, FIG. 3 is a block diagram of a conventional in-phase combining space diversity receiver, and (a) to (C) in FIG.
FIG. 3 is a diagram of the phase comparison characteristic and its output characteristic in the device shown in the figure. 1... Infinite phase shifter, 2... Power combiner, 3, 4...
・Narrowband bandpass filter, 5.6... Automatic gain control amplifier, 7... Phase shift comparator, 8... 90° phase shifter, 9, 10... Voltage comparator, 11...・Infinite phase shifter control circuit, 12.13...Reference voltage generation circuit. 81st glance

Claims (1)

【特許請求の範囲】[Claims] 1、2つのアンテナから夫々入力される2つの受信入力
信号の位相を比較する位相比較器と、この位相比較器の
出力から2つの受信入力信号間の位相の遅れを検出する
第1の電圧比較器と、同様に位相の進みを検出する第2
の電圧比較器と、これら電圧比較器の出力として得られ
る位相制御情報により前記2つの受信入力信号の位相差
を制御する制御回路とを備えた受信装置において、前記
第1および第2の電圧比較器には夫々前記位相制御情報
によって出力電圧が変化される基準電圧発生器を付設し
、この基準電圧発生器の出力電圧により第1及び第2の
電圧比較器の各しきい値電圧にヒステリシス特性を持た
せたことを特徴とする同相合成スペースダイバーシティ
受信装置。
1. A phase comparator that compares the phases of two received input signals input from two antennas, and a first voltage comparison that detects a phase delay between the two received input signals from the output of this phase comparator. and a second one that similarly detects the phase advance.
and a control circuit that controls the phase difference between the two received input signals using phase control information obtained as outputs of these voltage comparators, wherein the first and second voltage comparison A reference voltage generator whose output voltage is changed according to the phase control information is attached to each of the devices, and the output voltage of the reference voltage generator causes hysteresis characteristics to be applied to each threshold voltage of the first and second voltage comparators. What is claimed is: 1. An in-phase synthesis space diversity receiving device characterized by having:
JP1059001A 1989-03-10 1989-03-10 In-phase combining space diversity receiver Expired - Fee Related JPH0758929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1059001A JPH0758929B2 (en) 1989-03-10 1989-03-10 In-phase combining space diversity receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1059001A JPH0758929B2 (en) 1989-03-10 1989-03-10 In-phase combining space diversity receiver

Publications (2)

Publication Number Publication Date
JPH02237324A true JPH02237324A (en) 1990-09-19
JPH0758929B2 JPH0758929B2 (en) 1995-06-21

Family

ID=13100618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1059001A Expired - Fee Related JPH0758929B2 (en) 1989-03-10 1989-03-10 In-phase combining space diversity receiver

Country Status (1)

Country Link
JP (1) JPH0758929B2 (en)

Also Published As

Publication number Publication date
JPH0758929B2 (en) 1995-06-21

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