JPH11195727A - Substrate for semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform highly reliable electric inspection by providing a part mounting land which is thicker than the other part at the position of the recess position at the specified value lower than the surface position of a surface protecting film at the wiring layer on an insulating substrate, wherein the wiring layer where a surface protecting layer is provided is exposed partially. SOLUTION: The substrate for a semiconductor device has a wiring layer 12, which is formed on the substrate 11 to have the specified wiring pattern, and a solder resist layer 13 as a surface protecting layer covering approximately the entire surface of the wiring layer for exposing the wiring layer 12 partially. Then, a part mounting land, which has the surface at the recess part within the range lower than 10 μm from the surface position of a dolder resist layer 13, is formed on the surface of the exposed wiring layer 11. At this time, the insulating substrate 11 comprises the glass epoxy-resin having a thickness of 0.4 mm with the copper layer having the thickness of 35 μm on the surface. The copper layer is formed on the surface of the insulating substrate with adhesion, plating or sputtering. A nickel-gold plated layer for protection 14a is formed on the surface of a part mounting land 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate having a component mounting land and a method of manufacturing the same, and more particularly, to a semiconductor device substrate having high reliability while maintaining insulation even when the component mounting land has a high density. The present invention relates to a substrate for a semiconductor device capable of performing an electrical test with high flexibility and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the density of electronic devices has been increased as represented by electronic organizers and mobile phones. Along with this, the density of wiring patterns of a semiconductor device substrate for mounting a semiconductor chip such as an LSI has been increasing.

In this type of semiconductor device substrate, a predetermined circuit is formed by mounting a semiconductor chip. Here, if there is an abnormality in the wiring pattern of the semiconductor device substrate, the circuit does not operate normally, and the electronic device becomes defective. Therefore, usually, before mounting the semiconductor chip, the semiconductor device substrate is subjected to an electrical test by contacting a test terminal or the like with a component (semiconductor chip) mounting land to determine whether the wiring pattern is conductive or insulated. It is. Needless to say, this type of electrical inspection requires reliability of contact between the inspection terminal and the component mounting land.

FIGS. 9 and 10 are partial cross-sectional views showing a component mounting land and its peripheral structure in a semiconductor device substrate having different structures. In the structure shown in FIG. 9, a copper layer formed on an insulating substrate 1 by sticking or plating is patterned by etching, and a wiring layer 2 having a predetermined wiring pattern and a component mounting land 3 are formed. Further, a solder resist layer 4 for surface protection is provided on the wiring layer 2.
Are formed. On the component mounting land 3, a plating layer 3a of nickel-gold or the like is formed. That is,
In the structure shown in FIG. 9, the component mounting land 3 on the wiring layer 2 is formed.
The other parts are protected by the solder resist layer 4, and the component mounting lands 3 are located at a position substantially depressed from the surface of the solder resist layer 4.

On the other hand, in the structure shown in FIG. 10, a catalyst (not shown) is applied to the surface of the insulating substrate 6, and a resist layer 7 made of a photosensitive resin or the like is formed on the catalyst. A portion exposed from the resist layer 7 is subjected to electroless plating to form a wiring layer 8. Note that the resist layer 7 is used as it is as a part of the insulating layer. Then, on the exposed wiring layer 8, a plating layer 8a of nickel-gold or the like is formed. That is, in the structure shown in FIG. 10, the wiring layer 8, the component mounting lands 9, and the insulating layer 7 are formed on substantially the same plane, and the wiring layer 8 is not protected by a solder resist or the like. Note that when the wiring layer 8 is protected, the structure becomes the same as that shown in FIG. Further, the fully additive substrate is also considered to have the structure shown in FIG.

[0006]

However, in the semiconductor device substrate described above, in the structure shown in FIG. 9, the surface of the component mounting land 3 is depressed from the surface substantially by the thickness of the solder resist layer 4. In position. For this reason, when the density of the component mounting lands 3 increases along with the density of the wiring layer 2 (for example, there is a high-density land having a land width of 35 μm and a gap between lands of 50 μm). At the time of inspection, the solder resist layer 4 around the land 3 becomes an obstacle, causing a problem that the inspection terminal to be brought into contact with the land 3 does not sufficiently contact.

That is, in the structure shown in FIG. 9, the component mounting lands 3 are larger in thickness than the solder resist layer 4 by the thickness thereof.
Since the solder resist layer 4 is located at the concave position, the solder resist layer 4 is thick,
When the dimensions of the land 3 are small, the inspection terminal
And electrical inspection becomes difficult.

In particular, when the component mounting land 3 and the inspection terminal are brought into contact with each other via a conductive elastic material such as an anisotropic conductive rubber in order to increase the reliability of the contact, the contact is more difficult. Becomes Further, when the solder resist layer 4 is made thin, pinholes and the like are generated, and there is a possibility that the wiring layer 2 is exposed, and there is a problem that the insulating property is reduced.

When gold plating is performed on the surface of the component mounting land 3, it is usually 15 to 2 to withstand the gold plating.
The solder resist layer 4 must be formed with a thickness of about 0 μm.

On the other hand, in the structure shown in FIG. 10, since the component mounting lands 9 are on the same plane as the wiring layer 8 and the insulating layer 7, electrical inspection is possible, but the surface of the wiring layer 8 is formed of a solder resist layer. Since it is not protected, there is a problem that there is concern about the insulating properties of the surface. Also, the component mounting land 3
In the case where Au plating is applied to protect the wiring, the plating layer 8a is formed also on the wiring layer 2 other than the land 3, so that there is a problem that the cost is increased. On the other hand, if the solder resist layer is printed on the wiring layer 8 other than the land 9, the structure becomes the same as the structure shown in FIG. 9 and the electrical inspection becomes difficult.

If the component mounting lands 3 protrude from the solder resist layer 4, the manufacturing apparatus or the substrates come into contact with each other during the manufacturing process or transportation of the semiconductor device substrate, and the surface of the land is damaged. There is a disadvantage that.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and provides a semiconductor device substrate capable of performing an electrical test with high reliability while maintaining insulation even when component mounting lands are dense. And a method for producing the same.

[0013]

The gist of the present invention is that a surface protection layer is formed on a wiring layer other than a component mounting land, and the component mounting land is recessed within 10 μm or less of the surface protection layer. An object of the present invention is to perform an electrical test with high reliability while maintaining the insulation property by the configuration formed in advance.

As a structure for projecting the component mounting land, for example, a structure in which a wiring layer other than the component mounting land is thinned by half etching or the like and a surface protective layer is provided thereon, or a component mounting land is provided. A configuration in which the surface protection layer is provided on the wiring layer other than the land area while the thickness of the land area to be formed is increased by forming a conductor layer is conceivable.

Based on the gist of the present invention as described above, the following means are specifically taken. The invention corresponding to claim 1 is an insulating substrate, a wiring layer formed with a predetermined wiring pattern on the insulating substrate, and partially exposing the wiring layer and substantially the entire surface of the wiring layer. A surface protection layer that covers the exposed wiring layer,
And a component mounting land which is formed thicker than other portions of the wiring layer and has a surface at a position depressed within a range of 10 μm or less from the surface position of the surface protection layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the first aspect.
(A) using an insulating substrate having a copper layer formed on its surface, and selectively forming a first resist layer on the copper layer;
(B) after the formation of the first resist layer, selectively etching the copper layer to form the wiring layer; and (C)
Removing the first resist layer after the formation of the wiring layer, and forming a second resist layer on a land area serving as the component mounting land on the wiring layer; and (D) forming the second resist layer. After forming, a step of thinning the wiring layer other than the land area by half etching; and (E) removing the second resist layer after the completion of the half etching,
Forming the surface protection layer on the thinned wiring layer.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device substrate according to the first aspect.
(A) using an insulating substrate, forming a copper layer over substantially the entire surface of the insulating substrate, and then selectively forming a first resist layer on the copper layer; and (B) exposing between the first resist layer Forming a wiring layer on the formed copper layer, (C) forming a second resist layer selectively on the first resist layer and the wiring layer, and (D) forming a second resist layer between the second resist layer. Forming a component mounting land on the exposed wiring layer;
(E) removing the first and second resist layers;
(F) a step of removing a portion of the copper layer other than the wiring layer by soft etching, and (G) a step of forming a surface protection layer on the wiring layer other than the component mounting land and the insulating substrate. And a method for manufacturing a semiconductor device substrate.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device substrate according to the first aspect,
(A) An insulating substrate is used, and the first substrate is selectively placed on the insulating substrate.
Forming a resist layer, (B) forming a wiring layer on the insulating substrate exposed between the first resist layers, and (C) selectively forming a wiring layer on the first resist layer and the wiring layer. (D) forming the second resist layer;
Forming a component mounting land on the wiring layer exposed between the resist layers; (E) stripping the first and second resist layers; and (F) wiring layers other than the component mounting land. Forming a surface protective layer on the insulating substrate.

(Operation) Therefore, in the invention corresponding to claim 1, the surface protection layer is formed on the wiring layer other than the component mounting land by taking the above-described means. Even at high densities, insulation can be maintained, and the land for component mounting is one layer thicker than the surface protection layer.
Since the recess is formed within the range of 0 μm or less, the electrical inspection can be performed with high reliability.

According to a second aspect of the present invention, after the wiring layer is formed, the wiring layer other than the land area is thinned, and the surface protection layer is formed on the thinned wiring layer. Thus, a structure having the function of acting can be easily and reliably manufactured.

Further, the invention according to claim 3 is a step of forming a copper layer over substantially the entire surface, a step of selectively forming a wiring layer on the copper layer, and a step of soft-etching the copper layer other than the wiring layer. Since the method includes the step of removing, a structure having the function corresponding to claim 1 can be easily and reliably manufactured by the semi-additive method.

Further, since the invention corresponding to claim 4 includes a step of selectively forming a wiring layer on an insulating substrate, a structure having the function corresponding to claim 1 can be easily formed by a full additive method. And it can manufacture reliably.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing the structure of a semiconductor device substrate according to a first embodiment of the present invention. This semiconductor device substrate includes an insulating substrate 11, a wiring layer 12 formed on the insulating substrate 11 with a predetermined wiring pattern, a wiring layer 12 partially exposed, and substantially the entire surface of the wiring layer 12. And a component mounting land formed on the exposed surface of the wiring layer 12 and protruding from the surface position of the solder resist layer 13 within a range of 10 μm or less from the surface of the solder resist layer 13. 14 is provided.

Here, the insulating substrate 11 is made of a 0.4 mm thick glass epoxy having a 35 μm thick copper layer on the surface, and here, CCL-EL170 (manufactured by Mitsubishi Gas Chemical) is used. . Note that the copper layer may be formed on the surface of the insulating substrate 11 by any method such as sticking, plating, or sputtering. Also, the insulating substrate 11
It may be a multilayer wiring board in which wiring has already been formed. The method of forming these copper layers and the modified examples of the insulating substrate 11 are as follows.
This is common to other embodiments.

The component mounting land 14 has a nickel-gold plating layer 14a for protection formed on the surface.

Next, a method of manufacturing such a semiconductor device substrate and its operation will be described with reference to FIGS. Now, as shown in FIG. 2 (a), an insulating substrate 11 having a copper layer 12a on its surface is prepared, and mechanical polishing with a buff and a mixed aqueous solution of sulfuric acid and hydrogen peroxide are performed in order to improve the adhesion to a dry film. Chemical polishing is performed. As shown in FIG. 2B, a dry film as a first resist layer (manufactured by Hitachi Chemical Co., Ltd., product name: PHOTEC) is formed on both sides of the insulating substrate 11.
15 is stuck.

Subsequently, a pattern film (not shown) is superposed, irradiated with UV light, and developed with a sodium carbonate solution. As shown in FIG. 2C, a dry film 15 on the copper layer 12a is desired. Is formed in the same pattern as the wiring pattern.

Further, a copper (II) chloride solution is sprayed, and the exposed portion of the copper layer 12a is corroded and removed to form the wiring layer 12. Further, a 5% NaOH solution is sprayed thereon to completely remove the dry film 15, and the wiring layer 12 is exposed as shown in FIG.

Next, as shown in FIG. 2E, a dry film (manufactured by Asahi Kasei Kogyo Co., Ltd., trade name: Sunfort) 16 is adhered to both surfaces as a second resist layer. The dry film 16 is of a type that sufficiently softens at the time of sticking and follows the unevenness in order to embed the unevenness of the wiring layer 12, and has a thickness of 50 μm which is thicker than the thickness of the wiring layer 12.

Next, as shown in FIG. 3A, through the same UV irradiation and development steps as described above, the component mounting lands 14 are formed.
The dry film 16 is removed except for the region where

The exposed wiring layer 12 was formed thin by half etching in the same spraying step of the cupric chloride solution as described above.
The etching time was adjusted to be 8 μm thick. Then, similarly, as shown in FIG. 3B, the dry film 16 is removed by a spraying step of a 5% NaOH solution.

As a solder resist, PSR-4000 is used.
(Made by Taiyo Ink Manufacturing Co., Ltd.) on a flat surface
By developing, the solder resist on the component mounting land 14 is removed, and as shown in FIG.
Formed to protect the The solder resist is printed on a flat insulating substrate on which the wiring layer 12 is not formed, baked at 90 ° C. for 30 minutes, exposed and developed, and further baked at 130 ° C. for 60 minutes. The test was performed under the condition of a thickness of 25 μm.

Thereafter, as shown in FIG. 1, a 2 μm thick Ni plating and 0.05
Au plating having a thickness of μm is sequentially applied to form a plating layer 14a, and a semiconductor device substrate is completed. Here, as shown in an enlarged manner in FIG. 4, when the thickness of the component mounting land 14 was measured, it was 30 μm. Also, when the thickness of the wiring layer 12 thinned by half etching was measured together with the thickness of the solder resist layer 13 formed thereon,
It was 35 μm.

As a result, at the time of the electrical inspection, the inspection terminals can be reliably brought into contact with the component mounting lands without being interrupted by the solder resist layer. An inspection can be performed. For example,
Inspection was performed by contacting 100 terminals of the semiconductor device according to the present embodiment with the inspection terminals, but no inspection defects considered to be caused by poor contact of the inspection terminals did not occur. Since there is almost no difference in height between the solder resist layer 13 and the component mounting land 14, an electrical inspection can be easily performed.

Since the surface of the wiring layer 12 other than the component mounting lands 14 is covered with the solder resist layer 13, migration of the surface layer hardly occurs.
Insulation can be maintained.

Further, the strength of the land 14 is increased due to the structure in which the component mounting land 14 is formed thick, so that the stability of mounting the component by wire bonding or the like can be improved.

As described above, according to the present embodiment, since the solder resist layer 13 is formed on the wiring layer 12 other than the component mounting lands 14, even when the component mounting lands 14 are formed with high density, The insulating property can be maintained, and the component mounting land 14 is 10 μm thicker than the solder resist layer 13.
m, the electrical inspection can be performed with high reliability.

After the formation of the wiring layer 12, the wiring layer other than the land 14 region is thinned, and the solder resist layer 13 is formed on the thinned wiring layer 12, whereby the structure shown in FIG. It can be manufactured reliably.

(Second Embodiment) FIG. 5 is a sectional view showing the structure of a semiconductor device substrate according to a second embodiment of the present invention. The semiconductor device substrate includes an insulating substrate 21, a lower wiring layer 22 formed on the insulating substrate 21 with a predetermined wiring pattern, and a via hole 2 of the lower wiring layer 22.
3, an insulating layer 24 covering substantially the entire lower wiring layer 22 and another wiring pattern on the insulating layer 24, and via a via hole 23, the lower wiring layer Upper wiring layer 25 formed to be connected to 22
A solder resist layer 26 that partially exposes the upper wiring layer 25 and covers substantially the entire upper wiring layer 25; and a solder resist layer 26 formed on the exposed surface of the upper wiring layer 25, And a component mounting land 27 having a surface at a concave position within a range of 10 μm or less.

Here, the insulating substrate 21 is made of a 0.4 mm thick glass epoxy having a 18 μm thick copper layer on the surface. The insulating layer 24 is formed by applying, exposing, and developing an insulating resin ink. As the insulating resin ink, PSR-4000 (manufactured by Taiyo Ink Mfg. Co., Ltd.) is used here.

As described above, the component mounting land 27 has a nickel-gold plating layer 27a for protection formed on the surface.

Next, a method of manufacturing such a semiconductor device substrate and its operation will be described with reference to FIGS. Similarly to the above, as shown in FIG. 6A, the lower wiring layer 22 is formed on the insulating substrate 21 by etching the copper layer on the insulating substrate 21. However, the thickness of the lower wiring layer 22 is 18 μm. Subsequently, the dry film 28 is attached to the back surface of the insulating substrate 21, and the insulating resin ink is applied to the surface of the insulating substrate 21 to a thickness of about 50 μm. The insulating resin ink on the surface is exposed and developed as described above. Thus, as shown in FIG. 6B, an insulating layer 24 is formed on the lower wiring layer 22 while exposing a portion to be the via hole 23.

After the surface of the insulating layer 24 is roughened by a solution containing potassium permanganate, as shown in FIG. 6C, a copper film 25a having a thickness of 0.5 μm is formed on the entire surface by electroless copper plating. Is done. The dry film 28 on the back side
Is peeled off.

Next, a copper film 2 on the surface is used as a first resist layer.
A dry film having a thickness of 25 μm is adhered on 5a, and a dry film 29 is similarly adhered on the back surface. FIG.
As shown in (d), the dry film 2 on the copper film 25a
9 is formed into a reverse pattern for exposing the wiring pattern of the upper wiring layer 25 by the same exposure and development as described above.

As shown in FIG. 7A, electrolytic copper plating is performed, and the copper film 25a exposed from the dry film 29 is formed.
A copper layer 25b having a thickness of 27 μm is deposited thereon. A dry film 30 is adhered as a second resist layer on the first resist layer and the copper layer 25b, and is exposed and developed in the same manner as described above, as shown in FIG. The dry film 30 is formed in a reverse pattern for exposing the copper layer 25b.

As shown in FIG. 7C, a component mounting land 27 is formed by performing electrolytic copper plating and depositing a 4 μm thick copper layer on the exposed copper layer 25a. Subsequently, a NaOH solution is sprayed by spraying, and the dry films 29 and 30 as the first and second resist layers are peeled off to expose the copper film 25a. This copper film 25a
As shown in FIG. 7D, exposed portions are removed by soft etching.

In the same manner as described above, as shown in FIG. 7 (e), the first
The solder resist layer 26 is formed on the entire surface under the same conditions as those of the embodiment.
Is formed. Similarly, as shown in FIG.
Ni plating with a thickness of m and Au plating with a thickness of 0.05 μm are sequentially applied to form a plating layer 27a, thereby completing a semiconductor device substrate.

In this semiconductor device substrate, as shown in FIG. 8, the component mounting land 27 has a thickness of 30 μm, and the total thickness of the wiring layer around the component mounting land 27 and the solder resist layer 26 thereon. Was 40 μm.

As a result, the semiconductor device substrate can be easily subjected to an electrical test with high reliability similarly to the first embodiment, and the insulating property can be maintained by the solder resist layer 26. Can be. Similarly, the mounting stability can be improved by the thick component mounting land 27. Also, as in the first embodiment, 100 semiconductor device substrates according to the present embodiment were inspected by contacting the inspection terminals. However, inspection defects considered to be caused by poor contact of the inspection terminals occurred. Did not.

As described above, according to the second embodiment,
A semiconductor device substrate that can obtain the same operation and effect as the first embodiment can be easily and reliably manufactured by the semi-additive method.

(Third Embodiment) The third embodiment is based on the full additive method, and the semiconductor device substrate is the same as the second embodiment, that is, FIG.

As for the manufacturing method, only points different from the second embodiment will be described.

First, in FIG. 6C, a 25 μm-thick dry film is stuck on the roughened insulating layer 24 without performing the step of forming electroless copper plating on the entire surface. It is the second that the dry film 29 is stuck on the back side.
This is the same as the embodiment.

Then, a copper layer 25b formed on the insulating layer 24 exposed in FIG. 7A is formed with a thickness of 25 μm.

Further, a 6 μm thick copper layer is deposited on the copper layer 25 exposed in FIG.
To form

In the third embodiment, flux was applied to the surface of the component mounting land without performing Ni plating or Au plating. Of course, a step of applying Ni plating or Au plating may be adopted.

As in the second embodiment, the thickness of the component mounting land 27 and the total thickness of the wiring layer and the solder resist layer 26 around the component mounting land 27 were measured to be 30 μm and 40 μm, respectively. Met.

As described above, according to the third embodiment, it is possible to easily and surely manufacture a semiconductor device substrate capable of obtaining the same operational effects as those of the first and second embodiments by the full additive method. Can be.

(Other Embodiments) The first to third embodiments
In the embodiment, the case where one build-up layer composed of an insulating layer and a wiring layer is provided is described. However, the present invention is not limited to this, and the present invention can be similarly applied to a configuration in which a plurality of build-up layers are stacked. The same effect can be obtained by implementing the present invention.

In the first to third embodiments,
The substrate structure having the wiring layer and the component mounting land on only one side has been described. However, the present invention is not limited to this. The wiring layer and the component mounting land are provided on both sides, and the wiring layer between both sides is electrically connected through a through hole. Even if the board structure is connected to
The present invention can be implemented in a similar manner to obtain similar effects.

That is, according to the present invention, if a surface protection layer is formed on a wiring layer other than the component mounting land, and the component mounting land has a surface structure formed so as to protrude from the surface protection layer, It also includes a configuration in which the internal structure is modified (for example, a build-up layer on both sides, a plurality of build-up layers, a multilayer wiring board having wiring inside, or a substrate material other than glass epoxy).

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0064]

As described above, according to the present invention, even when the component mounting lands have a high density, a semiconductor device substrate capable of executing an electrical inspection with high reliability while maintaining insulation and a semiconductor device substrate having the same. A manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device substrate according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining the manufacturing method in the embodiment.

FIG. 3 is a process cross-sectional view for explaining the manufacturing method in the embodiment.

FIG. 4 is an enlarged cross-sectional view for explaining a configuration of a component mounting land in the embodiment.

FIG. 5 is a sectional view showing a configuration of a semiconductor device substrate according to a second embodiment of the present invention;

FIG. 6 is a process cross-sectional view for explaining the manufacturing method in the embodiment.

FIG. 7 is a process cross-sectional view for explaining the manufacturing method in the same embodiment.

FIG. 8 is an enlarged cross-sectional view for explaining a configuration of a component mounting land according to the embodiment.

FIG. 9 is a partial cross-sectional view showing a conventional component mounting land and its peripheral configuration.

FIG. 10 is a partial cross-sectional view showing a conventional component mounting land and its peripheral configuration.

[Explanation of symbols]

 11, 21 ... insulating substrate 12 ... wiring layer 12a, 25b ... copper layer 13, 26 ... solder resist layer 14, 27 ... component mounting land 14a, 27a ... plating layer 15, 16, 28, 29, 30 ... dry film 22 ... lower wiring layer 23 ... via hole 24 ... insulating layer 25 ... upper wiring layer 25a ... copper film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jun Kawana 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd. (72) Inventor Akira Ogawa 1-1-5-1, Taito, Taito-ku, Tokyo Letterpress Printing Co., Ltd.

Claims (4)

[Claims] An insulating substrate; a wiring layer formed on the insulating substrate with a predetermined wiring pattern; and a surface protection for partially exposing the wiring layer and covering substantially the entire surface of the wiring layer. A component mounting part formed on the exposed surface of the wiring layer and thicker than the other part of the wiring layer, and having a surface at a position depressed by 10 μm or less from the surface position of the surface protection layer. And a semiconductor device substrate. 2. The method of manufacturing a semiconductor device substrate according to claim 1, wherein (A) using an insulating substrate having a copper layer formed on a surface thereof, selectively forming a first resist layer on the copper layer. And (B) selectively etching the copper layer after forming the first resist layer to form the wiring layer; and (C) forming the first resist layer after forming the wiring layer. Forming a second resist layer on a land region that becomes the component mounting land on the wiring layer;
(D) a step of thinning the wiring layer other than the land area by half-etching after the formation of the second resist layer; and (E) removing the second resist layer after the completion of the half-etching. Forming the surface protection layer on the formed wiring layer. 3. The method of manufacturing a semiconductor device substrate according to claim 1, wherein (A) using an insulating substrate, forming a copper layer on substantially the entire surface of the insulating substrate, and then selectively forming the copper layer on the copper layer. Forming a first resist layer; and (B) forming a wiring layer on the copper layer exposed between the first resist layers;
(C) a step of selectively forming a second resist layer on the first resist layer and the wiring layer; and (D) forming a component mounting land on the wiring layer exposed between the second resist layers. (E) removing the first and second resist layers, (F) removing the copper layer other than the wiring layer by soft etching, and (G) the component mounting land. Forming a surface protective layer on the wiring layer and the insulating substrate other than the above-mentioned insulating substrate. 4. The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein (A) using an insulating substrate, selectively forming a first resist layer on the insulating substrate;
Forming a wiring layer on the insulating substrate exposed between the first resist layers; and (C) selectively forming a second resist layer on the first resist layers and the wiring layers.
(D) forming a component mounting land on the wiring layer exposed between the second resist layers; (E) removing the first and second resist layers; and (F) forming the component mounting land. Forming a surface protective layer on the wiring layer other than the land and on the insulating substrate.