JPH05145238A - Thin film formation of ceramic substrate - Google Patents

Thin film formation of ceramic substrate

Info

Publication number
JPH05145238A
JPH05145238A JP30750291A JP30750291A JPH05145238A JP H05145238 A JPH05145238 A JP H05145238A JP 30750291 A JP30750291 A JP 30750291A JP 30750291 A JP30750291 A JP 30750291A JP H05145238 A JPH05145238 A JP H05145238A
Authority
JP
Japan
Prior art keywords
film
conductor
layer
collective
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP30750291A
Other languages
Japanese (ja)
Inventor
Makoto Fujikawa
藤川  誠
Shuntaro Takizawa
俊太郎 滝澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP30750291A priority Critical patent/JPH05145238A/en
Publication of JPH05145238A publication Critical patent/JPH05145238A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To bring formed pads and collective layers surely in continuity through conductor vias by firmly connecting a conductor via formed by plating to the top face of a collective layer and by bringing a conductor film coating the top face of an insulating layer serving as an interlayer insulating film in continuity to a conductor via exposed from the top face of the insulating layer. CONSTITUTION:The top face of a collective layer 1-1 of a substrate 1 is plated by a coat with a plating resist film 12 having a via lower hole 12-1, thereby making a conductor via 13 of constant level project out of the top face of the collective layer 1-1. After the resist film 12 is removed, photosensitive polyimide is applied; when the whole surface of a polyimide film 14' is etched by dryetching or the like, an insulating layer 14 is formed with exposure of a conductor via 13. Since coating the whole surface of this insulating layer 14 with a conductor film 15' enables a coat of the conductor film 15' of continuity to the conductor via 13, this conductor film 15' is wetetched or the like to form a pad 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種電子機器の構成に
広く使用されるセラミック基板の薄膜形成方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a thin film on a ceramic substrate which is widely used in the construction of various electronic devices.

【0002】最近、各種電子機器等に装着されるプリン
ト板ユニットには高集積化された電子部品が高密度に実
装されるに伴って、この電子部品を実装する回路基板は
セラミック基板(以下基板と略称する)に層間接続用の
ビア導体と電子部品接合用の微小なパッドをそれぞれ高
密度に形成した薄膜を積層したものが多く使用されるよ
うになっている。
Recently, as highly integrated electronic components are mounted at high density on a printed circuit board unit mounted on various electronic devices, a circuit board on which the electronic components are mounted is a ceramic substrate (hereinafter referred to as substrate). (Hereinafter abbreviated as "), a multi-layered structure in which a via conductor for interlayer connection and a fine pad for joining electronic components are respectively formed at high density is laminated.

【0003】そのために、セラミック基板に液状ポリイ
ミド樹脂を塗布した層間絶縁層に導体ビアを形成するビ
ア下孔の形成方法は、層間絶縁層に感光性のポリイミド
樹脂を使用して感光,現像によりビア下孔を形成してい
るが、ポリイミド樹脂の現像に際してビア下孔の貫通不
完全が発生して層間絶縁層のパッドとの導通不良が生じ
ているため、セラミック基板のコレクティブ層と前記層
間絶縁層に形成されるパッドとが確実に導通する新しい
セラミック基板の薄膜形成方法が必要とされている。
Therefore, a method of forming a via hole in which a conductive via is formed in an interlayer insulating layer in which a liquid polyimide resin is applied to a ceramic substrate is as follows. Although a pilot hole is formed, incomplete penetration of the via pilot hole occurs during the development of the polyimide resin, resulting in poor electrical continuity with the pad of the interlayer insulating layer. Therefore, the collective layer of the ceramic substrate and the interlayer insulating layer are formed. There is a need for a new method for forming a thin film on a ceramic substrate, which ensures reliable conduction with a pad formed on the substrate.

【0004】[0004]

【従来の技術】従来広く使用されているセラミック基板
の薄膜形成方法を、図2の工程順側断面図で説明する。
2. Description of the Related Art A method of forming a thin film on a ceramic substrate, which has been widely used in the past, will be described with reference to FIG.

【0005】(a) は、微細なコレクティブ層1-1 を表面
に形成した厚膜の基板1に対して、この基板1と前記コ
レクティブ層1-1 の上面に感光性の液状ポリイミド樹脂
を塗布して薄膜の絶縁第一層2を形成した状態。
(A) is a thick-film substrate 1 having a fine collective layer 1-1 formed on the surface thereof, and a photosensitive liquid polyimide resin is applied to the upper surface of the substrate 1 and the collective layer 1-1. Then, the thin insulating first layer 2 is formed.

【0006】(b) は、この絶縁第一層2の上面に図示し
ていない第一次のビア孔形成用マスクを密着させて露光
し、専用の現像液に浸漬して超音波等を照射することに
より絶縁第一層2に第一次ビア下孔2-1 を形成して、仮
ベーキングを行った状態。
In (b), a mask for forming a primary via hole (not shown) is brought into close contact with the upper surface of the insulating first layer 2 for exposure, and it is immersed in a dedicated developing solution for irradiation with ultrasonic waves or the like. By doing so, the primary via hole 2-1 is formed in the insulating first layer 2 and the temporary baking is performed.

【0007】(c) は、第一次ビア下孔2-1 が形成された
絶縁第一層2の上面に、(a) 項と同様な感光性の液状ポ
リイミド樹脂を塗布して薄膜の絶縁第二層3を形成した
状態。
(C) is a thin film insulation by applying a photosensitive liquid polyimide resin similar to (a) to the upper surface of the insulating first layer 2 in which the primary via hole 2-1 is formed. The state in which the second layer 3 is formed.

【0008】(d) は、この絶縁第二層3の上面を図示し
ていない第二次ビア形成用マスク用いて露光し、再び専
用の現像液に浸漬して超音波等を照射することにより段
付きのビア下孔3-1 を形成して、その後にハードベーキ
ングを行った状態。
In (d), the upper surface of the insulating second layer 3 is exposed by using a mask for forming a secondary via (not shown), immersed in a dedicated developer again, and irradiated with ultrasonic waves or the like. A state in which a stepped via pilot hole 3-1 is formed and then hard baking is performed.

【0009】(e) は、カソードスパッタリング等により
上記段付きのビア下孔3-1 に銅等の導体金属を充填して
導体ビア4を形成した後に、無電解銅めっきにより導体
ビア4と導通した導体膜5'を絶縁第二層3の全面に形成
し、この導体膜5'の上面にめっき用のレジストを薄く塗
布して、露光により形成しようするパッドと同一寸法に
導体膜5'を被膜したレジスト膜6を形成した状態。
(E) is a conductive via 4 formed by filling the stepped via lower hole 3-1 with a conductive metal such as copper by cathode sputtering or the like, and then conducting with the conductive via 4 by electroless copper plating. Formed conductive film 5'on the entire surface of the insulating second layer 3, a thin coating of resist is applied on the upper surface of the conductive film 5 ', and the conductive film 5'is formed to the same size as the pad to be formed by exposure. The state where the coated resist film 6 is formed.

【0010】(f) は、このレジスト膜6から露出した導
体膜5'をウエットエッチングにより溶解, 除去して絶縁
第二層3の上面にパッド5を形成した状態。の工程によ
りセラミック基板の表面に薄膜が形成されている。
(F) is a state in which the conductor film 5'exposed from the resist film 6 is dissolved and removed by wet etching to form the pad 5 on the upper surface of the second insulating layer 3. A thin film is formed on the surface of the ceramic substrate by the process of.

【0011】[0011]

【発明が解決しようとする課題】以上説明した従来の薄
膜形成方法で問題となるのは、図2(a) 〜(d) に示す如
く基板1の表面に感光性の液状ポリイミド樹脂を塗布し
てビア形成部を露光し、これを専用の現像液に浸漬して
超音波等を照射する現像法でビア下孔3-1 を形成してい
るが、図3に示すように超音波の照射具合やベーク等の
諸原因によりポリイミド樹脂が残留して基板1に形成さ
れたコレクティブ層1-1 を露出する上記ビア下孔3-1 が
形成されない箇所が発生する。
The problem with the conventional thin film forming method described above is that a photosensitive liquid polyimide resin is applied to the surface of the substrate 1 as shown in FIGS. 2 (a) to 2 (d). The via formation hole 3-1 is formed by a developing method in which the via formation part is exposed to light, and this is immersed in a dedicated developer to irradiate with ultrasonic waves, but as shown in FIG. Due to various factors such as the condition and baking, the polyimide resin remains and there is a portion where the via hole 3-1 for exposing the collective layer 1-1 formed on the substrate 1 is not formed.

【0012】そのため、絶縁第二層3の上面に形成され
るパッド5との間の導通がなくなるから、絶縁第二層3
の露光,現像の再処理を行うことにより補修している
が、この再処理を行ってもコレクティブ層1-1 が露出し
ない場合は不良として基板1を廃却しているので薄膜形
成費が高騰するという問題が生じている。
Therefore, the electrical connection between the second insulating layer 3 and the pad 5 formed on the upper surface of the second insulating layer 3 is lost.
It is repaired by performing re-treatment of exposure and development, but if the collective layer 1-1 is not exposed even after performing this re-treatment, the substrate 1 is discarded as a defect and the thin film formation cost rises. There is a problem of doing.

【0013】本発明は上記のような問題点に鑑み、絶縁
層の表面にコレクティブ層と確実に導通したパッドを形
成することができる新しいセラミック基板の薄膜形成方
法の提供を目的とする。
In view of the above problems, it is an object of the present invention to provide a new method for forming a thin film on a ceramic substrate, which can form a pad on the surface of an insulating layer that is surely electrically connected to the collective layer.

【0014】[0014]

【課題を解決するための手段】本発明は、図1に示すよ
うに基板1およびコレクティブ層1-1 上面にビア下孔12
-1を有するめっき用のレジスト膜12を被膜させてメッキ
により一定高さの導体ビア13を当該コレクティブ層1-1
の上面に突出させて、前記レジスト膜12を除去した後に
上記基板1, 該コレクティブ層1-1 および前記導体ビア
13の上面を覆う感光性のポリイミド膜14' を施し、当該
ポリイミド膜14' の全表面をドライエッチングして該導
体ビア13の上面を露出させた絶縁層14を形成して、スパ
ッタリングおよび無電解めっきにより該導体ビア13と導
通した導体膜15' を絶縁層14の全面に被膜させ、この導
体膜15' をエッチング等により溶解, 除去して絶縁層14
の上面にパッド15を形成する。
According to the present invention, as shown in FIG. 1, a via hole 12 is formed on the upper surface of a substrate 1 and a collective layer 1-1.
-1 is coated with a resist film 12 for plating, and a conductive via 13 having a constant height is formed by plating on the collective layer 1-1.
Of the substrate 1, the collective layer 1-1 and the conductive via after the resist film 12 is removed by projecting the resist film 12 onto the upper surface of the substrate 1.
A photosensitive polyimide film 14 ′ that covers the upper surface of 13 is formed, and the entire surface of the polyimide film 14 ′ is dry-etched to form an insulating layer 14 that exposes the upper surface of the conductor via 13, and sputtering and electroless plating are performed. A conductive film 15 'which is electrically connected to the conductive via 13 is coated on the entire surface of the insulating layer 14 by plating, and the conductive film 15' is dissolved and removed by etching or the like to remove the insulating layer 14 '.
Pad 15 is formed on the upper surface of the.

【0015】[0015]

【作用】本発明では、基板1のコレクティブ層1-1 上面
にビア下孔12-1を有するめっき用レジスト膜12を被膜さ
せてめっきすることより、一定高さの導体ビア13を当該
コレクティブ層1-1 の上面から突出させ、前記レジスト
膜12を除去した後に感光性のポリイミドを施してドライ
エッチング等により当該ポリイミド膜14' の全表面をエ
ッチングすると該導体ビア13が露出した絶縁層14が形成
され、この絶縁層14の全面に導体膜15' を絶縁層14の全
面に被膜させると当該導体ビア13と導通した導体膜15'
が被膜されるから、この導体膜15' をウエットエッチン
グ等によりパッド15を形成することで前記コレクティブ
層1-1 と確実に導通したパッドを有する薄膜を形成する
ことが可能となる。
In the present invention, the conductive vias 13 having a constant height are formed by coating the plating resist film 12 having the via lower holes 12-1 on the upper surface of the collective layer 1-1 of the substrate 1 and plating. 1-1 is projected from the upper surface, and after removing the resist film 12, a photosensitive polyimide is applied and the entire surface of the polyimide film 14 'is etched by dry etching or the like to form an insulating layer 14 in which the conductor via 13 is exposed. When the entire surface of the insulating layer 14 is covered with the conductive film 15 ′, the conductive film 15 ′ is electrically connected to the conductive via 13.
Since the conductor film 15 'is coated with the conductive film 15' by forming the pad 15 by wet etching or the like, it is possible to form a thin film having a pad electrically connected to the collective layer 1-1.

【0016】[0016]

【実施例】以下図面に示した実施例に基づいて本発明を
詳細に説明する。図1は本実施例によるセラミック基板
の薄膜形成方法を工程順の側断面図で示し、図中におい
て、図2と同一部材には同一記号が付してある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on the embodiments shown in the drawings. FIG. 1 is a side sectional view showing a method of forming a thin film on a ceramic substrate according to this embodiment in the order of steps, in which the same members as those in FIG. 2 are designated by the same reference numerals.

【0017】本発明の薄膜形成方法は、図1の(a) に示
すように、微細なコレクティブ層1-1 を表面に形成した
厚膜の基板1に対し、この基板1と前記コレクティブ層
1-1の上面にめっき用のレジストを塗布して図示してい
ないビア孔形成用マスクでこのレジストを露光すること
により、上記コレクティブ層1-1 が微細径,例えば30
〜130μm露出するのビア下孔12-1を有しためっき用
のレジスト膜12を被膜させた状態。
In the thin film forming method of the present invention, as shown in FIG. 1 (a), a thick film substrate 1 having a fine collective layer 1-1 formed on the surface thereof is used for the substrate 1 and the collective layer.
By coating a resist for plating on the upper surface of 1-1 and exposing this resist with a via hole forming mask (not shown), the collective layer 1-1 has a fine diameter, for example, 30
A state in which a resist film 12 for plating having a via hole 12-1 exposed to 130 μm is coated.

【0018】(b) は、上記レジスト膜12より露出した前
記コレクティブ層1-1 の上面に対して、銅の電解メッキ
により20〜30μm高さの導体ビア13を形成した状
態。(c) は、上記めっき用のレジスト膜12を除去した後
に、感光性の液状ポリイミド樹脂を20〜30μm塗布
して上記基板1と該コレクティブ層1-1 および前記導体
ビア13の上面を覆ったポリイミド膜14' を形成した状
態。
(B) shows a state in which a conductive via 13 having a height of 20 to 30 μm is formed on the upper surface of the collective layer 1-1 exposed from the resist film 12 by copper electrolytic plating. (c) shows that after the resist film 12 for plating is removed, a photosensitive liquid polyimide resin is applied in an amount of 20 to 30 μm to cover the upper surface of the substrate 1, the collective layer 1-1 and the conductor via 13. The state where the polyimide film 14 'is formed.

【0019】(d) は、リアクティブ−イオン−エッチン
グ(RIE)等のドライエッチングにより上記ポリイミ
ド膜14' の全表面を約2〜5μm除去して前記導体ビア
13の上面を露出させた絶縁層14を形成した状態。
(D) shows that the entire surface of the polyimide film 14 'is removed by about 2 to 5 .mu.m by dry etching such as reactive-ion-etching (RIE) to remove the conductor vias.
A state in which an insulating layer 14 exposing the upper surface of 13 is formed.

【0020】(e) は、カソードスパッタリングおよび無
電解めっきにより絶縁層14の全面に導体ビア13と導通し
た約5μmの銅よりなる導体膜15' を形成して、この導
体膜15' の上面にめっき用のレジストを薄く塗布して露
光することにより、形成されるパッドと同一寸法の導体
膜15' を被膜するレジスト膜16を形成した状態。
In (e), a conductor film 15 'made of copper having a thickness of about 5 .mu.m is formed on the entire surface of the insulating layer 14 by cathode sputtering and electroless plating, and the conductor film 15' is formed on the upper surface of the conductor film 15 '. A state in which a resist film 16 covering the conductor film 15 ′ having the same size as the pad to be formed is formed by thinly applying a resist for plating and exposing it.

【0021】(f)は、このレジスト膜16から露出した導
体膜15' をウエットエッチングにより溶解, 除去するこ
とにより絶縁層14の上面にパッド15を形成した状態。の
工程によりセラミック基板の表面に薄膜が形成されてい
る。
(F) shows a state where the pad 15 is formed on the upper surface of the insulating layer 14 by dissolving and removing the conductor film 15 ′ exposed from the resist film 16 by wet etching. A thin film is formed on the surface of the ceramic substrate by the process of.

【0022】その結果、めっきにより形成された導体ビ
ア13はコレクティブ層1-1 の上面と強固に接続されると
ともに、層間絶縁膜となる絶縁層14の上面に被膜される
導体膜15' はその絶縁層14の上面から露出した前記導体
ビア13と確実に導通するから、ウエットエッチング等に
より形成されるパッド15とコレクティブ層1-1 は該導体
ビア13を介して確実導通した薄膜を容易に形成すること
ができる。
As a result, the conductor via 13 formed by plating is firmly connected to the upper surface of the collective layer 1-1, and the conductor film 15 'coated on the upper surface of the insulating layer 14 serving as an interlayer insulating film is Since the conductive via 13 exposed from the upper surface of the insulating layer 14 is surely conducted, the pad 15 formed by wet etching and the collective layer 1-1 can easily form a thin film which is surely conducted through the conductive via 13. can do.

【0023】[0023]

【発明の効果】以上の説明から明らかなように本発明に
よれば極めて簡単な方法で、基板のコレクティブ層と確
実に導通したパッドを設けた薄膜を容易に形成すること
ができる等の利点があり、著しい経済的及び、信頼性向
上の効果が期待できるセラミック基板の薄膜形成方法を
提供することができる。
As is apparent from the above description, according to the present invention, it is possible to easily form a thin film provided with a pad that surely conducts to the collective layer of the substrate by an extremely simple method. Therefore, it is possible to provide a method for forming a thin film of a ceramic substrate, which is expected to have a remarkable economic effect and an effect of improving reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例によるセラミック基板の薄
膜形成方法を示す工程順側断面図である。
FIG. 1 is a cross-sectional view in order of the steps, showing a method for forming a thin film on a ceramic substrate according to an embodiment of the present invention.

【図2】 従来の薄膜形成方法を示す工程順側断面図で
ある。
FIG. 2 is a sectional view in the order of steps, showing a conventional thin film forming method.

【図3】 問題点を説明するための側断面図である。FIG. 3 is a side sectional view for explaining a problem.

【符号の説明】[Explanation of symbols]

1は基板、 1-1 はコレクテ
ィブ層 12,16はレジスト膜、 12-1はビア下
孔、13は導体ビア、14は絶縁層、
14' はポリイミド膜、15はパッド、
15' は導体膜、
1 is a substrate, 1-1 is a collective layer 12, 16 is a resist film, 12-1 is a via hole, 13 is a conductive via, 14 is an insulating layer,
14 'is a polyimide film, 15 is a pad,
15 'is a conductor film,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基板(1) と表面に形成され
たコレクティブ層(1-1) の上面にビア下孔(12-1)を有す
るめっき用のレジスト膜(12)を被膜させて、めっきによ
り一定高さの導体ビア(13)を当該コレクティブ層(1-1)
の上面に突出させ、前記レジスト膜(12)を除去した後に
上記基板(1),該コレクティブ層(1-1)および前記導体ビ
ア(13)の上面を覆う感光性のポリイミド膜を施して、当
該ポリイミド膜の全表面をドライエッチングして該導体
ビア(13)の上面を露出させた絶縁層(14)を形成し、当該
絶縁層(14)の全面に該導体ビア(13)と導通した導体膜を
被膜させてエッチング等によりパッド(15)を形成したこ
とを特徴とするセラミック基板の薄膜形成方法。
1. A plating method comprising: forming a resist film (12) for plating having a via pilot hole (12-1) on the upper surface of a ceramic substrate (1) and a collective layer (1-1) formed on the surface, and plating. The conductive via (13) with a certain height by the collective layer (1-1)
Of the substrate (1), after removing the resist film (12), a photosensitive polyimide film covering the upper surfaces of the collective layer (1-1) and the conductor via (13) is applied, The entire surface of the polyimide film is dry-etched to form an insulating layer (14) exposing the upper surface of the conductor via (13), and the entire surface of the insulating layer (14) is electrically connected to the conductor via (13). A method of forming a thin film on a ceramic substrate, characterized by forming a pad (15) by coating a conductor film and etching or the like.
JP30750291A 1991-11-22 1991-11-22 Thin film formation of ceramic substrate Withdrawn JPH05145238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30750291A JPH05145238A (en) 1991-11-22 1991-11-22 Thin film formation of ceramic substrate

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Application Number Priority Date Filing Date Title
JP30750291A JPH05145238A (en) 1991-11-22 1991-11-22 Thin film formation of ceramic substrate

Publications (1)

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JPH05145238A true JPH05145238A (en) 1993-06-11

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JP30750291A Withdrawn JPH05145238A (en) 1991-11-22 1991-11-22 Thin film formation of ceramic substrate

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891199B1 (en) * 2007-09-07 2009-04-02 주식회사 코리아써키트 Method of manufacturing pcb using improved surface treating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891199B1 (en) * 2007-09-07 2009-04-02 주식회사 코리아써키트 Method of manufacturing pcb using improved surface treating

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