JPH11186483A - Lead frame for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an economic highly reliable lead frame for semiconductor device, which can extremely reduce Pd oxide which is generated by heat treatment performed at the time of mounting a chip or curing a molding resin, can reduce thickness of a plated Pd layer without providing such noble metal as Au, Ag, etc., on the Pd layer, and the solder wettability of which is not deteriorated even when the lead frame is subjected to heat treatment. SOLUTION: A lead frame for semiconductor device is composed of nickel(Ni) or nickel alloy layers provided on both surfaces of a blank lead frame material 1 as intermediate layers 2 and palladium-iodine (Pd-I) alloy layers provided on the intermediate layers 2 as uppermost layers 3. The thickness and iodine (I) contents of the uppermost Pd-I alloy layers 3 are respectively adjusted to 0.005-1.0 μm and 0.1-50 wt.%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device forming an IC frame structure.

[0002]

2. Description of the Related Art A lead frame has a frame structure for supporting leads of an IC, an LSI discrete semiconductor, or the like. As shown in FIG. 2, it is composed of a pad for mounting an IC chip, an inner lead for wire bonding, and an outer lead for soldering to a printed wiring board.

Conventionally, lead frames for semiconductor devices include:
Ag or Ag alloy plating is provided on the uppermost layer of the chip mounting portion and the wire bonding portion of the lead frame, and Sn or Sn alloy layer is provided on the uppermost layer of the outer lead portion. Since a plating mask is required to manufacture a lead frame having such a structure, the manufacturing process becomes complicated and the manufacturing cost increases.

For this reason, a lead frame in which Ni plating is applied as an intermediate layer over the entire surface of the lead frame and Pd plating is applied as an outermost layer is an alternative to this method.
No. 49382 discloses this. However, the lead frame of this structure also has a Pd of the surface layer after a heat treatment step.
Oxidizes and deteriorates solder wettability.

The Pd antioxidant layer is made of Au.
A structure in which a plating film of Ag or Ag is provided on Pd is disclosed in JP-A-4-115558. However, the lead frame of this structure has a high manufacturing cost because a noble metal such as Au or Ag is plated on the entire surface of the lead frame.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to extremely reduce Pd oxides generated by heat treatment at the time of mounting a chip or at the time of curing a mode resin, and to deposit a noble metal such as Au or Ag on a Pd layer. An object of the present invention is to provide an economical and highly reliable semiconductor device lead frame in which the Pd plating layer is thin and the solder wettability is not deteriorated by the heat treatment step.

[0007]

The present invention has the following features. (1) A lead frame for a semiconductor device, comprising a nickel (Ni) or nickel alloy layer as an intermediate layer and a palladium (Pd) -iodine (I) alloy layer as an uppermost layer on a lead frame material. (2) The Pd-I alloy plating of the uppermost layer has a thickness of 0.005 to 1.0 m and an iodine (I) content of 0.1 to 50% by weight. )
4. The lead frame for a semiconductor device according to 1.

Hereinafter, the present invention will be described in detail. In the lead frame of the present invention, as shown in FIG. 1, an intermediate layer 2 and an uppermost layer 3 are sequentially formed on the entire surface or a necessary portion of a lead frame material 1. Each plating layer is
Either an electrolytic plating method or an electroless plating method may be used.

As the lead frame material, pure Cu, C
u-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, Cu
-Zn alloy, pure Fe, Fe-Ni alloy, ordinary copper, Al clad material, ternary alloy to which a third element is added, and the like are used.

The Ni or Ni alloy layer serving as the intermediate layer is a layer provided to suppress the diffusion of the lead frame material metal element into the uppermost Pd-I alloy layer.

The thickness of the uppermost Pd-I alloy plating layer is:
0.005 μm to 1.0 μm is common. this is,
When the thickness is less than 0.005 μm, the wire bonding property and the solder wettability deteriorate, and when the thickness is 1.0 μm or more, the use of a noble metal increases the cost.

The iodine (I) content is 0.1 to 50.
If the amount is less than 0.1% by weight, the solder wettability after heat treatment is deteriorated, and if it is more than 50% by weight, the wire bonding property is deteriorated.

The lead frame of the present invention may be used as it is as a lead frame for a semiconductor device after plating, or may be subjected to a heat treatment after plating to form a lead frame for a semiconductor device.

The lead frame of the present invention has very little deterioration in solder wettability even after a heat treatment step. The reason is,
In the case of a Pd film containing no iodine, a Pd oxide layer is formed after the heat treatment, and the Pd oxide layer cannot be removed by a generally used inactive flux and the solder wettability is poor. This is because the I-plated film hardly generates an oxide layer even after the heat treatment, and does not cause solder wetting failure even with an inactive flux.

[0015]

The present invention will be further described below with reference to examples and comparative examples. Example 1 and Comparative Example 1 After degreasing and activating the surface of a lead frame made of a copper alloy substrate by a conventional method, the entire surface was 1 μm thick as an intermediate layer.
Then, Pd-I plating having a thickness of 0.1 μm and an iodine (I) content of 11% was performed to obtain a lead frame (Example 1).

As Comparative Example 1, P
Pd plating 0.1μm instead of d-I plating
A lead frame was manufactured.

The obtained lead frame was evaluated for wire bonding property and solder wettability. The wire bonding property evaluation test was performed using a gold wire having a diameter of 25 μm, a load of 120 g, a temperature of 200 ° C., and an ultrasonic wave of 950 m.
Wire bonding was performed at w (milliwatts) and 90 ms (milliseconds), and the tensile strength was measured with a peel gauge.

After the plating, the solder wettability evaluation test
After each heat treatment at 60 ° C. for 60 seconds and at 360 ° C. for 60 seconds, the heat treatment was performed by the Menisko Kerafu method. The soldering conditions were as follows: Ronji type non-active type α-metal R-100 flux was dip-coated and immersed in a 63% Sn-37% Pd solder bath at 230 ± 1 ° C., and the zero-crossing time was measured.

Table 1 shows the structure of the lead frame subjected to various tests. Table 2 shows the results of the bonding property evaluation test and the solder wettability evaluation test. In Table 2, the evaluation A is excellent, B is slightly good, C is slightly bad, and D is bad.

Table 3 and FIGS. 3 to 6 show the results of surface analysis of the lead frames of Example 1 and Comparative Example 1 before and after heating at 330 ° C. for 60 seconds by an Auger analyzer. According to this, comparing before (FIG. 3) and after (FIG. 4) heat treatment of the Pd-I plating of the example of the present invention,
d and oxygen are almost unchanged. That is, 360 ° C. × 6
Even after the heat treatment for 0 second, the surface state does not change. On the other hand, comparing the heat treatment (FIG. 5) before and after the heat treatment (FIG. 6) of the Pd plating (not including I) of the comparative example, the heat treatment significantly reduced Pd and conversely increased oxygen. I have. This means that Pd plating not containing I was
When a heat treatment at 60 ° C. for 60 seconds is performed, a Pd oxide layer is formed, the surface state changes, and the heat resistance becomes poor.

Example 2 and Comparative Example 2 After degreasing and activating the surface of a lead frame made of a copper alloy substrate by a conventional method, a 1 μm thick intermediate layer was formed on the entire surface.
m Ni plating, then 0.05μm thick, iodine (I)
Pd-I plating with a content of 3% was performed to obtain a lead frame (Example 2).

Further, as Comparative Example 2, a lead frame was manufactured by performing Pd plating at 0.05 μm instead of the Pd-I plating in Example 2.

The obtained lead frame was evaluated for wire bonding and solder wettability in the same manner as in Example 1. Table 2 shows the results.

Example 3 and Comparative Example 3 After degreasing and activating the surface of a lead frame made of a copper alloy substrate by a conventional method, a 1 μm thick intermediate layer was formed on the entire surface.
m of Ni plating and then Pd-I plating with a thickness of 0.3 μm and an iodine (I) content of 0.1% were obtained to obtain a lead frame (Example 3).

As Comparative Example 3, a lead frame was manufactured by plating 0.3 μm of Pd instead of Pd-I plating in Example 3.

The obtained lead frame was evaluated for wire bonding and solder wettability in the same manner as in Example 3. Table 2 shows the results.

As shown in Table 2, the lead frame of the example of the present invention has good solder wettability even after the heat treatment step, but the comparative example not containing iodine has poor solder wettability. .

[0028]

[Table 1]

[0029]

[Table 2]

[0030]

[Table 3]

[0031]

The lead frame of the present invention has higher heat resistance, better solder wettability, and a simpler manufacturing process, and is more economical and reliable than conventional products.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating the manufacture of a semiconductor device lead frame according to the present invention.

FIG. 2 is a diagram illustrating a frame structure of a general semiconductor device lead frame.

FIG. 3 is a graph showing the results of a surface analysis performed by an Ogin analyzer on a sample before heat treatment in Example 1 (1) of the present invention.

FIG. 4 is a graph showing the results of surface analysis performed by an Osin analyzer on a sample after heat treatment in Example 1 (2) of the present invention.

FIG. 5 is a graph showing the results of a surface analysis by an Ogin analyzer of a sample before heat treatment in Comparative Example 1 (1).

FIG. 6 is a graph showing the results of a surface analysis performed on a sample after heat treatment in Comparative Example 1 (2) by an Ogin analyzer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Material 2 Middle layer 3 Top layer 4 Pad part 5 Inner lead part 6 Outer lead part 7 Dam bar 8 Guide rail

Claims (2)

[Claims] 1. A lead frame for a semiconductor device, comprising a nickel (Ni) or nickel alloy layer as an intermediate layer and a palladium (Pd) -iodine (I) alloy layer as an uppermost layer on a lead frame material. . 2. The palladium-iodine alloy layer as the uppermost layer has a thickness of 0.005 to 1.0 μm and an iodine content of 0.1 to 50% by weight. 4. The lead frame for a semiconductor device according to 1.