JPH11186388A - Manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, without having an Si substrate exposed to an etching gas for a long time, and without directly exposing the Si substrate to a gas contg. at least CD. SOLUTION: This manufacturing method comprises the steps for forming a thin Si nitride film 31 on an Si substrate 10, depositing an Si oxide film 32, and etching to form contact holes in two steps: a first step for using a gas contg. CO or contg. it and the Si nitride film 31 as an etch stopper, and a second step using a gas not contg. CO and under the condition that the Si nitride film 31 be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in a substrate process and a wiring process, and more particularly, to a technology for forming a contact hole.

[0002]

2. Description of the Related Art In the field of semiconductor devices such as LSI devices, pattern rules are steadily shrinking as devices become smaller and more highly integrated. Accordingly, a structure having a small diameter and a high aspect ratio is also required for a contact hole for connecting a wiring layer with a substrate or a transfer gate.

A conventional method of manufacturing a semiconductor device which satisfies the above demand will be described with reference to FIGS. FIG. 7 is an enlarged sectional view showing a part of a substrate process in a manufacturing process of a dynamic random access memory (DRAM), and FIG. DRAM
Are generally elements based on a CMOS circuit, and include an n-channel MOSFET (nMOS) and a p-channel MOSFET.
ET (pMOS) is connected by wiring.

[0004] As shown in FIG.
An n-type region (n-well) 11 is implanted into well 10 by well ion implantation.
And a p-type region (p-well) 12 are formed, and element isolation regions 13 and 14 are formed by selective oxidation. Also,
On the silicon substrate 10, a number of transfer gates 20 are formed. The transfer gate 20 is configured by stacking a gate oxide film 21, a gate polysilicon film 22, and a silicon oxide film 23 in this order from the silicon substrate 10 side.
In this specification, the term “offset” means that the silicon oxide film 23 forming the transfer gate 20 is displaced (offset) from the top surface of the transfer gate 20 with respect to the gate polysilicon film 22 which is an actual conductive layer. It is referred to as “silicon oxide film”. After these three layers are deposited on one surface, they are etched by a usual photolithography process to form the transfer gate 20.

A region on the left side of the figure with respect to the element isolation region 13 is a peripheral circuit region Rp having a relatively low degree of integration, and a region on the right side is
This is a memory cell region Rm having a relatively high degree of integration. The n-well 11 in both regions is masked with a resist, and the p-well 12
Then, an n-type impurity is implanted into the portion by an ion implantation method as shown by the arrow in the figure to form an n ⁻ diffusion layer 15 serving as the source / drain of the nMOS. The resist pattern at the time of ion implantation is not shown.

Next, a silicon oxide film is deposited on the entire surface of the wafer by a chemical vapor deposition (CVD) method, and is etched anisotropically to form a side wall 30 as shown in FIG. It is formed on the side surface of the transfer gate 20. The width of the sidewall 30 formed here is determined so as to be a value required as a mask when forming a diffusion layer serving as a source / drain of a MOS in the peripheral circuit region Rp.

Subsequently, as shown in FIG. 7C, the other region is masked by a normal photolithography process, and an n-type impurity is implanted into the p-well and a p-type impurity is implanted into the n-well of the peripheral circuit region Rp. Implanted sequentially by ion implantation, p ⁺
The diffusion layer 16 and the n ⁺ diffusion layer 17 are formed as the source and drain of the MOS in the peripheral circuit region Rp. Since the MOS in the memory cell region Rm only performs the ON / OFF operation, no p ⁺ diffusion layer or n ⁺ diffusion layer is required. However, since the MOS in the peripheral circuit region Rp performs an amplification operation or the like, these diffusion layers Is required.
The side wall 30 controls the position of the ion implantation, that is, the positional relationship between each of the diffusion layers 16 and 17 and the transfer gate 20, whereby the characteristics of the MOSFET are determined.
In FIG. 7C, a resist pattern at the time of ion implantation is not shown.

After the formation of the diffusion layers 16 and 17 in the peripheral circuit region Rp, a silicon oxide film 32 is deposited and the surface is chemically and mechanically polished.
Polishing by (CMP) and flattening as shown in FIG. In the wiring step, a polysilicon film 33 is deposited on the silicon oxide film 32, and a mask pattern 40 of a resist film is formed by a normal photolithography process in order to form a contact hole reaching the silicon substrate 10 and the transfer gate 20. The polysilicon film is formed under the condition that the silicon oxide film 32 is used as a stopper using this as a mask.
33 is anisotropically etched to form an opening 33a.

After the resist of the mask pattern 40 is ashed, polysilicon is further deposited and anisotropically etched back to form a sidewall 33b inside the opening 33a as shown in FIG. 8B. I do. Then, by dry etching the silicon oxide film 32 using the polysilicon film 33 as a mask, a contact hole 41 reaching the silicon substrate 10 and a contact hole 42 reaching the transfer gate 20 are formed as shown in FIG. I do. Opening 33a using sidewall 33b as described above
By reducing the diameter of the contact hole, a contact hole having a smaller diameter can be formed than when the mask pattern 40 formed by the photolithography process is used as it is.

After the contact holes 41 and 42 are filled with polysilicon to form pads by etch back and connect to bit lines, processing such as formation of capacitor electrodes is performed.
The DRAM wafer process (pre-process) ends. When the pre-process is completed, an operation check test is performed, and the semiconductor device is completed through packaging (post-process).

[0011]

However, in the above-described conventional method for manufacturing a semiconductor device, there is a possibility that the silicon substrate 10 may be damaged by being exposed to the etching gas for a long time during the etching for forming the contact hole. There is a problem that the performance of the semiconductor device is deteriorated and the manufacturing yield is reduced. That is, the contact hole
When forming 41 and 42, the silicon oxide film 3 to be etched
In consideration of the variation in the film thickness of 2, the etching time is determined according to the portion having the largest film thickness so that all the contact holes 41 reach the silicon substrate 10 reliably. For this reason, in a portion where the silicon oxide film 32 is relatively thin, the time of exposure to the gas from the opening of the contact hole 41 to the end of the etching becomes longer, and the portion is easily damaged.

In particular, when carbon monoxide is added to the gas, the silicon substrate is greatly damaged. In order to keep the diameter of the contact hole as designed, it is necessary to prevent the sidewall 33b formed in the polysilicon film 33 from being etched away. Therefore, a gas system containing carbon monoxide having a high selectivity to the polysilicon film 33, for example, a gas system such as CHF3 / CO and Ar / C4F8 / CO / O2 is used. However, when the silicon substrate 10 is exposed to a gas to which carbon monoxide is added, the lifetime of minority carriers in the substrate is shortened, it is difficult to recover the minority carriers, and the contact resistance increases. Is reported on pages 201-212 of 1995 DRY PROCESS SYMPOSIUM. All of these phenomena degrade the performance of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and does not expose a silicon substrate to an etching gas for a long time and uses a gas containing at least carbon monoxide. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a silicon substrate is not directly exposed.

[0014]

According to a method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is formed thinly on a silicon substrate, and then a silicon oxide film is deposited. The first stage etching is performed under the condition that the silicon nitride film is used as a stopper, and the second stage etching is performed under the condition that the silicon nitride film is removed using a gas containing no carbon monoxide. And In the first etching step, the etching time is set longer in consideration of the variation in the thickness of the silicon oxide film, but in this step, the silicon substrate is not exposed to the gas. In addition, in the second etching step, it is not necessary to allow a margin for the etching time because the variation in the thickness of the silicon nitride film is small, and the time for exposing the silicon substrate to the gas is short. Moreover, since the gas system used in the second etching step does not contain carbon monoxide, damage to the silicon substrate is small.

More specifically, in the method of manufacturing a semiconductor device according to the present invention, a step of depositing a silicon nitride film over the entire surface of a silicon substrate and a step of depositing a silicon oxide film over the silicon nitride film over the entire surface of the silicon substrate Forming a selective film on the silicon oxide film, which has selectivity for etching with respect to the silicon oxide film and the silicon nitride film, and which can be etched using the silicon oxide film as a stopper; Forming a mask on the upper selective film by a photolithography process,
Using a mask, etching the selective film under conditions using the silicon oxide film as a stopper to form an opening, and further depositing the same material as the selective film on the selective film, and then anisotropically etching back. And forming holes in the silicon nitride film under conditions that the selection film is used as a mask, the silicon nitride film is used as a stopper, and that a sufficient selection ratio with respect to the selection film can be secured. The first step of forming a contact hole in which dry etching is performed until the silicon nitride film is reached, and the silicon nitride film is removed under conditions that use the selective film as a mask and have a small effect on the silicon substrate and can secure a selectivity to the selective film. And a second step of forming a contact hole in which dry etching is performed using a gas system containing no carbon monoxide. It is characterized in.

The selection film can be formed of polysilicon. Before the step of forming the silicon nitride film,
The method may include forming a transfer gate on a silicon substrate. In this case, in the step of depositing the silicon nitride film, the silicon nitride film is deposited to a thickness that leaves a wider gap between the transfer gates than the diameter of the contact hole. A step of forming a first silicon oxide film as a protective film on the entire surface of the silicon substrate between a step of forming a transfer gate and a step of depositing a silicon nitride film; and a step of depositing a heterogeneous film on the protective film. Forming a sidewall on the side surface of the transfer gate by anisotropically etching the heterogeneous film, and doping n-type and p-type impurities around the transfer gate using the sidewall as a mask. And removing the heterogeneous film by etching using the protective film as a stopper. The different kind of film can be formed by a polysilicon film or a silicon nitride film.

The transfer gate may be formed to have a polysilicon film and a silicon oxide film formed on the polysilicon film. In this case, since a silicon oxide film is formed under the silicon nitride film on the transfer gate, a contact hole for contacting the transfer gate is formed by etching a silicon oxide film, a silicon nitride film, and a silicon oxide film in this order. Need to be done. Therefore, the thickness of the silicon nitride film is
The first of contact hole formation on transfer gate
It is determined not to function as a stopper at the stage, but to function as a stopper in portions other than the transfer gate. As a result, in portions other than the transfer gate, the silicon oxide film is etched in the first stage,
While the silicon nitride film is etched in the stage, the silicon nitride film is etched in the first stage on the transfer gate, and the silicon oxide film is etched in the second stage. In the first stage of forming a contact hole,
A gas system containing carbon monoxide can be used, and a layer or a gas system containing no carbon monoxide can be used.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to a dynamic random access memory.
FIG. 1 shows two examples of an embodiment applied to a (DRAM) manufacturing process.
This will be described with reference to FIG.

1 and 2 show a method of manufacturing a semiconductor device according to the first embodiment. FIG. 1 shows a part of a substrate step in a DRAM manufacturing step, and FIG. 2 shows a part of a wiring step thereof. It is an expanded sectional view shown step by step. DRAM is generally an element based on a CMOS circuit, and includes an n-channel MOSFET (nMOS) and a p-channel MOSFET.
(pMOS) are connected by wiring. FIG.
As shown in FIG. 1A, an n-type region (n-well) 11 and a p-type region (p-well) 12 are formed in a silicon substrate 10 by implanting well ions, and an element isolation region 13 is formed by selective oxidation. , 14 are formed. The region on the left side of the figure with respect to the element isolation region 13 is a peripheral circuit region Rp, which is a low-integration region where the transistor integration is relatively low, and the region on the right side is
This is a memory cell region Rm which is a high integration region having a relatively high integration degree.

In the manufacturing method of the first embodiment, a first step of forming the transfer gate 20 on the silicon substrate 10 (FIG. 1A), and a second step of forming a first silicon oxide film 35 as a protective film. Step (FIG. 1B), a third step of depositing a polysilicon film 36 as a heterogeneous film on the first silicon oxide film 35 (FIG. 1B), forming sidewalls 36a on the side surfaces of the transfer gate 20 4 (FIG. 1C), the peripheral circuit region Rp
Fifth step (FIG. 1C) of doping n-type and p-type impurities around the transfer gate 20 of FIG. 1, and a sixth step (FIG. 1C) of removing the polysilicon film 36 using the first silicon oxide film 35 as a stopper. 1 (C)-(D)), a seventh step of forming a silicon nitride film 31 functioning as a stopper on the entire surface of the silicon substrate 10 (FIG. 1 (D)), a film covering the transfer gate 20 on the entire surface of the silicon substrate 10 An eighth step of depositing a thick second silicon oxide film 32 (FIG. 2A), a ninth step of flattening the surface of the second silicon oxide film 32 (FIG. 2A), a second step of FIG. A tenth step (FIG. 2A) of forming a polysilicon film 33 as a selective film on the silicon oxide film 32, a mask for forming a contact hole
40 polysilicon film by photolithography process
An eleventh stage (FIG. 2A) for forming an opening 33a on the polysilicon film 33 under the condition that the second silicon oxide film 32 is used as a stopper.
(A)), a thirteenth step of forming a sidewall 33b inside the opening 33a (FIG. 2B), and a fourteenth step of etching the second silicon oxide film 32 using the polysilicon film 33 as a mask.
(FIG. 2C) and a fifteenth step (FIG. 2C) of etching the silicon nitride film 31 and the first silicon oxide film 35 using the polysilicon film 33 as a mask. Hereinafter, each stage will be described in order.

As shown in FIG. 1A, the transfer gate 20 is formed by a gate oxide film in order from the silicon substrate 10 side.
21 and a gate polysilicon film 22. In the first stage of the substrate process, after these two layers are deposited on the entire surface of the silicon substrate 10, the resist film is left on the portion where the transfer gate 20 is formed by a usual photolithography process, and the gate polysilicon film 22 is formed using the resist film as a mask. And the gate silicon oxide film 21 are simultaneously dry-etched to form the transfer gate 20.

After the transfer gate 20 is formed, the n-well 11 in the peripheral circuit region Rp and the memory cell region Rm is masked with a resist, and an n-type impurity is added to the p-well 12 as shown by an arrow in the drawing. By doping by ion implantation (ion implantation), an n ^- diffusion layer 15 serving as the source / drain of the nMOS is formed. The resist pattern at the time of ion implantation is not shown.

In the second and third stages, as shown in FIG. 1B, a first silicon oxide film 35 is deposited as a protective film on the entire surface of the silicon substrate by CVD, and then a polysilicon film is formed as a heterogeneous film. A film 36 is deposited by a CVD method. In the fourth stage, the polysilicon film 36 is anisotropically etched to form side walls 36a on the side surfaces of the transfer gate 20, as shown in FIG. The etching condition in the fourth stage is, for example, a discharge frequency of 2.45 GHz.
Pressure of 5mTorr using ECR plasma etching equipment
Supply Cl ₂ gas at a flow rate of 100 cc / min to reduce microwave power.
Set 300W, RF power to 20W, and electrode temperature to 20 ° C. At this time, the sum of the thickness of the first silicon oxide film 35 and the thickness of the sidewall 36a becomes a width required as a mask when forming a diffusion layer serving as a source / drain of a MOS in the peripheral circuit region Rp. Adjust the etching time as described above. The thickness of the first silicon oxide film 35 is determined so that the first silicon oxide film 35 remains even after the sidewall 36a is removed in the sixth step.

In the fifth stage, ordinary photolithography
Other regions are masked by a process to form a peripheral circuit region Rp.
N-type impurity in p-well and p-type impurity in n-well
As shown by arrows in FIG.
And p⁺Diffusion layer 16, n ⁺Diffusion layer 17 in peripheral circuit area
It is formed as the source / drain of the MOS of Rp. Rhinoceros
The wall 36a is located at the position of ion implantation, that is, each diffusion layer 1
By controlling the positional relationship between 6, 17 and the transfer gate 20,
Thus, the characteristics of the MOSFET are determined. What
In FIG. 1C, the resist pattern at the time of ion implantation is also used.
Are not shown.

In the sixth step, the polysilicon film is formed under the condition that a sufficient selectivity with respect to the first silicon oxide film 35 can be secured.
The side wall 36a composed of 36 is isotropically etched and removed. The etching conditions in the sixth step are, for example, using a microwave downflow etching apparatus having a discharge frequency of 2.45 GHz, and using CF ₄ , O ₂ , and Cl ₂ gas at a pressure of 40 Pa and flow rates of 175 cc / min, 125 cc / min, Supply at 50cc / min, set microwave power to 500W and electrode temperature to 25 ° C.

In the seventh stage, as shown in FIG. 1D, the transfer gate 2 adjacent to the memory cell region Rm
The silicon nitride film 31 having a thickness sufficient to leave a gap d larger than the diameter of the contact hole during the zero-thickness and to function as a stopper at the time of etching in the fourteenth step is formed by CV.
Formed over the entire surface by D method.

In the eighth step, as shown in FIG. 2A, a second silicon oxide film 32 having a thickness covering the transfer gate 20 is deposited on the entire surface of the silicon substrate 10, and in the ninth step, the second silicon oxide film 32 is deposited. The surface of the silicon oxide film 32 is polished and flattened by CMP. The ninth stage is the substrate process.

In a tenth stage, which is the first stage of the wiring process, as shown in FIG. 2A, a polysilicon film 33 as a selection film used as a mask when forming a contact hole is planarized. The second silicon oxide film 32 is deposited. The selective film is required to have selectivity at the time of etching with respect to the silicon oxide film and the silicon nitride film, and to be capable of etching using the silicon oxide film as a stopper. In the eleventh stage, a mask pattern 40 of a resist film is formed by a normal photolithography process in order to form a contact hole reaching the silicon substrate 10 and the transfer gate 20,
In the twelfth step, the polysilicon film 33 is anisotropically etched by using this as a mask and using the silicon oxide film 32 as a stopper to form an opening 33a as shown in FIG. The etching condition in the twelfth step is, for example, using a parallel plate type reactive ion etching apparatus and a pressure of 20 mTorr.
r SF ₆ and HBr gas flow 36cc / min, 8cc / min respectively
And the RF power is set to 300 W and the cooling He pressure is set to 4 Torr.

In the thirteenth step, after the resist of the mask pattern 40 is ashed, polysilicon is further deposited and anisotropically etched back to form the inside of the opening 33a as shown in FIG.
A sidewall 33b is formed as shown in FIG.
The etching condition in the thirteenth stage is, for example, a discharge frequency
Using a 2.45GHz ECR plasma etching system, pressure 5
Supply Cl ₂ gas at a flow rate of 100 cc / min at mTorr, and set the microwave power to 300 W, the RF power to 20 W, and the electrode temperature to 20 ° C.

In the fourteenth and fifteenth steps, contact holes are formed by etching using the polysilicon film 33 formed as described above as a mask. By reducing the diameter of the opening 33a using the sidewall 33b, it is possible to form a contact hole having a smaller diameter than using the mask pattern 40 formed by the photolithography process as it is.

The fourteenth step is the first step of forming a contact hole. In this step, the silicon nitride film 31 deposited on a portion other than the transfer gate 20 is used as a stopper, and the polysilicon film 33 is sufficiently selected. Dry etching is performed under conditions that can ensure the ratio, and the second silicon oxide film 32 is etched until the holes reach the silicon nitride film 31. The etching conditions in the fourteenth stage are, for example, using a magnetron etching apparatus and a pressure of 30 mTorr.
Ar, CO, C ₄ F ₈ , O ₂ gas flow at 200cc / min, 50cc / mi
n, 12cc / min, 6cc / min, RF power 1500W, cooling He back pressure 3 / 70Torr (center / edge), electrode temperature 20
Set to ° C. In the fourteenth step, a gas containing carbon monoxide is used to increase the selectivity with respect to the polysilicon film 33, and the etching time becomes longer in consideration of the variation in the thickness of the second silicon oxide film 32. Is set.

The fifteenth step is a step of forming a contact hole.
In this step, the polysilicon film 33 is used as a mask
The effect on the silicon substrate 10 is small and
Under conditions where the selectivity to the silicon film can be secured, silicon
Gas containing no carbon monoxide until the nitride film is removed
Is used to perform dry etching. As a result,
The silicon nitride film 31 and the first silicon oxide film 35 are
Contact hole 4 as shown in FIG.
1,42 are formed. The etching conditions in the fifteenth stage are as follows:
For example, using a magnetron etching device, pressure 40mT
Ar, CHF at orr₈, O _Two100cc / min, 28cc / mi
n, 12cc / min, RF power 400W, cooling He back pressure 3
/ 70 Torr (center / edge), set the electrode temperature to 20 ° C
You. The film to be etched in the fifteenth step is thin and thick
The etching time has a margin because the absolute amount of
It is set without adding.

After the contact holes 41 and 42 are filled with polysilicon and pads are formed by etch back and connected to bit lines, processing such as formation of capacitor electrodes is performed.
The DRAM wafer process (pre-process) ends. When the pre-process is completed, an operation check test is performed, and the semiconductor device is completed through packaging (post-process).

According to the first embodiment described above, the fourteenth
In the stage, the silicon nitride film 31 is used as a stopper to prevent the silicon substrate 10 from contacting a gas containing carbon monoxide. In the fifteenth stage, the silicon substrate 10 is set without leaving a margin for the etching time. It is possible to minimize the time that 10 is exposed to gas.
Moreover, since the gas used in the fifteenth step does not contain carbon monoxide, damage to the silicon substrate 10 can be suppressed to a small level. Therefore, it is possible to prevent the performance of the semiconductor device from deteriorating and the yield from decreasing.

FIGS. 3 and 4 are process diagrams showing a method for manufacturing a semiconductor device according to the second embodiment. The arrangement of the wells 11 and 12 on the silicon substrate 10, the element isolation regions 13 and 14, the transfer gate 20, and the separation between the peripheral circuit region Rp and the memory cell region Rm are the same as those in the first embodiment.

In the manufacturing method according to the second embodiment, a first step (FIG. 3A) of forming a transfer gate 20 on a silicon substrate 10 and a second step of forming a first silicon oxide film 35 as a protective film are performed. Step (FIG. 3B), a third step of depositing a silicon nitride film 37 as a heterogeneous film on the first silicon oxide film 35 (FIG. 3B), forming sidewalls 37a on the side surfaces of the transfer gate 20 4 (FIG. 3C), the peripheral circuit region Rp
Fifth step (FIG. 3C) of doping the periphery of the transfer gate 20 with n-type and p-type impurities, and a sixth step (FIG. 3C) of removing the silicon nitride film 37 using the first silicon oxide film 35 as a stopper. 3 (C)-(D)), a seventh step of forming a silicon nitride film 31 functioning as a stopper on the entire surface of the silicon substrate 10 (FIG. 3 (D)), a film covering the transfer gate 20 on the entire surface of the silicon substrate 10 An eighth step of depositing a thick second silicon oxide film 32 (FIG. 4A), a ninth step of flattening the surface of the second silicon oxide film 32 (FIG. 4A), a second step A tenth step of forming a polysilicon film 33 on the silicon oxide film 32 (FIG. 4A), and an eleventh step of forming a contact hole forming mask 40 on the polysilicon film 33 by a photolithography process (FIG. 4A). (A)), the polysilicon film 33 is formed under the condition that the second silicon oxide film 32 is used as a stopper. The twelfth step of forming the opening 33a by etching (FIG. 4A), the opening 33a
The thirteenth step of forming the side wall 33b inside the substrate (FIG. 4)
(B)), a fourteenth step of etching the second silicon oxide film 32 using the polysilicon film 33 as a mask (FIG. 4C), and a silicon nitride film using the polysilicon film 33 as a mask.
Fifteenth etching of the first silicon oxide film 35 and the first silicon oxide film 35
(FIG. 4C).

The difference between the manufacturing method of the second embodiment and the manufacturing method of the first embodiment is that the heterogeneous film formed in the third stage is a polysilicon film in the first embodiment. In the second embodiment, the silicon nitride film 37 is used. As a result, in the fourth stage, the silicon nitride film 37 is etched to form a sidewall 37a, and in the sixth stage, the silicon nitride film forming the sidewall 37a is formed. 37 is removed by etching. Since the first stage is the same as the corresponding stage of the first embodiment, the second to sixth stages will be described below.

In the second and third stages, as shown in FIG. 3B, a first silicon oxide film 35 is deposited as a protective film on the entire surface of the silicon substrate 10 by a CVD method, and then a silicon film is deposited as a heterogeneous film. A nitride film 37 is deposited by a CVD method. 4th
In the step, the silicon nitride film 37 is anisotropically etched to form side walls 37a on the side surfaces of the transfer gate 20, as shown in FIG. 4C. 4th
Etching conditions at the stage, for example, discharge frequency 13.56M
Using a parallel-plate type reactive ion etching system of Hz, CHF ₃ and O ₂ gas at a pressure of 40 mTorr and flow rates of 67 cc / min and 13 c, respectively.
c / min and the RF power applied to the lower electrode is 350
After performing main etching with W, electrode spacing set to 35 mm and electrode temperature set to 40 ° C., CHF ₃ and SF ₆ gas were supplied at a flow rate of 10 cc / min and 100 cc / min, respectively, at a pressure of 325 mTorr and applied to the lower electrode. The RF power is set to 140 W, the electrode interval is set to 20 mm, and the electrode temperature is set to 40 ° C., and over-etching is performed. At this time, the film thickness of the first silicon oxide film 35 and the sidewall 37
The etching time is adjusted so that the sum of the thickness a and the width becomes a width required as a mask when forming a diffusion layer to be a source / drain of a MOS in the peripheral circuit region Rp. Also,
The thickness of the first silicon oxide film 35 is maintained even after the sidewall 37a is removed in the sixth step.
Is determined so as to remain.

In the fifth stage, other regions are masked by a normal photolithography process to form a peripheral circuit region Rp.
The p-well to n-type impurity, a p-type impurity into the n-well is doped by ion implantation in order as shown by the arrows in FIG. 3 (C), the p ⁺⁺ diffusion layer 16, n ⁺⁺ diffusion layer 17 It is formed as the source / drain of the MOS in the peripheral circuit region Rp. The side wall 37a controls the position of the ion implantation, that is, the positional relationship between each of the diffusion layers 16, 17 and the transfer gate 20, whereby the characteristics of the MOSFET are determined.

In the sixth step, the silicon nitride film is formed under a condition that a sufficient selectivity with respect to the first silicon oxide film 35 can be secured.
The side wall 37a composed of 37 is isotropically etched and removed. The etching conditions at this time are, for example, using a microwave downflow etching apparatus having a discharge frequency of 2.45 GHz, and using a gas of CF ₄ , O ₂ , N ₂ , and Cl ₂ at a pressure of 80 Pa at a flow rate of 270 cc / min and 270 cc / min, respectively. , 80cc / min, 17
Supply at 0 cc / min, set microwave power to 600 W and electrode temperature to 25 ° C.

In the seventh stage, as shown in FIG. 3D, the transfer gate 2 adjacent to the memory cell region Rm
The silicon nitride film 31 having a thickness sufficient to leave a gap d larger than the diameter of the contact hole during the zero-thickness and to function as a stopper at the time of etching in the fourteenth step is formed by CV.
Formed over the entire surface by D method. The processing from the seventh stage onward is the same as that of the first embodiment, and a description thereof will be omitted.

In the second embodiment described above, the first
As in the first embodiment, the time during which the silicon substrate is exposed to the etching gas can be minimized, and the gas containing carbon monoxide can be prevented from touching the silicon substrate 10, thereby deteriorating the performance of the semiconductor device. And a decrease in yield can be prevented.

FIGS. 5 and 6 are process diagrams showing a method for manufacturing a semiconductor device according to the third embodiment. The arrangement of the wells 11 and 12 on the silicon substrate 10, the element isolation regions 13 and 14, the transfer gate 20, and the separation between the peripheral circuit region Rp and the memory cell region Rm are the same as those in the first embodiment.

In the manufacturing method according to the third embodiment, a first step (FIG. 5A) of forming a transfer gate 20 on a silicon substrate 10 and a second step of forming a first silicon oxide film 35 as a protective film are performed. Step (FIG. 5B), a third step of depositing a polysilicon film 36 as a heterogeneous film on the first silicon oxide film 35 (FIG. 5B), forming sidewalls 36a on the side surfaces of the transfer gate 20 4 (FIG. 5C), the peripheral circuit region Rp
Fifth step of doping n-type and p-type impurities around transfer gate 20 (FIG. 5C), and a sixth step of removing polysilicon film 36 using first silicon oxide film 35 as a stopper (FIG. 5C). 5 (C) to (D)), a seventh step of forming a silicon nitride film 31 functioning as a stopper on the entire surface of the silicon substrate 10 (FIG. 5D), a film covering the transfer gate 20 on the entire surface of the silicon substrate 10 An eighth step of depositing a thick second silicon oxide film 32 (FIG. 6A), a ninth step of flattening the surface of the second silicon oxide film 32 (FIG. 6A), a second step of FIG. A tenth step (FIG. 6A) of forming a polysilicon film 33 as a selection film on the silicon oxide film 32, a mask for forming a contact hole
40 polysilicon film by photolithography process
An eleventh step (FIG. 6A) for forming an opening 33a by etching the polysilicon film 33 under conditions using the second silicon oxide film 32 as a stopper (FIG. 6A).
(A)), a thirteenth step of forming a sidewall 33b inside the opening 33a (FIG. 6B), using the polysilicon film 33 as a mask, the transfer gate 20 of the second silicon oxide film 32 and the silicon nitride film 31. 14th step of etching the upper part
(FIG. 6 (C)) and a fifteenth step of etching the silicon nitride film 31, the first silicon oxide film 35, and the offset silicon oxide film 23 of the transfer gate 20 using the polysilicon film 33 as a mask (FIG. C)).

The manufacturing method of the third embodiment is different from the manufacturing method of the first embodiment in that the transfer gate 20 is formed of three layers including an offset silicon oxide film 23 in the third embodiment. The point is that the thickness of the silicon nitride film 31 is determined not to function as a stopper for etching in the fourteenth step on the transfer gate 20 but to function as a stopper in portions other than the transfer gate 20. Since the second to sixth steps and the eighth to thirteenth steps are the same as the corresponding steps of the first embodiment, the first, seventh, fourteenth, and fifteenth steps will be described below. I do.

As shown in FIG. 5A, the transfer gate 20 has a gate oxide film in order from the silicon substrate 10 side.
21, a gate polysilicon film 22 and an offset silicon oxide film 23 are laminated. In the first stage of the substrate process, after these three layers are deposited on the entire surface of the silicon substrate 10, a resist film is left in a portion where the transfer gate 20 is formed by a normal photolithography process, and the offset polysilicon is formed using the gate polysilicon film 22 as a stopper. The oxide film 23 is dry-etched. After the resist is ashed, the transfer gate 20 is formed by simultaneously dry-etching the gate polysilicon film 22 and the gate silicon oxide film 21 using the offset silicon oxide film 23 as a mask.

The reason that the offset silicon oxide film 23 is used as a mask is to prevent the resist layer from being damaged by etching a large step like the transfer gate 20 using a thin resist layer. The thickness of the resist layer that can be developed by the exposure apparatus depends on the depth of focus of the exposure apparatus, but the finer the pattern formed by photolithography, the higher the numerical aperture (NA) in order to increase the resolution of the exposure apparatus. Must be reduced, which reduces the depth of focus. in this way,
The resist layer that can be developed becomes thinner as the miniaturization progresses. Therefore, when etching with a large step is required, a mask such as the above-mentioned offset silicon oxide film 23 is required.

In the seventh stage, as shown in FIG. 5D, the transfer gate 2 adjacent to the memory cell region Rm
A silicon nitride film 31 is formed on the entire surface by a CVD method so as to leave a gap d wider than the diameter of the contact hole during 0. In the third embodiment, since the offset silicon oxide film 23 is formed below the silicon nitride film 31 on the transfer gate 20, the contact hole for contacting the gate polysilicon film 22 of the transfer gate 20 is formed of silicon oxide. It must be formed by etching the film 32, the silicon nitride film 31, and the offset silicon oxide film 23. Here, if the silicon nitride film 31 has such a thickness as to serve as a stopper for the fourteenth stage etching in all regions, the offset will occur within the opening time of the contact hole 41 reaching the silicon substrate 10 during the fifteenth stage etching. There is a possibility that the silicon oxide film 23 cannot be etched. Therefore, the thickness of the silicon nitride film deposited in the seventh stage is
On the transfer gate 20, the thickness is determined so as not to function as a stopper for etching in the fourteenth step, and to function as a stopper in portions other than the transfer gate 20.

In the fourteenth stage, dry etching is performed under the condition that the silicon nitride film 31 deposited on the portion other than the transfer gate 20 is used as a stopper and a sufficient selectivity with respect to the polysilicon film 33 can be secured. In portions other than the transfer gate 20, the second silicon oxide film 32 is etched, and on the transfer gate 20, the second silicon oxide film 32 and the silicon nitride film 31 are etched. The etching conditions are the same as in the first embodiment. The thickness of the second silicon oxide film 32 is
Since the upper part is thinner, the etching on the silicon nitride film 31 is started earlier on the transfer gate 20 in the other parts. Therefore, even when the silicon nitride film 31 on the transfer gate 20 is removed by etching, at least a part of the silicon nitride film 31 remains in other portions.

In the fifteenth step, dry etching is performed using a polysilicon film 33 as a mask and a gas system containing no carbon monoxide under the conditions for removing the silicon nitride film. The film 31 and the first silicon oxide film 35 are etched, and the first silicon oxide film 35 and the offset silicon oxide film 23 are etched on the transfer gate 20 to form contact holes as shown in FIG. 41 and 42 are formed.

In the third embodiment described above, the first
As in the first embodiment, the time during which the silicon substrate is exposed to the etching gas can be minimized, and the gas containing carbon monoxide can be prevented from touching the silicon substrate 10, thereby deteriorating the performance of the semiconductor device. And a decrease in yield can be prevented. Further, by using the offset silicon oxide film 23 as a mask, a fine transfer gate 20 can be formed. In addition, by appropriately setting the thickness of the silicon nitride film 31 functioning as a stopper, the contact hole 42 reaching the transfer gate 20 and the contact hole reaching the silicon substrate as in the other embodiments that do not include the offset silicon oxide film 23. 41 can be simultaneously formed.

In each of the above embodiments, the gas containing carbon monoxide is used in the fourteenth stage, which is the first stage of the contact hole formation. However, by taking measures such as cooling the electrode, Even a gas containing no carbon monoxide can be etched under the condition that the selectivity to the polysilicon film 33 is high. For example, the first embodiment of the first embodiment
In four stages, using magnetron etching equipment, pressure 30
mTorr, Ar, C ₄ F ₈ , O ₂ gas each flow 500sccm,
The power was supplied at 12 sccm and 8 sccm, the RF power was set to 1500 W, the cooling He back pressure was set to 3/70 Torr (center / edge), and the electrode temperature was set to 20 ° C. In the fifteenth stage, the pressure was continuously set to 40 mTorr, Ar, CHF ₃ , O
₂ each gas flow rate 100cc / min, 28cc / min, 12cc / mi
n, RF power is set to 400 W, cooling He back pressure is set to 3/70 Torr (center / edge), and electrode temperature is set to 20 ° C.

By performing the etching under the above-described conditions, the contact hole 41 and the contact hole 41, while suppressing the progress of the etching to the polysilicon film 33, as in the first embodiment using the gas to which carbon monoxide is added. 42 can be formed. In this case, a facility for excluding toxic carbon monoxide gas, an alarm, and the like are not required, and the cost of manufacturing equipment can be suppressed.

[0054]

As described above, according to the present invention, a silicon nitride film is formed on a silicon substrate as a stopper when a contact hole is formed, and then a silicon oxide film is deposited. Separation into a first step of cutting the layer up to the silicon nitride film and a second step of cutting the silicon nitride film minimizes the time for which the silicon substrate is exposed to gas, and furthermore, the second step Since the gas used in the method does not contain carbon monoxide, damage to the silicon substrate can be suppressed to a small level. Therefore, the performance of the manufactured semiconductor device can be kept good, and the yield can be kept high.

[Brief description of the drawings]

FIG. 1 is an enlarged cross-sectional view of a semiconductor device, showing a part of a substrate process in steps of a method of manufacturing a semiconductor device according to a first embodiment;

FIG. 2 is an enlarged cross-sectional view of the semiconductor device, showing a part of a wiring step in a method of manufacturing the semiconductor device according to the first embodiment in a stepwise manner;

FIG. 3 is an enlarged cross-sectional view of a semiconductor device showing a part of a substrate step in a method of manufacturing a semiconductor device according to a second embodiment in a stepwise manner;

FIG. 4 is an enlarged cross-sectional view of a semiconductor device, showing a part of a wiring step in a method of manufacturing a semiconductor device according to a second embodiment in a stepwise manner;

FIG. 5 is an enlarged cross-sectional view of a semiconductor device, showing a part of a substrate process in a process of a method of manufacturing a semiconductor device according to a third embodiment in a stepwise manner.

FIG. 6 is an enlarged cross-sectional view of a semiconductor device, showing a part of a wiring step in a method of manufacturing a semiconductor device according to a third embodiment in a stepwise manner;

FIG. 7 is an enlarged cross-sectional view of a semiconductor device showing stepwise a part of a substrate process in a conventional semiconductor device manufacturing method.

FIG. 8 is an enlarged cross-sectional view of a semiconductor device showing stepwise a part of a wiring step in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 10 Silicon substrate 20 Transfer gate 32 Second silicon oxide film 31 Silicon nitride film 35 First silicon oxide film 41,42 Contact hole

Claims (10)

[Claims] A step of depositing a silicon nitride film on the entire surface of the silicon substrate;
Depositing a silicon oxide film on the silicon nitride film; and having a selectivity for etching with respect to the silicon oxide film and the silicon nitride film on the silicon oxide film, and capable of etching using the silicon oxide film as a stopper. Forming a selective film, forming a contact hole forming mask on the upper selective film by a photolithography process, and using the mask and the silicon oxide film as a stopper. Forming an opening by etching; and further depositing the same material as the selective film on the selective film, and then forming an sidewall anisotropically by etching back anisotropically. Using the selection film as a mask, the silicon nitride film as a stopper, and a sufficient selection ratio with respect to the selection film. In conditions can be ensured, the first contact hole forming dry etching until hole reaches the silicon nitride film
A gas containing no carbon monoxide until the silicon nitride film is removed, under the condition that the select film is used as a mask, the influence on the silicon substrate is small, and the selectivity with respect to the select film is ensured. A second step of forming a contact hole by dry etching using a system, wherein these steps are sequentially performed. 2. The method according to claim 1, wherein the selection film is formed of polysilicon. 3. The method according to claim 1, wherein before the step of forming the silicon nitride film,
Forming a transfer gate on the silicon substrate, wherein, in the step of depositing the silicon nitride film, the silicon nitride film is deposited to a thickness that leaves a wider gap than the diameter of the contact hole between the transfer gates. 3. The method of manufacturing a semiconductor device according to claim 1, wherein: 4. A step of forming a first silicon oxide film as a protective film on the entire surface of the silicon substrate between the step of forming the transfer gate and the step of depositing the silicon nitride film; Depositing a heterogeneous film having selectivity during etching with respect to the protective film, and forming a sidewall on the side surface of the transfer gate by anisotropically etching the heterogeneous film;
4. The method according to claim 3, further comprising: doping impurities around the transfer gate using the sidewalls as a mask; and removing the mask layer by etching using the protective film as a stopper.
13. The method for manufacturing a semiconductor device according to item 5. 5. The method according to claim 4, wherein the heterogeneous film is formed of a polysilicon film. 6. The method according to claim 4, wherein the heterogeneous film is formed of a silicon nitride film. 7. The method according to claim 3, wherein the transfer gate has a polysilicon film and a silicon oxide film formed on the polysilicon film. 8. The method according to claim 1, wherein the thickness of the silicon nitride film is a first thickness of the contact hole on the transfer gate.
The method of manufacturing a semiconductor device according to claim 7, wherein the function is not set to function as a stopper at a stage, but is set to function as a stopper in a portion other than the transfer gate. 9. The method according to claim 1, wherein in the first step of forming the contact hole, dry etching is performed using a gas containing carbon monoxide. 10. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step of forming the contact hole, dry etching is performed using a gas system containing no carbon monoxide. .