JPH11177024A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make observation hand for the circuit constitution of a semiconductor device and the contents of a memory element configuring circuit constitution by forming electrode wirings for shielding formed between the electrode wirings of a wiring layer insulated and isolated from an integrated circuit and kept at a constant potential. SOLUTION: Bit lines 307 are formed onto an element through an inter-layer insulating film 306. Bit-line contacts 307a connected to the bit lines 307 from one of source-drains 301a formed to semiconductor substrates 301 on both sides of floating gates 304 are formed. Electrode wirings 307b for shielding are shaped between the bit lines 307 adjacent to wiring layers, to which the bit lines 307 are formed. The electrode wirings 307b for the shielding are not related directly to the operation of the semiconductor device, and are apparent wirings. Such electrode wirings 307b for shielding are inserted, and the circuit pattern of the semiconductor device is remarkably difficult to be decoded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element formed on a semiconductor substrate, having an electrode wiring formed on a wiring layer disposed via an insulating layer and connecting to the element, and having the element and the electrode connected thereto. The present invention relates to a semiconductor device having an integrated circuit formed by wiring.

[0002]

2. Description of the Related Art In order to analyze the function, operation mode, circuit mode, circuit pattern, stored data, etc. of an integrated circuit of a semiconductor device on which the integrated circuit is formed, an external connection conventionally provided in the semiconductor device has been used. There is a method in which a power supply is connected to a power supply terminal to supply an electric signal, and the input / output of the terminal signal is measured by an IC tester or the like. In order to analyze them, observe the circuit block configuration and the circuit pattern itself using a shape recognition device such as an optical microscope from the ground surface of the semiconductor layer. There is a method to observe on internal wiring.

FIG. 5 is a plan view showing an example of a circuit block in a semiconductor integrated circuit mounted on an IC card. As shown in FIG. 5, on the chip 501, an EEPROM (Electrically Erasable Prism) which is a nonvolatile memory is provided.
peripheral circuit such as a programmable read only memory (502) 502 and a voltage booster circuit 503 for writing / erasing the same, and a ROM 50 as a read only memory.
4. CPU 5 which is a central processing unit for performing calculations and controls
05, and RAM 506 as a temporary storage memory
Further, an MPU 507 which is a microprocessor for security authentication is formed. In addition, around the units, a data bus and an electrode wiring for power supply are provided, and a lead electrode pad 508 connected to the data bus and a terminal for external connection is arranged.

Incidentally, an EEPROM 502 and a ROM 504 mounted on such an IC card and an M
The PU 507 stores various important data such as a protocol required for communication, a number code for authentication, a usage amount, and a remaining frequency. Therefore, it is necessary to prevent these codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, from being read by a third party from the viewpoint of preventing forgery of the IC card. .

[0005]

However, in the conventional semiconductor device as shown in FIG. 5, the circuit configuration block is started by observing from the top, and the functional element circuit,
The arrangement of the EEPROM, ROM and MPU for authentication can be seen. In addition, by probing measurement using an electron beam, it was possible to easily read the contents of the memory element, skip the authentication itself by causing the MPU for security authentication to run away as a trigger and malfunction. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is intended to make it difficult to observe the circuit configuration of a semiconductor device and the contents of a memory element constituting the semiconductor device. The purpose is to:

[0007]

A semiconductor device according to the present invention comprises an element formed on a semiconductor substrate, a wiring layer disposed on the element via an insulating layer, and a conductive material having a light-shielding property. And electrode wiring formed on the wiring layer,
A semiconductor device provided with an integrated circuit including an element and an electrode wiring is newly provided with a shielding electrode wiring which is insulated and separated from the integrated circuit and formed between electrode wirings of a wiring layer and has a constant potential. I did it. Therefore, this semiconductor device
The layer below the wiring layer was covered with the electrode wiring and the shielding electrode wiring formed on the same wiring layer.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, an outline of the present invention will be described. Particular attention is paid to a certain wiring layer of the integrated circuit, and this is schematically shown. As shown in FIG. 1A, a source electrode wiring 102 and a gate electrode wiring drawn from a MOS transistor 101 formed on a substrate. 103 and the drain electrode wiring 104 are formed. At this time, each wiring has a pad electrode 1 for connection to the outside.
02a, 103a and 104a are respectively connected.
Note that these electrode wirings are made of a conductive material having a light-shielding property.

According to the present invention, the shielding electrode wiring 105 is formed in a region where the electrode wiring is not formed in the wiring layer, in a state where the electrode wiring constituting the integrated circuit is insulated and separated. It was made. However, for example, since capacitance between the source electrode wiring 102 and the source electrode wiring 102 is generated, the floating of the shielding electrode wiring 105 adversely affects the operation of the integrated circuit. For this reason, the shielding electrode wiring 105 is connected to, for example, a substrate on which an integrated circuit is formed, and is always kept at the same potential. By forming the shielding electrode wiring 105 in this way, it is difficult to recognize the circuit pattern by observing the integrated circuit from above.

In the manufacture of a semiconductor device as described above, for example, a photolithography technique is used as is well known for forming the wiring pattern.
There, a photomask (reticle) is used as an original. The shielding electrode wiring according to the above-described invention can be formed simultaneously with a predetermined wiring layer, and an inversion pattern of a wiring pattern for forming an integrated circuit is prepared on a reticle for forming the wiring layer. It will be good.

Hereinafter, the fabrication of the reticle will be briefly described. Here, formation of the wiring layer shown in FIG. 1 will be described. First, as shown in FIG. 2A, an original wiring pattern 201 for forming an integrated circuit is created. Next, as shown in FIG. 2B, an inverted pattern 202 of the original wiring pattern 201 is created. Then, for example, as shown in FIG.
The shielding electrode wiring pattern 202a is created by retreating the second pattern area by the minimum line width allowed by the pattern rule, for example, about 0.5 μm. Then, as shown in FIG. 2D, the reticle 2 for forming a wiring layer is formed by combining the wiring pattern 201 and the shielding electrode wiring pattern 202a.
10 may be formed. These operations can be performed automatically by using a well-known CAD tool. By inputting a circuit wiring design pattern, the shielding electrode wiring pattern is automatically inverted. Can be obtained.

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described.
In the first embodiment, a case will be described in which the above-described shielding electrode wiring is applied to an EEPROM. FIG.
1A is a plan view showing a configuration of a semiconductor device according to the first embodiment, and FIGS. FIG. 3D shows an equivalent circuit thereof. In the first embodiment, a layer in which a bit line is formed is provided with a shielding electrode wiring. As shown in FIG. 3, the semiconductor device includes an element isolation region 302 on a semiconductor substrate 301.
A floating gate 304 is formed in a region defined by a gate insulating film 303 via a gate insulating film 303, and a control gate 305 is formed thereon to constitute a memory cell.

A bit line 307 is formed on these elements via an interlayer insulating film 306. Here, FIG.
Looking at the cross section of the plane perpendicular to the direction in which the floating gate 304 extends in FIG.
A bit line contact 307a connected to the bit line 307 is formed from one of the source / drain 301a formed on the four semiconductor substrates 301 on both sides. In the first embodiment, the shielding electrode wiring 307b is provided between the adjacent bit lines 307 in the wiring layer on which the bit lines 307 are formed. The shielding electrode wiring 307b does not directly affect the operation of the semiconductor device, but is a dummy wiring. By inserting such a shielding electrode wiring 307b, it becomes extremely difficult to decode the circuit pattern of the semiconductor device.

By the way, this shielding electrode wiring 307b
Is made of a conductive material. Therefore, a capacitance is generated between the shielding electrode wiring 307b and the adjacent bit line 307. Here, the shielding electrode wiring 3
When the potential of 07b is completely floating, the bit line 307
, The potential of the shielding electrode wiring 307b also fluctuates, which adversely affects the circuit. For this reason, the shielding electrode wiring 307b is grounded to the semiconductor substrate 301 at the terminal end of the memory block, for example, and always has the same potential.

Usually, a memory device mounted on an IC card is not so large in capacity, and is a flash memory having a capacity of about 256 Kbytes designed according to the 1.5 μm rule. In this case, the wiring pitch is about 2 μm, and the above-mentioned shielding electrode wiring can be inserted between them. In this case, by inserting the shielding electrode wiring, the gap between the memory elements formed on the substrate is reduced.
About 50% can be shielded. Such shielding can reduce the entrance of optical excitation light by half. Then, reading of the stored contents of the memory device can be made more difficult.

Second Embodiment FIG. 4 is a plan view (a) and sectional views (b), (c), and (d) showing a configuration of a semiconductor device according to a second embodiment.
It is. In the second embodiment, a case will be described in which the above-described shielding electrode wiring is applied to a DRAM.
As shown in FIG. 4, the semiconductor device includes a semiconductor substrate 40
A gate electrode (word line) 404 is formed in a region partitioned by the element isolation region 402 on the first through a gate insulating film 403. Further, a source / drain 405 is formed on the semiconductor substrate 401 on both sides of the gate electrode 404,
These form a MOS transistor. In addition,
Two adjacent MOS transistors have a common drain

A cell plate 406 is formed so as to partially cover a region on one (source) of the source / drain 405 of the MOS transistor. A capacitor is formed by a part of the cell plate 406 and a region on one of the source / drain 405 (source).
The region 410 in FIG. 4A becomes one memory cell including one MOS transistor and one capacitor. Also, when viewed in a plane, the bit line 40 is orthogonal to the word line 404.
7 are arranged. The bit line 407 is formed on the word line 404 via the interlayer insulating film 408, and is in contact with the drain which is shared by the two adjacent MOS transistors.

In the second embodiment, in the same wiring layer where the bit line 407 is formed, the shielding electrode wiring 40 is arranged so as to be arranged between the bit lines 407.
7a was formed. This shielding electrode wiring 407
“a” is the same as in the first embodiment, and does not directly affect the operation of the semiconductor device, but is a dummy wiring. By inserting such a shielding electrode wiring 407a, it is difficult to observe the capacitor formation region from above, as is apparent from FIG.
Therefore, it is difficult to read the charge storage state by a method such as an electron beam.

The same as in the first embodiment,
The shielding electrode wiring 407a is made of a conductive material. Therefore, the shielding electrode wiring 40
A capacitance is generated between the bit line 7a and the adjacent bit line 407. Here, when the potential of the shielding electrode wiring 407a is completely floating, a signal propagating through the bit line 407 causes
The potential of the shielding electrode wiring 407a also fluctuates,
The circuit will be adversely affected. For this reason, the shielding electrode wiring 407a is grounded to the semiconductor substrate 401, for example, at the end of the memory block, and is always kept at the same potential.

In order to keep the shielding electrode wirings 407a always at the same potential, they may not only be grounded to the semiconductor substrate 401 but also as shown below. That is, the shielding electrode wiring 407a is connected to the potential supply wiring arranged in the wiring layer above the wiring layer of the bit line 407, and a constant potential is always applied to the shielding electrode wiring 407a by the potential supply wiring. You may. Further, the potential supply wiring may be arranged in the uppermost wiring layer made of a material having a light-shielding property, and the potential supply wiring may be formed so as to cover a required region. By doing so, the circuit configuration of the semiconductor device cannot be observed unless the potential supply wiring arranged in the uppermost layer of the semiconductor device is first removed. Then, if the potential supply wiring is removed to observe the circuit configuration of the semiconductor device,
The shield electrode wiring is in a floating state, and the semiconductor device does not operate normally.

[0021]

As described above, according to the present invention, a device formed on a semiconductor substrate, a wiring layer disposed on the device via an insulating layer, and a conductive material having a light-shielding property are provided. A semiconductor device having an electrode wiring formed in a wiring layer and having an integrated circuit formed by the element and the electrode wiring;
A new shielding electrode wiring is provided between the electrode wirings of the wiring layer, which is insulated and separated from the integrated circuit and has a constant potential. Therefore, in this semiconductor device, the layer below the wiring layer is covered with the electrode wiring and the shielding electrode wiring formed on the same wiring layer. As a result, according to the present invention, there is an effect that it is difficult to observe the circuit configuration of the semiconductor device and the contents of the memory element constituting the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an outline of the present invention.

FIG. 2 is a plan view illustrating an example of a reticle used when embodying the present invention.

FIG. 3 is a plan view (a), a sectional view (b), and (c) showing the configuration of the semiconductor device according to the first embodiment of the present invention.
And a circuit diagram (d).

FIG. 4 is a plan view (a) and a sectional view (b) showing a configuration of a semiconductor device according to a second embodiment of the present invention;
(C) and (d).

FIG. 5 is a plan view showing an example of a circuit block in a semiconductor integrated circuit mounted on an IC card.

[Explanation of symbols]

101: MOS transistor, 102: source electrode wiring, 103: gate electrode wiring, 104: drain electrode wiring, 105: shielding electrode wiring.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyuki Umino 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Masahiko Maeda 3- 19-2, Nishi-Shinjuku, Shinjuku-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. An element formed on a semiconductor substrate, a wiring layer disposed on the element via an insulating layer, and an electrode wiring formed of a conductive material having a light shielding property and formed on the wiring layer. And a semiconductor device provided with an integrated circuit including the element and the electrode wiring, wherein the integrated circuit is insulated and separated from the integrated circuit, and is formed between the electrode wirings of the wiring layer to have a constant potential. A semiconductor device comprising a shielding electrode wiring. 2. The semiconductor device according to claim 1, wherein said shielding electrode wiring is connected to said semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the shielding electrode wiring is supplied with a constant potential via a potential supply wiring formed in a layer different from the wiring layer. Semiconductor device. 4. The semiconductor device according to claim 3, wherein the potential supply wiring is disposed on the integrated circuit of the semiconductor device, and is formed so as to cover the integrated circuit while being insulated and separated from the integrated circuit. A semiconductor device characterized by being performed.