TW306068B - Flash EPROM structure - Google Patents

Abstract

A flash EPROM structure comprises of: (1) in each flash EPROM memory cell at least including M rows and 2N columns of memory array; (2) M word lines, each word line coupled to one row among flash EPROM memory cell; (3) N global bit lines; (4) data access circuit coupled to N global bit lines so as to make memory array be able to read and write data; (5) selector circuit coupled to 2N column and N global bit line of flash memory cell, supplying selective connection between two of 2N columns to N global bit line, so as to make N global bit line data be able to access 2N columns of flash EPROM array via data input/output circuit.

Description

A7 5. Description of the invention () The present invention relates to the manufacturing technology of flash EPROM, especially an improved structure of flash EPROM memory structure and data unit (DATA CELL). . Approved clothing (please read the precautions on the back before filling in this page) Flash EPROM is an increasingly common non-volatile storage integrated circuit. This flash EPROM chip has functions such as electromagnetic data erasure, data storage and writing, and data reading from the memory unit (MEMORY CELL). The memory cell in the flash EPROM is composed of what is commonly referred to as a floating gate transistor, and the memory cell uses the charging or discharging of the floating gate to store data. The floating gate is composed of a conductive material, typically using polycrystalline silicon (POLYS IL ICON) material, and a thin layer can be provided between the floating gate and the channel of the transistor Oxide layer or other insulating substances; and the control gate or word line (WORD LINE) between the shell (J can be provided with a second layer of insulation to be insulated. Ministry of Economic Affairs Central Standard Falcon Bureau employee consumption cooperation Du The storage of the data printed in the memory unit is achieved by the charging or discharging of the floating gate. The charging of the floating Wenji adopts the FOWLER-NORDHEIM wearing mechanism (TUNNELING MECHANISM), and this method can be used in the alarm and drain (drain), or between the anode and the source (source) by adding a very high positive voltage to achieve. Thus, it can make the electrons into the floating gate through the insulating layer. In addition, the floating gate charge The collapse mechanism (AVALANCHE INJECT) can still be used. This method is to use the electric field to generate high-energy electrons in the channel that can penetrate the insulating layer to reach the floating gate. When the floating gate is charged, the critical voltage for the memory cell to turn on will be Will rise , The critical calendar will exceed the voltage on the word line when performing the fetching action. Thus, when a charged memory -3- This paper scale is applicable to the Chinese national standard (CNS M4 specification (210X 297 mm)

V. Description of the invention () When the unit is addressed (ADDRESSING) while performing the picking action, the memory unit will not be turned on. This non-conducting memory unit can be regarded as the polarity (POLARITY) of the SENSING CIRCUIT to represent the state of zero or one (STATE) in the binary digital system. After the floating gate is discharged, it becomes the opposite state. The discharge method is usually the F-N tunneling mechanism, that is, between the floating gate and the drain or source of the transistor or between the floating gate and the substrate. For example, a large positive voltage can be applied between the source and the gate and the drain can be floating, so that the floating electrode will discharge through the source. Duo printing equipment for consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs --------- Installation (Please read the notes on the back before filling out this page) The positive voltage required for the charging and discharging of the floating gate is designed quickly An important limitation of flash EPROM, especially when the β-cell is under the memory cell size and process specifications. It can be found in the publications of Bergemont et al. (J and Belleza, Woo et al. And Kazprounian et al.) That the design of contactless array nonvolatile memory elements has become more and more The more important. The so-called isolated arrays include each other by buried diffusion: arrays of memory cells that are intimate with each other, and the buried layer diffusion can only be generated by periodic contact with metal bit lines The effect of silk stitching. Early flash EPROM designs such as Mukherjee et al., In the memory system, each memory cell needs to have a half (ha 1 f) metal contact (meta 1 contact). Because the use of metal contact It must occupy a large area in the integrated circuit and become the main obstacle to the development of high-density memory devices. In addition, as the Θ-inch of the device becomes smaller and smaller, the shrinkage of the chip area is affected by the adjacent source and The metal contact pitch (Pitch) on the bit line formed by the drain is limited, and this bit line-4-This paper scale is applicable to the Chinese national rubbing rate (CNS M4 specification (210X297 mm) A7 B7 Description () is used to retrieve the data in the storage unit in the array. Therefore, we hope to provide a flash EPROM memory unit, structure and manufacturing method, so that it can manufacture high-density non-volatile memory Circuit, and can overcome some problems caused by high programming and clearing voltage. Therefore, the present invention is mainly to provide a new isolated flash EPROM memory cell and array architecture M and manufacturing technology, and can produce A high-density segmentable flash EPROM chip is provided. This flash EPROM memory unit is mainly designed based on a unique drain-source-drain structure. Among them, a single source diffusion region is shared by two columns of transistors. In addition, the present invention also proposes a memory circuit architecture suitable for flash EPROM memory cells. Economy Ministry of Central Standards Bureau employee consumer cooperation du printing -----:-installed-(please read the precautions on the back before filling this page) So, in our invention Including flash EPROM transistor array. The first 'drain diffusion region (extended drain diffusion region), the extended source diffusion region and the extended first Two drain diffusion regions. Field oxide regions are grown on opposite sides of the first drain diffusion region and the second drain diffusion region. The control gate where the floating gate and the word line are located is perpendicular to the gate-drain-source-drain structure to form two columns of storage cells with a common source region. The common source diffusion region is coupled to the bit line through some selected transistors. The generation structure proposed in the present invention makes the drains of two columns in the #parallel parallel unit, a global metal bit line in the source and drain diffusions, and a virtual ground (virtual — 5 — This paper scale is applicable to Chinese national standards (CNS specifications (210X297mm)

5. Description of the invention () ground) Power supply, and this method is to couple most of the transistors in the vertical column to the virtual ground through some parallel conductors (such as buried diffusion area). In this way, the two columns of flash EPROM memory cells in each drain-source-drain structure of the flash EPROM only require a metal contact pitch. In this way, according to our invention, the integrated circuit module of the flash EPROM can be manufactured on the semiconductor substrate. This combined unit includes a memory cell composed of at least M columns and 2N rows of flash EPROM cells. Each of the M word lines is merged into one column of the M columns of flash EPROM cells, and includes N global bit lines. Data in and out of the circuit are coupled to N global bit lines, which causes memory array writes and writes. The selector circuit _ combines the flash EPROM cell of 2N columns with N global bit lines, so that N global bit lines and 2 of 2N columns are selectively connected, so To enable data to pass into and out of the circuit and pass to the 2N-column flash EPROM cell, these N global bit lines must be used. In addition, this structure can be expanded by M, so that a gold bit line is not only shared by two columns of cells but also shared by more columns. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --------- Installed-(please read the precautions on the back and then fill out this page) and mentioned in our invention, the memory array contains Many of the above-mentioned drain-source-drain structure segments. Because of this nature, the selector circuit also includes a paragraph selector circuit, and is coupled to a local bit line through the drain diffusion in the paragraph. The paragraph selector circuit selectively connects the memory cells in the first or second column of the known paragraph to one of the N bit lines. & D, the drain diffusion area becomes a local bit line, and the selector circuit includes one end connected to the first drain diffusion area and the other end spliced to one of the N global bit lines 6- This paper scale is applicable to the Chinese national standard (CNS > · Α4 specification (210X297 mm). The Ministry of Economic Affairs Central Standards Bureau employee consumption cooperation du printed A7 B7. Fifth, the invention description () The first electronic contact of a connected gold point Crystal. And one end of the second transistor is coupled to the second drain diffusion region and the second end is coupled to the aforementioned gold-tare contact. The first and second transistors are independently The selection lines of parallel word lines are controlled. The array structure can be made denser by reducing the number of necessary word line drivers. According to this requirement, each word line driver must drive many in parallel There are 8 word lines, for example, and the word lines driven by a word line driver belong to different paragraphs of each column in the paragraphs of the array. In this way, the selected word lines will be decoded by the paragraph selection circuit ( decoded), its function The use of the word line decoding circuit is exactly the same. The use of one word line driver for 8 word lines can greatly reduce the layout area. According to another aspect of the invention, the semiconductor base layer has the first conductivity ( fi rst conduct ivi ty type), and the first well area in the grassroots (well) · Bell belongs to the second conductivity type (second conductivity type), and in the first well area there is a second Well area. The memory cells of the flash EPROM are present in the second well area, so that during the charging process of the floating gate in the memory cell, at least one of the drain and the source may have a negative potential. In this way, the extremely high positive voltage required to charge the memory cell can be reduced by applying the FN through the gate to the FN. The discharge method of the array in the memory is also applied to the gate of the memory cell A negative potential. It must be added to the drain to use M to generate FN ^ P effect to discharge the memory cell. The negative electrical history value is also reduced. The lower voltage will make the integrated electrical appliances responsible for storage Write and clear The standard requirement is -7- This paper scale is applicable to the Chinese national standard (CNS specification (210X 297 mm) —1--I-: 1 1 1--I -I— HH taxi ^^^ 1 m ^^^ 1 II! -— 1 ^ 1 " ", τ (Please read the precautions on the back before filling in this page) Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, printed and printed A7 B7 V. Description of invention () Make components for miscellaneous It becomes easier to manufacture and more economical. At the same time, the endurance of memory is also ideal because the generation of hot holes during storage and writing is weakened. In the present invention, the “cleared” state of the array is equivalent to the charging of the floating gate, so the cleared memory cell is non-conductive when addressed, and the “storaged” state is equivalent to The memory cell is discharged, so that when the memory cell to be written to is addressed, it will be turned on. The definition method of this structure enables the clearing action to be performed without pre-programming. Another feature of the invention is that the array includes rows of redundant EPROM memory cells. This row of redundant memory cells is used to replace a row of memory cells in the main array that is addressed by a single word line or by a group of word lines coupled to a single driver. Because the state of discharge represents the state of being stored and written and uses a negative voltage for the operations of storing, writing and erasing, the redundant row can be used. Previous flash EPROMs cannot use redundant rows because they are confused with the failed rows in the main array. Because the failed row cannot be separated from the stored part, the memory unit in the failed row may develop into an over-evase state and cause leakage current (leakage current) in the array. ) And invalidate the column.

In this way, the flash EPROM integrated circuit of the present invention can be manufactured using a twin well process (twin well) process, in which the first conductivity region on the semiconductor substrate is the second conductivity, and the first conductivity region Contains the second well region and is the first conductivity. The flash EPROM memory cells are all located in the second well area, and have 2N vertical IJ and M row of 'decision flash EPROM memory [cell. 2N Longitudinal U —8 — This paper scale is applicable to Chinese national standard (CNS Bu 8 4 specifications (210X 297 mm) ^ m · nn. ^ ΫΒΚ 1 ^ 1 m fl ^ m \ 1 0¾, va (please read the back first Note: Please fill in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The description of the invention () The flash EPROM memory unit is composed of N pairs of columns and each pair of columns contains many Each paragraph is composed of a first source diffusion region extending in the first direction in the second well region, and a first drain diffusion region extending in the first direction and the first drain diffusion region and the first There is a certain gap between the second drain diffusion region and the source diffusion region. This is the drain-source-drain architecture formed by 2 columns of flash memory cells in a well-known paragraph. The first insulating layer is located On the base layer, there is also an insulating calendar on the first and second channel regions formed by the drain-source-drain structure, and there is also an insulating layer on the source and drain diffusion regions. The electrode of the floating gate ( electrode) is on the insulating layer between the two columns of memory cells in the paragraph. Second The edge layer is located on the electrode of the floating gate. In this way, each paragraph contains the first set of flash EPROM memory cells formed by the first memory cell of a pair of memory cells and a pair of memory cells The second group of flash EPROM memory cells formed by the second of each. Each of the M word lines is spliced to one row of the M flash memory cells. The subset formed by the M word lines ( Each item in the subset) is stitched to one of the first group of memory cells in a known paragraph and one memory unit of the second group of memory cells. In this way, each word line is associated with a known paragraph The two memory cells in each pair of columns in the series intersect. The array contains N global bit lines. The input and output circuits of the data are combined into N global bit lines and the data is written out and written (using storage and writing And / or clearing procedures) 2N-column flash EPROM memory cell. The selector circuit is coupled to the first and second drain diffusion regions in numerous paragraphs, and makes the 2N-column flash EPROM memory cell With N global bit lines-9- This paper scale is applicable National Standards (€ milk) - Eight 4 Specifications (210/297 mm)

In m iw nn 1--In · m nn ^^^ 1 0¾, va (please read the precautions on the back before filling in this page) Printed by the Ministry of Economic Affairs Bureau of Central Standards Staff Consumer Cooperative Α7 Β7 V. Description of invention () phase connection. The selector circuit selects two columns in the 2N column memory cell to be connected to each of the N global bit lines. In this way, the N bit lines can be used to input or output data from the 2N vertical flash memory cells. When storing, writing, and erasing circuits, a negative voltage must be applied to the global bit line during charging to charge the floating gate of the selected flash memory cell, and then to the selected flash memory cell. When the floating gate is discharged, a negative voltage must be applied to the word line; thus, the positive voltage required to be applied to the other terminal can be reduced. In this way, a unique array using a virtual ground structure can achieve a higher packing density. The basic unit of a memory array includes sections formed by two rows of memory cells using a drain-source-drain structure. This array structure has less interference with the unselected bit lines of the neighboring cell when writing and erasing memory cells. In addition, the design complexity of the Y-address decoder is also reduced, and the complexity of the Y-address decoder using an array of source-drain-source-drain structures is relatively high. In the layout of the array, the two memory cells share a metal pitch, so that the design rule of the metal pitch can be relaxed. After decoding, the two columns of memory cells are spun to the known gold line, and they can be spliced to the drain-source-drain segment using the selection transistors located on the left and right. This special left and The two selection transistors i on the right are combined into a group of several word lines, the height of which may reach 64, so that the speed can be accelerated and the interference caused by storage and writing can be reduced. -10- This paper scale is applicable to China National Standard (CNS) 44 specifications (210X 297mm) nn ^ ϋ «nfl ^ tm 1 · mi ^^^^ 1 -r (please read the notes on the back before filling this page ) Indo-Chinese A7 B7, Employee Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description () The array is designed so that the memory unit where the memory is written is turned on, and the voltage applied to the word line during storage is negative. In addition, the purpose of performing the clear operation is to make the memory cell non-conductive, and the voltages applied to the drain, source, and base calendar are all negative. These can reduce interference problems and the positive voltage required during operation. Finally, the array can still provide a replacement structure of redundant rows and columns, which was not available in the previous design. Other features and advantages of the present invention can be found in the description, detailed description and patent application scope of the drawings. Brief description of the figures: Figure 1 is a schematic diagram of the flash EPROM integrated circuit module of the present invention. Figure 2 is a drain-source-drain structure proposed by the present invention, virtual Ground structure and flash EPROM arrays and other embodiments. Figure 3 is a diagram of an embodiment using two columns of flash memory cells to share a gold bit line structure. Figure 4 is a block diagram of a segmented flash EPROM array with the function of using redundant rows to correct the failed memory cell rows in the main array ° Figure 4A is a storage and write operation performed according to the principles of the present invention 0 ^ 3 flow chart. FIG. 4B is a simplified diagram of a simplified VERIFY circuit according to the principles of the present invention. -11- This paper scale is applicable to China National Standard (CNS) ~ A4 specification (210X297mm) ^^ 1 m 1- i if taxi R〆 ^^^ 1 I-tl ^ i In i-—i- n ^ — U3, T (Please read the precautions on the back before filling in this page) A7 B7 5. Description of the invention () Figure 5 A-F is the first type of flash with expanded floating gate with M to increase the coupling rate Steps for manufacturing EPROM memory cells. Figures 6A-6G are the following six steps in sequence to manufacture another flash EPROM memory cell implementation body following Figures 5A-5D. Description of figures: 50 dotted line 51A, 51B paragraph 52, 53 column 54A, 54B virtual ground 55, 56, 57, 58 gold lute to diffusion zone contact 59 virtual ground gold lute wire 60A, 60B metal to diffusion zone contact 70, 71-bit line 70 _ 1 I product 75- 1, 75-2,... 75-N memory unit 76- 1, 76-2. .. 76-N memory unit 77 memory unit. Column consumption of employees of the Central Bureau of Standards of the Ministry of Economy. Cooperative printing --------- install-(Please read the precautions on the back before filling in this page) 78 buried diffusion source line 79,80 buried diffusion drain line 81,82 selection Transistors 83,84 metal global bit lines' 85 selection transistor 85A transistor-12- This paper scale is applicable to Chinese national standards (CNS & A4 specifications (210X297 mm)

SQGGoS A7 Printed B7 by Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economy V. Description of invention () 65A, 65B selection transistor 100 flash EPROM memory array 101 redundant memory unit 102 reference memory 104 word line and block selection Decoder 105 Virtual ground circuit 106 Mode control circuit 107 Sense amplifier 108 Negative voltage generator 109 Positive voltage generator 120 Column pair 121 First drain diffusion line 122 Source diffusion line 123 Second drain diffusion line 124, 125, 126, 127 Memory cell 128, 129, 130, 131 memory cells 135 column pairs 136 array-type dummy diffusion regions 137 source diffusion lines 138 block left selection transistor 139 block right selection transistor 140 metal contacts 141, 142, 143 line 144 block right selection transistor-13- n tm ^ m «n ^ — ^^^^ 1 ^^ — ^ 1 ^^^^ 1 ^^^^ 1 ^^^^ 1 -η. order * -port (please read the precautions on the back before filling this page) This paper scale is applicable to the Chinese national standard (CNS Μ4 specification (210Χ 297 mm) A7 printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Invention description () Block 145 left selection transistor 146 metal contact 150,151 vertical () Pair 152 metal bit lines 170 voltage source 170- 1, 170-2,... 170-N section 171 bit line 171-1, 171-2,... 171-H shared word line driver 172 lines 173-1, 173-2,... 173-N block Select driver 175 column select decoder 176 block decoder 177 row decoder 178 line 181 virtual ground line driver 182 line

183- 1,183-2 redundant array U 184- 1,184-2 redundant word line driver 185- 1,185-2 redundant block driver 186 redundant decoder 187 lines 190 page write write buffer 191 sense amplifier 198 unit- 14- This paper scale is applicable to China National Standards (CNS) · A4 specifications (210X 297mm) ^^^ 1 mu — ^ i ^ l. ^^ 11 κϋ ^ — β mB 1. Moxibustion, vs (please read the precautions on the back before filling in this page) Employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7. 5. Description of invention () 199 Reference voltage source 200 Electropositive region 201 field effect insulation region 202 field effect oxide layer 203 passes through oxide layer 204 floating gate 205 nitride layer 206,207 mask 208 arrow 213,214 drain diffusion region 215 source diffusion region 216,217 drain oxide layer 218 source Oxide layer 221 word line 230 floating gate 231 deposition layer 232 floating gate 234 sand layer 240, 241 spacer 242 deposition layer 250 nitride layer 600, 601,.  . 610 Block 650 sense amplifier 651 comparison circuit — 15 — This paper scale is applicable to the Chinese national standard (CNS ^ A4 specification (210X297 public daughter)) n ^ — In-—1-- ji 11 n ^ nt nn n ^ — ^ nm —1—--、 一 -eJ (please read the precautions on the back before filling in this page) A7 B7 Central Bureau of Standards and Economics of Ministry of Economic Affairs®cWorker * r cooperation. Du Yinwu 5. Description of the invention () Page 652 Retarder Latch The preferred embodiment of the present invention can be described in detail in Figure 1, which is a schematic diagram of the layout of the integrated EPROM integrated circuit sensor. The integrated circuit module shown in FIG. 1 includes a flash-type E1PROM memory array 100 and is called a redundant memory unit 101 that replaces the failed memory unit in the main array with M: The reference memory unit 102 and the sense amplifier 107 work together to sense the differential signal of the state of the memory unit in the memory array./ There are still word lines and block selection decoders coupled to the memory array 100 104, used for decoding the horizontal address of the memory array. Also coupled to the memory array 100 is a column decoder and a virtual ground circuit 105 for decoding the vertical address of the array. The data storage and writing structure 103 is coupled to the column decoder and the virtual ground circuit 105. In this way, the sense amplifier 107 and the data storage and writing structure rely on the memory array to enable the material to enter or be transferred out of the circuit. Flash EPROM integrated circuit can usually only be operated in chess mode, write mode and clear horizontal mode. Therefore, a mode control circuit 106 needs to be coupled to the array 100. Finally, according to the invention we have proposed, a negative voltage must be applied to both the gate and the drain in the memory write and erase modes. Therefore, it is necessary to have a negative voltage generator 108 and a positive voltage generator 109, and use M to generate various reference powers required in the # column. Both the negative voltage generator 108 and the positive voltage generator 109 are driven by a power supply voltage (power supply voltaqe) Vcc. -16- One _____--— This paper scale is applicable to Chinese national standard (CNSM4 specification (2 丨 0X297mm) i.  —Pm nn---n In I —r nn I--nn (please read the precautions on the back before filling this page) A7 B7 V. Invention description () Figure 2 shows two paragraphs in a large integrated circuit . The division of the paragraph is approximately along the dotted line 50, and the paragraph 51A is approximately above the dotted line 50, and the paragraph 51B is approximately below the dotted line 50. The first pair of columns 52 in paragraph 51A forms a mirror image in paragraph 51B along the global bit line pair (bit lines 70, 71), which is the second pair of columns 53. When we observe along the bit line, we can find that the memory segments are connected to the virtual ground lines 54A, 54B (buried diffusion) from the upper and lower ends, and 55, 56, 57, 58 are metal to the diffusion area contact ( metal-to-diffusion contact) o Virtual ground conductors 54A, 54B extend horizontally through the array and are connected to vertical virtual ground wires 59 via metal-to-diffusion contact 60A, 60B. Paragraphs appear repeatedly along the opposite direction of the virtual ground line 59, so adjacent paragraphs share one metal virtual ground line 59. As such, in the paragraph layout of FIG. 2, the memory cells of two transistors in each column require two metal contact pitches, and a metal contact pitch is required between the metal virtual grounds 59 of each paragraph. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs II -------— In mn ^^^ 1 1 ^ 1 1 tr (t I (please read the precautions on the back before filling out this page) Each pair of columns (52,53) of the pair of known bit lines constitutes a group of flash EPROMg memory units. For women, S memory units 75-1, 75-2 to ϋ75_N form the first group of fast Flash EPROM memory cells, and this is the first in the column of 77 pairs of memory cells. Memory cells 76-1, 76-2, to 76-N form the second group of flash EPROM memory cells, and This is the second column of the pair of 77. The first group of memory cells and the second group of memory cells share the same buried diffuse source line 78. Memory cells 75-1, 75-2, to 75- N pro-to the buried diffusion drain line 79. The memory 76-1, 76-2, to 76-N is stitched to the buried diffusion drain line 80. The selector circuit is to select the transistor 81 and Right selection -17- This paper scale is applicable to the Chinese national standard (CNS & A4 specifications (210X 297 mm) η A 7 ^ ϋ 〇d 8 Β7 V. Description of invention () composed of selective transistor 82, and separately Drain the dip lines 79,80 and stitch them separately To the gold-bite global bit lines 83, 84. Thus, the source of the transistor 81 is spliced to the drain diffusion line 79 and the drain is spliced to the metal contact 57. The source of the transistor 82 is spliced to the drain diffusion The drain of the line 80 is coupled to the gold contact 58. The gates of the transistors 81 and 82 are controlled by the signal TSELSA, and the flash memory cell column is coupled to the global bit lines 83 and 84, respectively. The polar diffusion line 78 is coupled to the drain of the selection transistor 85. The source of the selection transistor 85 is coupled to the virtual ground diffusion region line 54A. The gate of the transistor 85 A is controlled by the signal BSELSA. In addition, Two or more paragraphs in Figure 2 can share the word line signal, this is because the selection signal TBSELA above the block ft! Below.  TBSELB, BBSELA and BBSELB decoding. In one of our embodiments, eight paragraphs share the word line driver, and one sector (sector) encompasses eight paragraphs. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs --------- Policy-(Please read the precautions on the back before filling out this page) We can find that in our invention, the flash type The EPROM architecture is a sectored array. The advantage of this structure is that the source and drain of the transistor in the unselected paragraph will be separated from the voltage and current of the bit line and the virtual ground line when the EPROM performs the operations of writing, storing, and erasing. In this way, when performing the action of 謓, the leakage current in the unselected paragraph does not flow to the bit line, so that the efficiency of sensing (sensing) is improved. When performing storage, writing and erasing operations, the calendar and unselected paragraphs on the virtual ground and bit lines are separated from each other. X makes it possible to clear a section, and when the sections in a section have a total of> 9 word line drivers, whether it is a section or a block can be cleared. In practice, the bottom block selects the transistor (transistor 65 A, 65B) is not -18- This paper scale is applicable to the Chinese national standard (CNS Bu Λ 4 specification (210X297 mm) Employee consumption cooperation of the Central Bureau of Economics of the Ministry of Economic Affairs Du printed A7 B7__ 5. Description of the invention () Yes, it is necessary, Figure 3 is the circuit without transistors 65A and 65B. At the same time, these blocks select transistors in the adjacent section will share a bottom area Block selection signal. Another case is that the bottom block selection transistor (65A, 65B) is a single isolation (is〇la_ti ο η) transistor between the virtual ground terminal 6〇A, 6〇B Figure 3 is another array structure of fast-reading EPR0M according to the present invention. In this structure, 2 columns of fast-reading type £:? |? 〇} 4 memory cells share a single gold bit Fig. 3 is an array with 4 pairs of columns, each pair of columns includes ~~ source-drain structure flash EPROM memory cells. The first pair of columns 12 includes the first drain diffusion Line 121, source diffusion line 122 and second drain diffusion line 123. Word lines WL〇 to WL63, each word line They all intersect the floating gates of the columns in the memory cells in sequence. As shown in the figure, the first pair of columns 120 contains an I column of memory cells 124, 125, 126, and 127Θ. It is a memory cell that is stitched up to 2 to WL61. The other column in column pair 120 includes memory cells 128, 129, 130, and 131. Another pair of column pairs can be seen along the same column in the array 135 ° It has a similar structure to the column pair 12〇, and the two are mirror images of each other. As we can see, the transistor (such as 125) on the first column of the column pair contains The drain on the drain diffusion line 121 and the source on the source diffusion line 122. The floating gate region covers the channel region between the first drain diffusion line 121 and the source diffusion line 122. Word line WL1 is covered on the floating gate of the memory unit 125 to form a fast-reading EPROM. 19- This paper standard is applicable to the Chinese National Standard (CNS μΜ current grid (210X 297 mm) --------- Outfit-(please read the precautions on the back before filling in this page) Order A7 B7 for the consumer consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Description of the invention () Memory unit. Column pair 120 and column pair 135 share an array-type virtual ground diffusion region 136 (ARVSS). Vertical source pair 120Θ source diffusion line 122 will be referred to as ground diffusion region 136 Similarly, the source diffusion line 137 of the column pair 135 also depends on the ground diffusion region 136. As mentioned above, each pair of memory cells in the column pair 120 share a single gold line. It must include the block left selection transistor 138 and the block right selection transistor 139. Transistor 139 includes the source on the drain diffusion line 121 and the drain connected to the gold-contact 140 and the gate of the control signal BLTR1 coupled to the line 141. Similarly, the right-select transistor 138 contains the source on the drain diffusion line 123, called the drain connected to the gold contact 140 and the gate coupled to the control signal BLTR0 on the line 142. For example, ifct, the selector circuit includes transistors 138 and 139, and provides selective connection to the first drain diffusion line 121 and the second drain diffusion line 123, so that it can be connected to the line 143 via the metal contact 140 ( MTBL0). We can also find that the column pair 135 includes the block right selection transistor 144 and the block left selection transistor 145, which are also connected to the gold contact 146 in a similar manner. The contact point 146 is coupled to the gold line 143 to which the contact point 140 is also coupled. The Jin Ping line can be shared by two columns on the M after adding an additional selector circuit. The architecture of FIGS. 2 and 3 uses a drain-source-drain cell to form two columns of memory cells , And the adjacent drain-source-drain electrodes are independent of each other to prevent leakage currents from interfering with each other. This kind of structure can be expanded to include two -20 per unit when the leakage current of the test circuit is within the allowable range or can be controlled. This paper standard is applicable to the Chinese national standard (CNS> A4 specification (210X297 mm) n mV — ^ 1 ^ 1 — ^ ϋ —HI— n ml 、 One (please read the precautions on the back and then fill out this page) A7 _B7_ printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description () Columns. For example, the fourth and fifth diffusion lines can be added in an independent area to form a drain-source-drain-source-drain structure and four vertical columns can be provided in each unit. Column memory cells. Column pairs can be expanded horizontally and vertically to form an array of flash EPROM memory cells containing M word lines and 2N columns. This array only requires N metal bit lines, each One is screwed to a pair of flash memory cell columns via a selection circuit. Although the figure only shows four vertical columns U120, 135, 150 coupled to two gold bit lines 143 and 152 (MTBL 0-MTBL1) And 151, this result (J can still be repeated in the horizontal and vertical directions to form a large Array of flash memory cells. In this way, columns 120 and 150 that share a word line are copied horizontally to form a paragraph in the array. The paragraphs are copied vertically. A group of paragraphs with individual word lines (8 paragraphs) Re-threaded to a common word line driver can be regarded as a section of the array. Because of the virtual ground structure of the array, the required metal spacing is reduced and the most common line word driver is used. The layout can be reduced. In this way, the word line WL63 'and the word line WL63 share a word line driver. In the preferred embodiment, 8 word lines share a word line driver. Thus, each group of 8 rows of memory cells requires only one word The spacing of the line drive circuit. The left and right selection transistors (139, 138 in paragraph 120) of the additional decoding circuit can become the structure of the common word line. The disadvantage of the common word line structure is that when the section performs the clear operation, 8 lines of memory The cells are all connected to the same word line calendar, and will cause interference to the memory cells that have to be cleared. If this causes a problem with the known array, then this is caused by the interference The problem can be used to ensure that the removal actions of all sections are in accordance with the Chinese national standard (CNS LA4 specification (210X297 mm) ^^ 1 an ^ i UK I 1 ill—-I n I-«HI—, I (5J (Please read the precautions on the back before filling this page) A7 _B7___ printed by the Employee Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs 5. Description of the invention () Decode the paragraph containing all the memory cells coupled to the common word line driver To solve. For the case where 8 word lines share one driver, the smallest segment clearing action must be performed on 8 paragraphs. Figure 4 is a block diagram of a flash EPROM array to illustrate some features of the present invention. In this way, the flash EPROM memory combination unit shown in FIG. 4 includes the main flash EPROM array composed of the sections 170-1, 170-2, 170-3 to 170__, and each of the areas The segment contains 8 paragraphs (SEG0-SEG7). 171-1 '171-2, 171-3, 171-N are a set of common word line drivers, they are used to drive 8 paragraphs in each segment Common word line. The shared word line driver 171-1 can be used, and there are 64 shared drivers for the section 170-1. Each of these 64 drivers provides an output to line 172. Each of these outputs is used to drive the eight word lines in the corresponding paragraph in section 170-1. You can see in Figure 4 that these outputs are divided into 8 groups and each group has 64 lines. In addition, it is also the block selection drivers 173-1, 17 3-2, 173-3, and 173-N that are spliced to the array. Each of these block selection drivers drives a left and right block selection signal for each paragraph. These segments adopt the structure of Fig. 3, in which the pair of block selection signals BLTR1 and BLTR0 are supplied to 64 word lines of each group. In addition, the flash EPROM array contains N global bit lines. The N bit lines can be connected in series from a 2N-column flash EPROM memory cell, a data input circuit, and a sense amplifier 191. These N bit lines 171 are spliced to the column selection decoder 175. Similarly, the block selection drivers 173-1 to 173-N are also coupled to the block decoder 176. Shared word line driver 171-1 -22- This paper uses the Chinese National Standard (CNS) -Λ4 specifications (2! 〇X 297mm) (please read the precautions on the back before filling in this page) Printed by the Central Standard Falcon Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs A7 B7 V. Description of invention () to 171-N is received by Laihe Decoder 177 from the address on line 178 to the address signal. Relying on the column selection decoder 175 is a page storage write buffer 190. The page memory write buffer 190 includes N latches, which are respectively connected to N bit lines. In this way, one page of data is N bits wide, and each row of memory cells is two pages wide (page 0 and page 1). The pages in the known row can be selected using the left and right decoding plus M described above. The optional voltage source 170 is used to provide the reference potentials required by the flash EPROM memory array when performing read-only, write-write and clear operations. These reference potentials are shown by the word line driver 171- 1 to 171-N are transmitted with the bit line. The virtual ground wire in the array is coupled to the virtual ground wire driver 181, and the driver 181 and the array are called together. In addition, the reference voltage source 199 of the positively charged well area (P well) and the negatively charged well area (N wel 1) are also spliced to the corresponding well areas in the array, respectively. Thus, as we saw in Figure 4, 64 word line drivers (such as word line driver 171-1) must drive 512 (64 X 8) rows of memory cells in the array. With the additional decoding function of the block selection driver (173-1), the layout structure of the common word line can be used. The flash EPROM array structure according to the present invention includes a row redudancy structure as shown in FIG. 4. As such, W bit lines extend from the main array through line 182 to include section 183 -183-2 redundant array. The redundant array is driven by redundant word line drivers 184-1 and 184-2. Similarly, redundant block selection drives 185-1 and 185-2 are also stitched together. 23- This paper scale is applicable to the Chinese National Standard (CNS ~) Λ4 specification (210X 297 mm) -is »I I---. 11 -I--I ί --------I-- tn 1-- (Please read the precautions on the back before filling out this page) Employee Consultation &Cooperation; Cooperation, Social Printing System A7 B7 5. Description of invention () To redundant array. If a known memory cell is found to be defective during the test, this row and the other seven rows sharing the same word line driver will be replaced by the corresponding row in the redundant array 183-1 and 183-2 . In this way, the system must include a content addressable luemory (CAM) unit 198 and a redundant code feeder 186 for receiving address data. As mentioned in our invention, during the test, the failed memory cell rows in the main array will be confirmed, and the addresses of these rows will be stored in the CAM unit 198. When the address ADDR IH on line 178 matches the address stored in CAM unit 198, the coincidence signal is generated by line 187. The matching signal will invalidate the word line drivers 171-1 to 171-N in the main array. The redundant decoder 186 will drive the redundant word line drivers 184-1 and 184-2 and drive the redundant block selection drivers 185-1 and 185-2 to select the appropriate replacement row. Redundant row decoding can also be coupled to the decoding of redundant columns, which improves the production yield of flash E PROM (yielc〇. The column selection decoder 175 is spliced to the page memory write latch 190, and N strips Each line of the element must have at least one latch. At the same time, the column selection decoder 175 is also called the data input circuit and the amplifier circuit 191. The combination of these circuits becomes the flute of the data input and output of the fast closed EPROM array The decoding of redundant rows also provides the ability to correct short circuits between adjacent word lines. Especially when two word lines are shorted, the two word lines must be found from the redundant array to replace the corresponding word lines . In our proposed ^ Array Frame Meizhong '8 word lines share a word line driver, two sets of 8 word lines will be used to replace the corresponding two sets of 8 word lines in the main P train. , Two in the main array --- IIII! I,-installed, — 1 II order 1 II ^ I! | (Please read the notes on the back before filling this page) -24- Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs Printed A7 B7 V. Description of invention () Short-circuited word lines will be able to apply redundant lines In the array architecture we proposed, the memory cell adopts the mode of segment clearing, and charges the floating gate (the electron enters the floating gate). At this time, when a cleared memory cell is sensed, the memory The cell is non-conducting and the output of the sense amplifier is at a high level. Similarly, the page memory write of this structure discharges the floating gate (making electrons leave the floating gate), so that when sensing, one is written The memory cell is turned on. The operating voltage required to perform the write and write operation is to apply a 6 volt electric current to the drain of the memory cell to be written to make it a low (actually zero) threshold. State. Then apply a negative electrode of 8 volts to the gate and the source is floating or connected to a voltage of 0 volts. In Figures 5G and 5H, the base layer or the positively charged area is 200 BJ. IJ is grounded. This will cause Fowler -Nordheim discharges the floating gate with the effect. The clearing action is performed by applying a negative voltage of 8 volts to the drain, the gate is positive 12 volts, and the source is negative 8 volts. The positive electrical area 200 is bias To negative 8 volts. This will cause Fowler-Nordheim Dangerous effect M causes the floating gate to be 5 volts and the source to be 0 volts. This method will give the memory the ability to clear the segment, and will use the decoding of the word line to select the memory cell to be cleared. Clearing interference on the selected memory cell will cause a negative voltage of 8 volts on the drain, zero volts on the idle pole and negative 8 volts on the source. This is tolerable for memory cells because they will not The electronic notification in the memory unit has too much influence. Similarly, the note that shares the same bit line in the same paragraph "100 million unit meeting -25- This paper standard is applicable to China National Standard (CNS ~) Α4 specification (210X297 mm ) ----------- Installed -------- ordered (please read the precautions on the back before filling in this page) d〇6G〇Q A7 B7 V. Invention description () Available Write interference, and there will be 6 volts on the drain, the gate is zero volts and the source is floating or zero volts. In this situation, there will be no gate-to-source drive and therefore will not have too much impact on the memory cells. Memory cells that share the same word line but have different bit lines or are addressed When the memory cell is kept in a high level state, the interference state is 0 volts at the drain, negative 8 volts at the gate, and 0 volts at the source or floating. Similarly, this disturbing state will not have a great effect on the unselected memory cells. The process technology of the Shuangjing area is more precise, so the negative voltage can be applied to the drain and source diffusion areas. If no negative voltage is applied to the drain and the source, the coupling rate of the alarm potential to the memory cell is 50%, the voltage of the gate will require 20 volts and the junction between the floating drain and the drain at this time on) requires a voltage drop of 10 volts. To produce such a high voltage on an integrated circuit requires some special circuit design and process technology. Similarly, applying a negative voltage to the blue pole can reduce the positive voltage required for the drain when storing and writing. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Figure 4-A is the flow chart of the flash EPROM circuit of Figure 4 performing the storage and writing operations. The process begins by erasing the sector where the data is to be written (e.g., sector 70-1) (block 600). After the clear action is performed, the clear determination action is performed (block 601). Next, the page number (0 or 1) and paragraph code (1 to 8) relative to the input address are determined by the virtual controller (block 602). When the page number and paragraph code are set, the pager will load the food data (block 603). The page buffer may be N-bit data or 1-byte data to match some special storage and write operations. Next — 26 — This paper scale is applicable to the Chinese national standard (CNSI A4 specification (? JOX 297mm). The Ministry of Economic Affairs Central Standard Falcon Bureau employee consumption cooperation du printed A7 B7. V. Invention description () Step will perform an IIE inspection If the user does not perform the clear operation first, determine which memory cells need to be stored and written (block 604). When the data is placed in the page buffer, the memory write and write potential is applied and the paragraph starts to execute the storage and write operation (Block 605). When the save and write operation ends, the action of verifying the IIE will be performed to prove whether the stored and written page is correct. During the verification process, the page buffer corresponds to the memory unit that was successfully stored and written Will be turned off (block 606). The next algorithm uses M to determine whether all bits of the page in the page buffer are turned off (block 607). If not all are turned off, the algorithm will determine whether it has been executed If the maximum number of retries (block 610) is reached, if it is not the maximum number of times, then return to block 605 to perform the page storage and write again, so that the wrong bit will be stored again. Bits that have passed the test will not be saved and written again. This is because the bits corresponding to these bits in the page buffer have been set to 0 during the verification process. If they are in the box When the maximum number of retries is reached in 610, the algorithm will stop and the system will signal a failure to store or write. If in block 607, all the bits of the page are closed, the algorithm will determine the segment Whether the storage and writing of the page have ended, that is to say, all the pages in the section have been written and have been completed (block 608). This is a parameter determined by the central processing unit (CPU). If the paragraph has not ended the operation, The algorithm will return to block 602 and the appropriate page number and paragraph number will be updated. If the calculation ends at block 608, the algorithm will be finished (block 609). As we mentioned when discussing block 605 of FIG. 4A Arrival, storage and writing test-27- This paper scale is applicable to the Chinese national standard (('NS') Λ4 specification (210X 297 mm) m ^ i —Fn ti m nn fcm ^^^^ 1 — ^ 1 ·- -— I ^^^^ 1, one OJ (please read the notes on the back first Write this page) The Ministry of Economic Affairs, Central Bureau of Standards, Consumer Affairs, Cooperation, Du Printing, A7, B7. 5. Description of Invention () The proof circuit reinserts the data in the page buffer by clearing the proof one bit by one bit. So, The structure of the simplified segment as shown in FIG. 4B must be included in the flash EPROM. The array of sense amplifiers 650 is coupled to the comparison circuit 651. The other of the comparison circuit—Yu Yurenbei U is from the page punch M652. ¢ 0 Therefore, the data of one byte from the sense amplifier will be compared with the corresponding byte in the page processor. A pass / fail signal for this byte will be sent back to the page buffer 652 bit reset (bit reset) end. In this way, the bits passed in the page will be reset. When all the bits in the pager are reset or a group of retry save and write operations are completed, the entire save and write operation is completed. Figures 5A-5H are manufacturing steps of an embodiment of a flash EPROM array according to the present invention. Figures 5A-5G are not drawn to the scale they should be. Figure 5H is the final structure with approximate ratio. Figures 6A-G provide another method of manufacturing flash EPROM, and the initial steps are the same as before, as shown in Figures 5A-D. Like Figure 5H, Figure 6H is the final structure drawing with approximate ratio. Let us first introduce the process of Figure 5A-5H. The memory unit is manufactured using 0. C0MS process of 6 micron, double layer gold, triple well area (two well areas are in the array, the third well area is used for peripheral circuit) and three layer poly (polycrystalline silicon). The main steps for manufacturing the memory cell can be seen in Figures 5A-5H. The main manufacturing steps of the memory unit in the present invention can be illustrated from-5A to 5G. The first step of the production is shown in Figure 5A. First, the electropositive silicon crystal (P-si 1 icon) is the base layer of P-200 (substrate), and a 'approximately -28- is formed on it. This paper size is suitable for China National standard (CNS7 A4 specification (210X 297 mm) --- n -I I_ · III I--Ding. . . . .  . . One ---- ^ US.  T mouth " (please read the precautions on the back before filling in this page) Indochina A7 B7, Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description () 6-micron (ym) deep negatively charged well area NW-198 ( N-wel 1) and a large series of 3 micron positively charged well area PW-199 (P-well). When forming a negatively charged well, first use a photoresist mask to define the well area on the base layer. N-type dopant is then injected into the well area. After implanting the intervening substance, the photomask is removed, and the base layer is annealed at high temperature for a long time to drive and excite the negatively charged intervening substance to form a negatively charged deep well region. The positively-charged well area is formed in the negatively-charged well area by similar steps as described above. In the second step, two relatively thick field oxide regions (field oxide r * egion) 201, 201 extend in a direction perpendicular to the paper surface. This field oxide region is formed by the famous L0C0S field oxidation process . A temporary oxide layer must also be formed on the base layer, which is then removed to prepare a thin oxide layer on the base layer for subsequent steps. As shown in Fig. 5B, the thickness of the tunnel oxide layer 203 (Angstrom) is about 90 angstroms (Angstrom) as shown in Fig. 5C. A layer of poly 1 (first * layer poly) 204 of about 800 angstroms is deposited on the oxidized oxide layer. Then, a vapor layer 205 of about 200 angstroms is deposited on the poly 1 layer. What is shown in FIG. 5D is that a photo masking process is used to define the floating gate, N + source and drain diffusion regions. The photomasks 206 and 207 (photo mask) are used to protect the floating blue pole located on the layer 204 of the po 1 y 1 layer. As shown in the figure, all poly 1 layer 204M and nitride layer 205 are etched and removed except for the areas protected by photomasks 206 and 207 to expose the drain, source, and drain. As shown in the direction indicated by the arrow 208 in Figure 5D, then the negative charge is inserted into the note -29- This paper scale is applicable to the Chinese National Standard (CN ^) A4 specification (210X 297 mm) —H ------ II-.  -J—-I I- ^ (Please read the precautions on the back before filling in this page) A7 B7_ printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention () It is exposed in the positive electric well area 199 These areas can therefore align themselves with the floating gate and field effect insulation area. Fig. 5E shows that after the base layer is thermally coagulated, interfering substances are excited to form drain diffusion regions 213, 214 and source diffusion regions 215. In addition, the drain oxide layers 216 and 217 with a thickness of about 2,000 angstrom, the source oxide layer 218 and the oxide layers 225 and 226 on the side of the poly 1 layer 204 must be grown. The next step is to remove the nitride layer 205 on the floating gate, and then deposit a Poly 2 layer 219 of about 800 Angstroms on the Poly 1 layer 204, and inject a negatively charged intervening substance. The next step is the process of photo mask processing to define the range of poly 2 (second layer poly), and the range of poly 2 layer is the control of the subsequent deposition of the floating gate in M poly 3 (third layer poly) The effective area within the pole is shown in Figure 5F. The effective area of the floating gate must be gradually increased by deposition to increase the meshing ratio up to or greater than 50%. In the subsequent high temperature annealing step, the negatively charged intervening substances will be evenly distributed between poly 2 and poly 1 Between layers and make it have very small contact resistance. On the Poly 2 layer 219, a layer 180 of about 180 Angstroms must be grown. Finally, deposit a layer of p〇ly3 221 (as shown in Figure 1G) and a layer of sanding line (WSi2) 234 (as shown in Figure 1H) on the ON0 layer. Then the poly 3 layer is etched away to define the structure of the memory cell. As shown in FIG. 5H, the silicide layer 234 on the poly 3 layer 221 is used to improve the conductivity of the word line. Figure 5H is a more accurate representation of the proportion of memory cells of this structure. According to the process of Figure 5A- 五 Η, the width of the drain diffusion is about 0. It is 7 microns and is located between the field oxide layer 202 and the floating blue electrode 230 of the poly 1 layer. Similarly, the floating gate 230 formed by poly 1 layer -30- This paper scale is applicable to China National Standard (CNS) A4 specifications. (210X 297mm) I --------- • Pack one ------ order ------- (please read the precautions on the back before filling in this page) Central Standard of the Ministry of Economic Affairs A7 B7 printed by the Bureau Staff Consumer Cooperative V. Description of the invention () The width is also about 0.7 microns wide. The width of the source diffusion region between the floating interpolar regions 230 and 232 is about 1 micrometer. The width of the diffusion region 214 is about 0. 7 microns. The width of the source diffusion region 215 is 1. 0 microns, because the width of M is slightly widened during manufacturing so that the poly 2 layer can have alignment errors when deposited. If alignment control is used for a more precise process, the width of the source diffusion area can be further reduced. The approximate proportions of various units in the vertical direction are shown in FIG. 5H. The thickness of the through oxide layer 203 under the floating gate electrode 230 or 232 of the P〇 1 y 1 layer is about 90 angstroms. The thickness of the poly 1 deposition layer 230 is about 800 angstroms. The thickness of the oxide layer 216 above the drain diffusion region 213 and the similar oxide layer above the source diffusion region 215 and the drain diffusion region 214 is about 2,000 to 2,500 Angstroms, but after the process is completed, the thickness is only 1 The thickness of the side wall oxide in the poly 1 part of the floating gate 230 is about 600 angstroms. As shown in the figure, it merges with the thermal oxide layer 226 above the source or drain diffusion area. The thickness of the poly 2 deposited layer 231 is about 800 angstroms. The thickness of the ON0 layer 220 is about 180 angstroms. The thickness of the poly3 layer 221 is about 2,500 angstroms. The thickness of the sanded tungsten layer 234 is about 2000 angstroms. The thickness of the field-effect insulating region 202 of the finished product is between 6,500 and 5,000 ± °°. Fig. 5H shows a characteristic of the process shown in Figs. 5A to 5H. As we can see in Figure 5G, the ρο 1 y 2 deposit 233 only partially covers the drain diffusion 214. In Fig. 5H, there is another type of mask that extends the floating electrode of ρο 1 y 2 and passes through the diffusion region of the drain and is in line with field effect oxygen. Standard (CN ^) A4 specification (210X297mm) ---------. --- installation ------ booking ----- travel (please read the precautions on the back before filling in this page) A7 _B7_ printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Layer 202 is partially heavy. This change in the manufacturing process allows the floating gate to meet the various design requirements, and this can be achieved by changing the extension length and the reforming of the effective oxidation zone (1. Metal A meta llization layer and a passivation layer (not shown) are deposited on the circuit of FIG. 5H. As shown in FIG. 5H, in the flash using the drain-source-drain structure The floating gate structure in the EPROM memory cell paragraph is composed of a poly 1 layer 230 and a poly 2 layer 231. The purpose of the poly 1 layer 230 is to align the source and drain diffusion regions with each other. Poly 2 The layer 231 is used to extend the surface of the floating gate to improve the coupling rate. In the drain-source-drain structure, we can find that it is formed by the P〇1 y 1 layer 230 and the poly 2 layer 231 The floating idle pole is on the left of the memory cell and the floating gate formed by the poly 1 layer 232 and the poly 2 layer 233 is on the right side of the memory cell. In the figure, the two floating gates are almost mirror images of each other. Will make the floating pole to the drain pole in the drain-source-drain structure The extension of the diffusion area will not make the common source diffusion area shorter. The technology and layout of this memory cell has many advantages. The leg oxide layer has been grown before the source / drain implant of the array. In this way, the thinning of the oxide layer and the dopant depletion effect will be minimized. The source and drain placement of the memory cell will automatically align with the shape of Ploy 1. In this way, the length of the memory cell channel will be Can be fully controlled. 'This flash EPROM array can use wider metal design rules, especially the structure as shown in Figure 3. Source block transistor and memory cell source-32- This paper size Applicable to China National Standard (CNS) A4 specification (210X 297mm) ---: --------; installed ------ ordered --------- travel (please read first (Notes on the back and then fill in this page) A7 B7_ printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () The polar / drain diffusion areas are combined. This heavy area connects the two diffusion areas to each other Together, the field effect insulation area is used to isolate adjacent bit line pairs. Inside the bit line pair, the structure is flat. In addition, for the memory cell shown in FIGS. 5A to 5H, the effective gate stitch area seen from the control gate is the area size of poly 2 Therefore, by extending the poly 2 layer above the buried layer or diffusion region or field effect oxide layer, the low interlocking rate caused by the poly 1 layer can be compensated for, and the interpolar interlocking rate becomes equivalent. In addition, by extending the poly 2 layer, a variety of different engagement rates M can be achieved to meet the needs of different product applications. Another method of manufacturing the memory cell structure is shown in Figures 6A-6G. The initial manufacturing steps for this structure are the same as in Figures 5A-D. Therefore, FIG. 6A is the result of removing the photomasks 206 and 207 in the structure of FIG. 5D and depositing the nitride layer 250 on the area. As shown in FIG. 6A, the nitride layer completely wraps the poly 1 layer 204 of the floating gate. The next step is shown in FIG. 6B. Using an anisotropic etching method, the nitride layer 250 is placed on the floating gate. The portion above the polar poly 1 layer 204 and outside the edge M is removed. After the nitride layer is etched away, the crystal M must be annealed so that the interposer can penetrate further to form the drain diffusion regions 213 and 214M and the source diffusion region 215. In addition, the thermal oxide layers 216, 217 will grow above the drain diffusion and source diffusion, respectively. The nitride layers 205 and 250 will protect the floating source poly 1 layer 204M from the oxide layer growing above it. The next step is shown in FIG. 6C, which is to remove the remaining nitride layers 205 and 250, and expose the POLY 1 floating alarm element 204. The next step is shown in FIG. 6D, a POLY 2 Sedimentary layer 219 quilt -33- This paper scale is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1 II ---- H 11 m --- 11 * ij:-: I :, tT- ϋ-; `` n II ^ (please read the notes on the back before filling this page)

2. Description of the invention () On this structure, the poly 2 layer 219 is deposited to a thickness of about 1,500 to 2,000 angstroms and a negatively charged interposer is implanted. As shown in Figure 6, the port 〇1 ^ spacers (31:> 3 (^ 1 * ') 240 and 241 are located at the edge of the port 〇1; / 1 廇 appearance, and this is the advantage @ 对 ^ 齐" 1 stomach @ (p 1 aslna) ® is formed by etching the poly 2 layer by engraving technology. In the subsequent high temperature step, the negatively charged intercalator in the 1301 ^^ 2 deposited layer will be evenly Distribution. As shown in Fig. 6F, the ONO layer 220 is deposited on top of the floating electrode formed by the poly 1 layer 242 and the p〇ly2 spacers 240 and 241. In addition, the next step will be in the field effect insulation area The adjacent part of 201 and 0N0 layer 220 leaves the block 243 of p〇ly 1. However, there is no electrical contact in this area, so it will not affect the operation of the device. After the ON0 layer 220 is deposited, it will be Deposition-poly 3,500 Angstroms thick as the word line of the device. Figure 6G is the final step of the process. This step is a sand line layer with a thickness of 2,000 Angstroms above the poly 3 word line 221 234, Μ increases the conductivity of the component. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) Figure 6G is also of this structure Approximately proportional structure diagram. And we can see that the drain diffusion 213 and 214 are between the field effect insulating region 202 and the floating gate 204 and its width is 0.6 microns. The thickness of the floating gate p〇ly 1 deposition layer 204 It is about 0.15 microns. The source diffusion 215 is located between the Polly layers of the floating gate, and its width is about 0.6 microns. Compared with FIG. 5H, this structure has more than 9 spoons of source and pole. Diffusion zone 215, and this is due to the characteristics of P〇ly 2 spacers 240 and 241 stomach_% alignment. In the layout of the structure shown in Figure 6G, there is no need to have -34- Standard (cns) α4 specification (21Qx 297 Gong Chu) Employee consumption cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs Du Yin crack Μ Β7 5. Invention description () As shown in Figure 5H, the optical alignment with the poly 2 extension on the floating gate should be formed The required mask error tolerance tolerance (mask misalingnment tolerance) makes the structure shown in Figure 6G directly scalable when the process dimensions (dimensions) decrease without having to consider the tolerance tolerance of the mask alignment The thickness of each area in the vertical dimension is similar to Figure 5H. But The thickness of the poly 1 deposition layer 242 is about 1,500 to 1,600 angstroms. The spacers 240 and 241 extend outward about 2,000 angstroms above the source and drain diffusion regions. In another manufacturing method of the structure of FIG. 6G, No second layer of nitride 250 is deposited. However, during the annealing process of FIG. 6B, the oxide layer will grow on both sides of the poly 1 deposited layer. These oxide layers on both sides of the poly must be etched away so that there is a contact point between the poly 2 and poly 1 grown in the subsequent steps. However, if you want to touch the oxide layer on both sides of the poly 1 part 0 of the floating gate, you may also risk touching the oxide layer between the floating gate and the base layer. If this area is etched too deep, it may cause a short circuit between the poly 2 deposited layer and the base layer. Therefore, the steps shown in Figures 6A to 6G are preferred for many applications. Amorphous silicon (amor-phous silicon) can be used to replace the polysilicon used in the floating gate. Therefore, a new flash EPROM memory cell and array structure are produced. This structure can generate a high-density core array using a layout of memory cells in which two adjacent regional drain bit lines share a source bit line. At the same time, the layout has also been optimized so that every two columns of memory cells in the array use a single metal wire. In addition, due to the use of the common word -35- this paper standard applies to the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) ----------- installed-, ------ order-- ---- ^ (Please read the precautions on the back before filling in this page) A7 B7 V. Description of invention () The line structure further reduces the layout area, and the pitch of the word line driver does not affect the main array. size. The present invention makes it possible to clear sections due to the use of a segmentable architecture. The flash EPROM using this architecture has a redundant row design. These techniques will improve the reliability and characteristics of flash memory arrays. Flash EPROMs with negative channels (n-channel) have been manufactured. And these techniques can be used for the equivalent circuit of the positive channel (p-charmel). In addition, these techniques have been implemented in the design of flash EPROM memory cells. Many of the features of this architecture can be adjusted and applied to a variety of memory circuits. The above is only a detailed description of the preferred embodiment of the present invention, and for those familiar with this art, it is obvious to anyone who is within the spirit of the present invention and its changes. The scope of the present invention is defined by the scope of patent application under M and its synonym plus M. I 11-1 —m ml I 1---i-1 ^ ―------* I5JI .11 -1-1 -----IP— (Please read the precautions on the back before filling this page ) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs-36- This paper scale applies the Chinese National Standard (cm) Λ4 specifications (2 丨 0X2W mm)

Claims (1)

A8 B8 C8 1) 8 6. Scope of patent application 1. A flash EPROM structure, including: A flash EPROM memory unit includes at least mn columns and at least 2N rows of memory array; mn Word lines, each word line is coupled to one of the rows of flash EPROM memory cells; N global bit lines; data entry and exit circuits are coupled to N global bit lines, M enables memory arrays to be written and written Input data; and a selector circuit, coupled to 2N columns and N global bit lines of the flash memory unit, can provide selective connection between 2 columns of 2N columns and N global bit lines, M The data of N global bit lines can be accessed to 2hU in the flash EPROM array by data in and out circuits. 2. The structure of the flash EPROM as described in item 1 of the patent application scope, wherein the 2N columns of flash EPROM cells in the memory array include: N pairs of flash EPROM memory cells, each There are several paragraphs for the memory cell. Each paragraph includes: two regional bit lines that are stitched to the selector circuit; one regional source line that is stitched to the source reference circuit; employee consumption of the Central Standard Falconry Bureau of the Ministry of Economic Affairs Printed by Cooperative Society> Clothes order (please read the precautions on the back before filling in this page) The first group of flash EPROM memory cells in the first column pair, the first column pair is between two Between one of the regional bit lines and the regional source line; the second set of flash EPROM memory cells within the second column pair, whose second column pair is between two regional bits Between the other line of the yuan line and the regional source line; -37- This paper scale is applicable to the Chinese National Standard (CNS) _Λ4 specifications (210 X 2ί > 7 mm) A8 B8 C8 D8 VI. Patent application scope M words Lines form a subset of word lines, each of which is stitched to One memory cell in the first group of flash EPROM memory cells and one memory cell in the second group of flash EPROM memory cells; and wherein the selector circuit includes silk stitched to two regional bit lines and at least A paragraph selector circuit of a global bit line, M provides selective connection between the first and second groups of memory cells in the paragraph and at least one all-or bit line. 3. The structure of the fast-reading EPROM as described in item 2 of the patent application scope includes an insulating layer formed on the 2N column, and N global bit lines are formed on the insulating layer, and the paragraph selection circuit includes an insulated From the layer to the contact point of one of the corresponding N global bit lines, M and silk are connected to the circuit of the contact point and the two regional bit lines, M makes the contact point and the two bit lines selectively contact. · 4 · The structure of the flash EPROM as described in item 3 of the patent application scope, in which the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed n ^ f ί. -Ii--n ^ i ί m ί-i- II!:, ^ 5J (please read the notes on the back of the performance first and then fill in this page) The paragraph selector circuit has a first transistor for each paragraph, and the first end of the transistor is on the first Within the local bit line, and its second end is spun to the contact point; and the second transistor, its first end is located in the second regional bit line, and its second end is coupled to Contact Hei Zhan. 5. The structure of the quick question EPROM as described in item 1 of the patent application scope includes: a row decoder circuit for driving M word lines, the number of drivers included in the row decoder circuit is less than M word lines Count, when each driver is enabled by the row decoder circuit, one of the M word lines in the M word lines can be driven in parallel. -38- This paper scale is applicable to Chinese national standard (CNS specification (210Χ297mm) Qi Zou Central Standards Bureau sx consumer cooperation spit, printed six. Patent application scope 6. The structure of the flash EPROM as described in item 1 of the patent application scope, in which the first conductive base layer is provided in the semiconductor base layer, In the base layer, there is a first well area with second conductivity (we 1 1), and a second well area with first conductivity is provided in the first well area, in the flash EPROM memory unit, The source electrode and the drain electrode are located in the second well region so that when performing the operation of changing the content of the memory cell, a negative potential is applied to one of the source electrode and the drain electrode. 7. The structure of the flash EPROM as described in item 1 of the patent application scope, which contains columns over 2NM, the selector circuit provides between 2 columns over Μ and at least one global bit line Selective connection, so that the data of the M global bit lines can be accessed to the flash EPROMP vehicle through the data in and out of the circuit 2 materials longitudinal U U. 8. A flash EPROM structure , A floating gate transistor array is formed in the base layer having the first conductivity, which includes: a plurality of insulating regions extending in the first direction in the base layer, separated from each other, and relatively thick, Μ formed in the base layer Mutually independent areas; in mutually independent areas, there are several first drain diffusion regions extending along the first direction, and one side of each drain diffusion region is aligned with the insulating region; in mutually independent regions There are several first drain diffusion regions extending along the first direction, and each source diffusion region is separated from the first drain diffusion region, M is between the source and the first drain diffusion region in an independent interval Forming the 'channel' area; independent of each other There are several second drain diffusion regions extending in the first direction in the area, and each side of the expansion area is aligned with the insulation area, and the -39- winter paper scale is applicable to the Chinese National Standard (CNS) A? Specifications (210X297mm) ---------------------- < I " ^ (Please read the precautions on the back before filling this page) 4 € Qilang Central Standard Bureau B Industrial and Consumer Cooperative System. Sixth, the scope of patent application is divided into source diffusion areas. M forms a second channel area between the source and the second drain diffusion area in each independent area; the first insulating layer is located at each The base layer, the first and second channel regions, the source diffusion region M and the first and second drain diffusion regions in the independent regions; the electrode group of the first floating gate is located in the first insulating layer in the insulating region, On the first channel region; the electrode group of the second floating idle pole is located on the first insulating layer and the second channel region in the insulating region; the second insulating layer is located on the electrode group of the first and second floating idle electrodes; Several word line conductors, located on the second insulating layer, extending in the second direction, each passing through the source diffusion region and the first A thick insulating layer above the second drain diffusion region, and above the first floating anode electrode and above the second floating anode electrode, and forming several pairs of common source diffusion regions in corresponding independent regions Floating gate transistors; several data conductors; several select circuits (select circuits), each of which is in contact with the corresponding data conductor and is called one of the corresponding first drain diffusion regions and The corresponding data conductor contacts and couples to one of the corresponding second drain diffusion regions, so that the corresponding data conductor and the opposite first and second drain diffusion regions generate selective gate currents; Μ and the reference conductor (referene conductor) bonded to several source diffusion regions ° '9. The structure of the flash EPR〇M as described in item 8 of the patent application scope, further includes: on the word line The square has a layer of bit line insulation, and the document -40- This paper scale is applicable to the Chinese National Standard (CNS) a3 specification (210X297 mm) ......................... .... 装 ........... -V '口 (Please read the precautions on the back before writing this page) ABCD, Ministry of Economic Affairs, Central Bureau of Standards, Consumer Cooperation, Du Printing 6. Scope of patent application The conductor is placed above the insulation layer of the bit line. I 〇. The structure of the flash EPROM as described in item 9 of the patent application scope, in which the word line includes polysilicon (polys i 1 icon) material, and the data conductor includes metal. II. The structure of the flash EPROM as described in item 8 of the patent application scope, in which at least one of the selector circuits includes a selection circuit including a contact point, in contact with one of the data conductors, the first transistor One end is connected to the corresponding second end of the first drain diffusion region and is coupled to the contact point, the second transistor has a first end in the corresponding first drain diffusion region, and a second end is silk-bonded To the contact, and the second transistor has a silk joint to the second end of the contact in the corresponding second drain diffusion region. 12. The structure of the flash EPROM as described in item 8 of the patent application scope further includes: a first well region with second conductivity is provided in the semiconductor base layer, and a first well region is provided in the first well region A second well region with a first conductivity, wherein the source diffusion regions and the second drain diffusion region groups are formed in the second well region, so as to change The potential is applied to one of the source and the drain. 13. A flash EPROM structure, a base layer region having a first conductivity in a semiconductor base layer, which includes: forming a first well region with a second conductivity in the base layer region, and in the first well A second well area with first conductivity is formed in the area; an array includes at least M rows and 2N columns of flash-type EPROMIS memory cells, where 2N columns of flash-type EPROM memory [cells include: N pairs Quick-reading EPROM memory cells, each pair of memory cells contains multiple sheets of paper. The Chinese National Standard (CNS) A5 specification (210X297 mm) is applicable ..................... ...... Installed ................... Order (please read the notes on the back before writing this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The paragraphs covered by the patent application, each paragraph includes: The first source diffusion region extending in the first direction in the second well region extends in the first * direction in the second well region and the first * A source diffusion region separated by a drain diffusion region, M forms a first channel region between the source and the first drain diffusion region; in the second well region, the first * A second drain diffusion region extending in two directions and separated by the source diffusion region, M forms a second channel region between the source and the second drain diffusion region; at the base layer, the first and second channel regions, the source electrode The first insulating layer formed above the diffusion region and the first and second drain diffusion regions; the first floating gate electrode group 9 of the first insulating layer on a channel region of the first insulating layer on the second channel region A second floating gate electrode group; and a second insulating layer on the first and second floating gate electrode groups »thereby allowing each paragraph to include the first set of flash EPR 0M memories in the first pair of columns Cells, and the second pair of columns contains a second set of flash-type ROM cells; M word lines, each of which is spliced into one of the flash memory cells, and the M word lines form a subset The word line, each subset of the word line 'is stitched to the first set of designated paragraphs of the flash-type EPROM memory unit, Μ and the second set of designated paragraphs of the flash-type EPROM memory unit; —42 — This paper size is applicable China National Standard (CNS) A3 Specification (210X297) .................................... ^ —............ " (Please read the precautions on the back before writing this page) ABCD Kajiro Central Standards Bureau employee consumption cooperation du printing VI. Patent application scope N A global bit line; the data input and output circuits are combined into N global bit lines and the data is read out and written into the 2N column of 'flash-type EPROM memory cells; the selector circuit is screwed to the first in many paragraphs One and the second drain diffusion area, and connect the 2N column of fast-read EPROM memory cells with N global bit lines, the selector circuit selects the two vertical columns lj and N global regions in the 2N column of memory cells Each of the bit lines is connected, so that if you want to input or output data from these 2N column flash memory cells, you can use the N bit lines to add M to complete; When the electrode of the floating electrode of the flash EPROM memory cell is discharged, a negative electric calendar must be applied to the word line; and when the electrode of the floating gate of the selected flash EPROM memory cell is charged, at least the source diffusion area or A negative voltage is applied to one of the drain diffusion regions. 14. The structure of the flash EPROM as described in item 13 of the patent application scope, where the paragraph further includes: a word line insulating layer, located on the first and second floating gate electrode groups, the word line is Focus on the word line insulation layer; and the bit insulation layer, located on the bit line, and the global bit line overlapped on the word line insulation layer. As described in item 14 of the patent application scope The structure of the flash EPROM, in which the word line is composed of a polycrystalline δ, and the global bit line is composed of a metal. 16. The structure of the flash EPROM as described in item 13 of the patent application scope, -43- This paper scale is applicable to the Chinese National Standard (CNS) Al specifications (2Κ) 297 mm) I t < «- --------- I ------------- '-"% (please read the notes on the back before writing this page) 8 8 8 8 AB. Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 6. The selector circuit in each paragraph of the patent application includes a contact point through an insulating layer to one of the corresponding N global bit lines, and a silk stitch to the contact point With the first and second drain diffusion circuits, M provides selective contact with the first and second drain diffusion regions. 17. The structure of a flash EPROM as described in item 16 of the patent application scope, wherein the selector circuit of each paragraph includes a first transistor whose first terminal is located in the first drain diffusion region, The second terminal point is silk-bonded to the contact point; M and a second transistor, the first terminal point is located in the second drain diffusion area, and the second terminal point is bonded to the aforementioned Contact point. 18. The structure of a flash EPROM as described in item 13 of the patent application scope includes a row decoder circuit for driving M word lines, and the row decoder circuit includes fewer drivers than M word lines, When each driver is enabled by the row decoder circuit, one of the M upper word line groups in the M word lines can be driven in parallel, and the M word line groups in which the group is driven in parallel include coupling to the flash In the EPROM memory unit, several word lines that specify one of the several paragraphs of the global bit line. 19. The structure of the flash EPROM as described in item 13 of the patent application scope further includes a relatively thick insulating region, which extends parallel to the direction of the first and second drain diffusion regions in the paragraph, so that Paragraphs are independent of each other. 20. The structure of the flash EPROM as described in item 13 of the patent application scope includes a set of redundant paragraphs, at least one of which is compatible with the entire range corresponding to the column of each pair of flash memory cells The bit line includes a redundant decoder circuit that is coupled to the group, which uses a row or a row of memory cells in the redundant paragraph group to programmatically replace 2N vertical-44 Standard (CNS) A3 Specification (210X297 Gongchu) ...................... $ 4 ................ " ..... I (Please read the precautions on the back before writing this page) Printed by the Ministry of Economic Affairs, Central Standard Falcon Bureau ’s employee cooperatives 6. One or one row of memory in the memory unit of the patent application range unit. 21. A kind of flash EPROM structure, a base layer area with first conductivity in the semiconductor base layer, which includes-· a first well area with second conductivity in the first area, and a first well area in the first area A second well area with first conductivity in the area; an isolated second conductivity drain diffusion area in the second well area; an isolated second conductivity source diffusion area in the second parallel area, It is separated from the drain diffusion region, and a channel region is formed between the source and drain diffusion regions; the first insulating layer is located above the base layer, the channel region, and the source and drain diffusion regions; a floating gate electrode , Chongman on the first insulating layer on the channel region; the second insulating layer above the floating gate electrode; the control gate electrode on the second insulating layer above the floating gate electrode passes over the channel region to form a Flash EPROM transistor; a negative potential voltage source, used to provide a negative potential to one of the drain diffusion region and the source diffusion region when changing the charge in the floating idle electrode. 22. A flash EPROM structure, a base region having a first conductivity in a semiconductor base layer, which includes: a first well region having a second conductivity in the first region, and a first well region in the first region A second well region with first conductivity; an isolated drain diffusion region, which is of second conductivity and located in the first direction of the second well region; an isolated source diffusion region, which is of second conductivity It is located in the second well area -45- This paper scale is applicable to the Chinese National Standard (CNS) A5 specification (210X297mm) (Please read the precautions on the back before writing this page) Install * \ = b Jing Qilang A member of the Central Bureau of Standards. X. A8 B8 C8 D8 printed by the consumer cooperative. 6. The scope of the patent application M extends in the first direction and is separated from the drain diffusion area to form a channel area between the source and drain diffusion areas; The first insulating layer is located above the base layer, the channel region, and the source and drain diffusion regions; several floating gate electrodes, repeating the floating gate electrodes on the first insulating layer on the channel region The second insulating layer above; several controls on the second insulating layer The gate electrode, which extends in the second direction, crosses each floating gate electrode, intersects the source and drain diffusion regions, and M forms a number of flash EPROM transistors in the channel region; a data conductor; The gate electrode has a contact point with the data conductor and has a diffusion region that is affinity to the isolated drain diffusion region, and the gate current is between the isolated drain diffusion region and the data conductor; and The negative potential voltage source uses M to provide a negative potential to one of the drain diffusion region and the source diffusion region when changing the charge in the floating gate electrode. 23. A flash EPROM structure, including: a memory array composed of at least M rows and at least N columns of flash EPROM memory cells; M word lines, each of which depends on M rows of flash A row of memory cells in the type of memory unit; several bit lines, each of which is combined into a row of memory cells in the Ν column flash EEPROM memory unit; a data entry and exit circuit, which is stitched to several bits Line, M makes the memory array one 46 one paper scale applicable to China National Standards (CNS) Ai specifications (210X297 mm) ............................ Dress up ................................. color (please read the notes on the back before writing this page) Printed by ABCD Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics. 6. The scope of patent application can be used to write out and write data; a redundant memory cell array, including at least X rows and N columns of flash EP ROM memory cells, located at The flash memory EPRO MU memory cells of the N-rank redundant memory cells are referred to as the bit lines; X redundant word lines, each of which is combined into the flash EPROM memory cell redundant array X line One of the memory cells; and a redundant decoder circuit, called X redundant word lines combined in a redundant array, which uses a row or a row of memory cells in a redundant paragraph group to programmatically replace a row or A row of M memory units. 24. The structure of the flash EPROM as described in item 23 of the patent application scope, the N-row flash EPROM memory cells in the memory array include: M / 2 pairs of flash EPROM memory cells, each A pair of columns includes several paragraphs, each of which includes: two regional bit lines coupled to the selector circuit; one regional source line pinned to the source reference circuit; located on two regional bit lines The first group of flash EPROM memory cells between one of them and the regional source line and the first column in the column alignment; between the other regional bit line and the regional source line The second group of flash EPROM memory cells belonging to the second column of the column alignment; the M word lines form a subset of word lines, and each subset of word lines are stitched to the first group of flash EPROM memories Unit and a second group of flash Ef ^ ROM memory cells, M sub-word line composed of the M word lines includes a first group of flash EPROM memory cells and a second group of flash EPROM memory cells; -47 -This paper scale is applicable to China National Standard (CNS) a3 specification (210X 297mm) (please read first (Notes on the back will be written on this page) Installed _ 'Can be printed by the Central Standards Bureau of the Ministry of Economic Affairs Employee Consumer Cooperation Du printed A8 B8 C8 D8_ VI. Patent application paragraph selector circuit, coupled to two regional bit lines and at least one Global bit line, M provides the connection between the first and second groups of memory blocks in this paragraph to at least one of several bit lines; a prohibited circuit, M is redundant in at least a subset of several paragraphs When the extra decoder accesses the redundant array, the segment selector is prohibited. 25. The structure of the flash EPROM as described in item 24 of the patent application scope, wherein the several bit lines include N / 2 bit lines, and the paragraph selector circuit of each paragraph depends on N / 2 One of the bit lines, so that the data entry and exit circuit can be connected to the N-column flash EPROM memory unit via M / 2 bit lines. 26. The structure of the fast-reading EPROM as described in item 25 of the patent application scope, which includes an insulating layer on N columns, and wherein the N / 2 bit lines are above the insulating layer, paragraph selection The circuit includes a contact point that passes through an insulating layer to one of the corresponding N / 2 bit lines, Μ and a circuit called the contact point and two regional bit lines, Μ makes the contact point and two bits The element lines are selectively connected. 27. The structure of a flash EPROM as described in item 23 of the patent application scope, wherein the redundant array includes a set of redundant segments, at least one of which is bonded to correspond to each pair of flash EPROM memories The bit line of the cell, the redundant decoder circuit includes a circuit coupled to a group of redundant segments so that the memory cells in the redundant segment group can replace the memory cells in the N column. 28. The structure of the flash EPROM described above, in which the regional bit line and the regional source line in the several paragraphs are from -48-This paper scale is applicable to the Chinese National Standard (CNS) Ai specification (210X297 mm) Yes (please read the precautions on the back and then fill out this page) ABCD 3u6G〇8 6. The scope of the patent application is composed of the buried diffusion region of the semiconductor base layer. 29. The structure of the flash EPROM as described in item 28 of the patent application scope (please read the precautions on the back before writing this page) The paragraph selector circuit for each paragraph includes a first transistor, which The first end is connected to the buried diffusion area of one of the regional bit lines, and the second end is potted to the contact point; M and includes a second transistor whose first end is connected to another regional bit The buried diffusion region of the line, and its second end is coupled to the contact point. 30. The structure of the flash EPROM as described in item 24 of the patent application scope includes: a row decoder circuit for driving M word lines, and the row decoder circuit includes fewer drivers than M word lines When each driver is enabled by the row decoder circuit, it can drive one of the M word line groups in parallel among the M word lines, and the M word line groups that are driven in parallel include A number of word lines in one of the paragraphs of the designated global bit line in the flash EPROM memory unit; and wherein the redundant decoder circuit includes a driver for driving the designated row driver in the memory array Replace all rows with redundant arrays. -Printed by Qi Lang Central Lizhan Bureau M Consumer Cooperative 31.-A method of charging the floating gate of a flash EPROM transistor. The transistor has a source, a drain and a control gate. The methods include: A positive potential is applied to the control gate, a negative potential is applied to the source, and a negative potential is applied to the drain. '32. The method of charging the floating gate of a flash EPROM transistor as described in item 31 of the patent application scope, in which the flash EPROM memory unit is located at -49- This paper standard is applicable to China National Standard (CNS) A5 Specifications (210X297mm) A8 B8 C8 D8__ 6. Patent-applicable well area, positive well area is located in the negative well area on the base level, and further includes adding negative potential bias to the positive well area (Biasing) steps. 33. A method of writing data to a group of flash EPROM memory cells, including: putting the data into a buffer (Page buffer); using the buffer to stitch the bit lines of a group of flash EPROM memory cells And at least apply a write storage potential to the control electrode of this group of flash EPROM memory cells to perform the write storage operation; after the write storage step is completed, the comparison circuit compares the output data of the memory with the buffer (Page buffer ) Whether the data in the same is the same to verify (Verify) whether the write and store operations are wrong; Μ and when the output of the memory unit and the value in the buffer are the same, clear the corresponding bit in the buffer and ask if any data If it is still stored in Yuanchong, it will re-write and compare. 34. The method of writing data to a group of flash EPROM memory cells as described in item 33 of the application scope, wherein the step of writing and storing will cause the memory to discharge, and further includes flashing before writing and storing The steps of charging and discharging the floating gate of EPROM memory cell. Du Printing by Employees' Consumer Cooperation of Central Bureau of Standards of the Ministry of Economic Affairs .................. ^ ....................玎 (Please read the precautions on the back before filling in this page) 35. The method of writing data to a group of flash EPROM memory units as described in item 34 of the patent application scope, in which the step of writing and storing includes the group A negative voltage is applied to the control gate of the memory, and a positive voltage is applied to the drain of the memory cell to be discharged, and then another low positive is applied to the drain of the memory cell to maintain the charging state according to the data in the buffer. Voltage. -50- This paper scale is applicable to the Chinese National Standard (CNS) Ai specification (210X297 public love) A8 SuGG〇8 cs D8_ Six, patent application scope 36. Write the information to a group as described in item 35 of the patent application scope The flash EPROM memory cell method, the other one-the voltage is usually grounded. 37. The method of writing data to a group of flash EPROM memory cells as described in item 35 of the patent application scope, wherein the charging method for the floating alarm includes applying a positive potential to the control gate and The source and drain of the memory cell are biased with a negative potential. 38. The method of writing data to a group of flash EPROM memory cells as described in item 37 of the patent application scope, wherein the fast-read EPROM memory cells are formed in the positively charged well area, and the positively charged well area is located in the semiconductor In the negatively charged well area on the base layer, the step of charging the floating gate of the memory cell includes applying a negative potential bias to the positively charged well area. 39. The method of writing data to a set of flash EPROM memory cells as described in item 31 of the patent application scope, where if the memory cells are not correct after the actions of rewriting, writing and comparing are completed, the clearing and retrying are repeated Until the q memory unit is completely correct or the number of retries reaches a maximum value. -51- This paper scale is applicable to the Chinese National Standard (CNS) Ai Specification (210 X 297 mm) ....................... Installed ... ............ 1T -............... color (please read the precautions on the back before filling this page)