KR100859409B1 - Flash memory device and manufacturing method thereof - Google Patents

Abstract

The present invention is a plurality of word lines formed in parallel on each other on a semiconductor substrate, a plurality of high voltage transistors arranged so as to be orthogonal to the word lines between the word lines, respectively formed under the high voltage transistors, and orthogonal to the high voltage transistors And a flash memory device including a plurality of actives and a plurality of contact plugs formed on the exposed actives.

Flash, Block Switch, High Voltage Transistor, Wordline

Description

Flash memory device and manufacturing method

1 is a layout diagram illustrating a flash memory device according to the present invention.

2A is a layout diagram illustrating a connection structure according to a first embodiment of the present invention.

2B is a layout diagram illustrating a connection structure according to a second embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 206, 207, 214, 215: wordline

102, 202, 203, 210, 211, HVNa, HVNb: high voltage transistor

103, 208, 216: active

104, 201, 204, 205, 209, 212, 213, 318: contact plug

300: semiconductor substrate 302: gate oxide film

304: first conductive film 306: device isolation film

308 Dielectric Film 310 Second Conductive Film

312: metal film 314: junction region

316: insulating film

The present invention relates to a flash memory device, and more particularly, to a word line block switch unit of a flash memory device.

In general, in a NAND flash row decoder structure, a block switch includes 32 wordlines, one source select gate, and a drain select gate 1. It consists of 34 high voltage transistors each. When the high voltage transistor is turned off, no voltage is transmitted, and the word line source select transistor and the drain select transistor are in a floating state in which no current flows.

High voltage transistors that apply voltage to the word line perform two functions. First, it functions as a switch for applying a positive voltage in the read or program mode of the NAND flash device. When a positive voltage is applied to the gate of the switch high voltage transistor by an external command signal, the high voltage transistor is turned on and the pump voltage is applied to the word line. Second, when the cell is in the erase cell mode, the selected block is grounded, and the unselected block does not transmit voltage to the word line. Therefore, the gate of the high voltage transistor must be grounded, and each wordline node must be floated. If there is a junction leakage in the high voltage transistor or the breakdown voltage BVDSS is weak, the voltage applied to the well during erasing increases. In this case, if the switch transistor does not protect the elevated voltage, a leakage current may be transferred to the high voltage transistor, which may cause a chip erase defect in which the well voltage may be lowered during erasing.

However, as the degree of integration of flash devices has increased in recent years, the thickness of word lines and lengths between peripheral devices have to be reduced, and it is very unstable to use high voltage as a conventional device pitch.

Accordingly, the present invention is to arrange the high voltage transistor to be perpendicular to the word line direction to secure the length of the device and the margin between the devices to operate the device using high voltage stably, and to reduce the size of the chip by securing the margin .

The flash memory device according to the present invention includes a plurality of word lines formed parallel to each other on a semiconductor substrate. And a plurality of high voltage transistors arranged to be orthogonal to the word lines between the word lines. It is formed under each of the high voltage transistors, and includes a plurality of actives orthogonal to the high voltage transistors. And a flash memory device comprising a plurality of contact plugs formed on top of the exposed actives.

The distance between the high voltage transistor and the contact is at least 0.3 μm, and the distance between the high voltage transistor and the contact is formed to be farther than the distance between the end of the active and the contact.

Two high voltage transistors are further formed on top of the active, wordlines are respectively electrically connected to the contact plugs, and a high voltage is applied to some of the contact plugs.

In the method for manufacturing a flash memory device according to the present invention, a semiconductor substrate having an active and device isolation film is provided. On the top of the active, a high voltage transistor is formed that intersects the active orthogonally. An ion implantation process is performed to form a junction region in the exposed active. An insulating film is formed on a semiconductor substrate including a high voltage transistor. Contact plugs are formed on top of the junction region. A method of manufacturing a flash memory device includes forming word lines parallel to one another on an insulating layer.

The high voltage transistor is formed by stacking a gate oxide film, a first conductive film, a dielectric film, a second conductive film, and a metal film, and the metal film is formed of any one of WSix, W, Ta, Ti, TaN, or TiN.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a layout diagram illustrating a flash memory device according to the present invention. The flash memory device includes a plurality of memory blocks. The memory block includes a memory cell array. The memory cell array includes a plurality of memory cell strings, and each of the plurality of memory cell strings includes a plurality of memory cells. The plurality of memory cells are connected to a plurality of word lines.

In general, the structure of a flash memory device needs to maintain a gap between active and active, and contact and gate for breakdown voltage (BVDSS) of 30 volts or more. As the degree of integration increases, a conventional block pitch is secured. There are a lot of difficulties.

In particular, matching the lengths of the high voltage transistors and the peripheral devices and the spacing between the devices becomes increasingly difficult as the degree of integration increases. These factors include the length A of the high voltage transistor, the spacing B between the active end and the contact region, the spacing C between the high voltage transistor and the contact region, the spacing D between the active and the active, and the length E of the active. . Here, the length A of the high voltage transistor is usually formed to be 1.3 mu m in length. The spacing B between the active end and the contact plug must be greater than 1.80 μm in order for the device to use a voltage higher than 30V. The spacing C between the high voltage transistor and the contact plug has a close relationship with the breakdown voltage BVDSS, and generally should be kept farther than 0.70 mu m. In particular, when using a voltage higher than 33V, a distance greater than 0.80 mu m should be ensured. The distance between active and active (D) should ensure a distance greater than 0.60 μm when using voltages higher than 30V. In general, the active length E should be secured at a distance greater than 2.0 μm to increase the reliability of the device.

Therefore, in order to deliver a voltage higher than 33V to the word line, the pitch of the high voltage transistor used in the row decoder has a length of 2A + B + 4C + 3F + 2D. Where F is the length of the contact. All of these sums should have a two-pitch size longer than at least 8.85µm to drive stable operation. Therefore, the length of one pitch should be at least longer than 4.43 mu m. To meet these conditions, the wordline must be at least 60 nm thick.

In the present invention, by forming a high voltage transistor in a direction perpendicular to the word line, a margin is secured when using a high voltage. For convenience of description, a part of the block selection unit is shown. Each block selector includes a word line 101, a high voltage transistor 102, an active 103 and a contact plug 104.

The first block selector SB1 includes at least two word lines 101a and 101b and at least two high voltage transistors A 'and B'. On the active 103 where the high voltage transistors A 'and B' are not formed, a contact plug 104 connecting the lower structure and the upper structure is formed. First, the configuration of the present invention will be described mainly for configuration, and a detailed arrangement will be described with reference to the following drawings. When a voltage is applied to the first high voltage transistor A ', a high voltage is applied to the word line 101a. When a voltage is applied to the second high voltage transistor B ', a high voltage is applied to the word line 101b. Similarly to the first block selector SB1, the second block selector SB2 includes at least two word lines 101c and 101d and high voltage transistors C ′ and D ′. When a voltage is applied to the third high voltage transistor C ', a high voltage is applied to the word line 101c. When a voltage is applied to the fourth high voltage transistor D ', a high voltage is applied to the word line 101d.

For example, in a device composed of 32 word lines, if the first and third high voltage transistors A 'and C' control the 0th block, the second and fourth high voltage transistors B 'and D ') Controls the first block. That is, the first high voltage transistor A 'is connected to the 0th word line 101a of the 0th block to apply a high voltage to the wordline connected to the memory cells of the memory cell array unit. The second high voltage transistor B 'is connected to the sixteenth word line 101b of the first block to transmit the high voltage. In the second block selector SB2, the third high voltage transistor C ′ is connected to the sixteenth word line 101c of the zeroth block and applies a high voltage to a wordline connected to the memory cells of the memory cell array unit. . The fourth high voltage transistor D 'is connected to the 0th word line 101d of the first block to apply a high voltage to the word line connected to the memory cells of the memory cell array unit.

When a plurality of block selectors having such a structure are arranged in 17, all of the high voltage transistors controlling 34 word lines can be implemented.

At this time, it is important to secure the gap margin of each part by rotating the high voltage transistors A ', B', C ', and D' so as to be perpendicular to the word lines 101a to 101d. By changing the angles of the high voltage transistors A ', B', C ', and D', the margins such as the space between the high voltage transistor and the word line, the high voltage transistor and the contact plug, and the contact plug and the active are sufficiently secured. At this time, the distance between the high voltage transistor and the contact plug should be at least 0.3 μm. By securing the gap margin between the devices can facilitate the arrangement according to the increase in the degree of integration, it is possible to safely transmit the high voltage in the chip using the high voltage. In addition, by separating the word lines from one block to another, interference occurring between word lines may be prevented.

2A is a layout diagram illustrating a connection structure according to a first embodiment of the present invention. When two high voltage transistors 202 and 203 are formed on the active 208, one block including a contact plug 201 to which a high voltage is applied and a contact plug 204 and 205 connected to a word line Form a selection. In order to select a plurality of blocks in the memory device, the plurality of block selection units are arranged horizontally. The block selectors are arranged side by side (C1) and immediately next to other block selectors (C2).

The operation of the block switch unit is as follows. High voltage is applied to the contact plug 201. When a voltage is applied to the high voltage transistor 202, a channel is formed under the high voltage transistor 202. A high voltage is applied to the contact plug 204 through the channel and the high voltage is delivered to the word line 206.

2B is a layout diagram illustrating a connection structure according to a second embodiment of the present invention. In the case where two high voltage transistors 210 and 211 are formed on the active 216, one block includes a contact plug 209 to which a high voltage is applied and a contact plug 214 and 213 connected to a word line. Form a selection. A plurality of block selection units are arranged horizontally to select a plurality of blocks in the memory device (D1). Word lines are arranged above and below the block selection section on the layout. That is, the word line 214 is arranged on the upper side of the block selector, and the word line 215 is arranged on the lower side of the block selector. Block selectors are arranged side by side (D1) and immediately next to another block selectors (D2). That is, word lines are arranged between the high voltage transistors.

The operation of the block switch unit is as follows. High voltage is applied to the contact plug 201. When a voltage is applied to the high voltage transistor 202, a channel is formed under the high voltage transistor 202. A high voltage is applied to the contact plug 204 through the channel and the high voltage is delivered to the word line 206.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention. Referring to Figure 1 manufacturing method for the cross section of the H-H 'direction as follows.

Referring to FIG. 3A, the gate oxide film 302 and the first conductive film 304 for the floating gate are sequentially formed on the semiconductor substrate 300.

Referring to FIG. 3B, a vision process for forming the first conductive film pattern 304a and the gate oxide film pattern 302a is performed, and a portion of the semiconductor substrate 300 is etched to form trenches. An oxide film is formed on the trench and the first conductive film pattern 304a to fill the trench. A chemical mechanical polishing (CMP) process is performed to polish the first conductive film pattern 304a even when the first conductive film pattern 304a is exposed to form the device isolation film 306.

Referring to FIG. 3C, a dielectric film 308, a second conductive film 310 for a control gate, and a metal film 312 are formed on the device isolation layer 306 and the first conductive film pattern 304a. At this time, a portion of the dielectric film 308 is etched before the second conductive film 310 is formed so that the subsequent first conductive film pattern 304a and the second conductive film 310 are connected to each other. The metal film 312 is formed using tungsten silicide WSix.

Referring to FIG. 3D, an etching process is performed to form the metal layer pattern 312a, the second conductive layer pattern 310a, the dielectric layer pattern 308a, the first conductive layer pattern 304b, and the gate oxide layer pattern 302b. To form the high voltage transistors HVNa and HVNb. An ion implantation process is performed to form a junction region 314 in the exposed semiconductor substrate 300.

Referring to FIG. 3E, an insulating layer 316 is filled on the semiconductor substrate 300 including the device isolation layer 306, the high voltage transistors HVNa and HVNb, and the junction region 314. A contact hole is formed in the insulating layer 316 on the junction region 314, and the contact plug 318 is formed by filling the contact hole with a metal material.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by arranging the high voltage transistors of the block selector controlling the memory cell block to be perpendicular to the word line, it is possible to secure a gap margin between devices using high voltages, thereby reducing the overall chip size and providing a stable high voltage. The transfer operation can be performed.

Claims (9)

A plurality of word lines formed parallel to each other on the semiconductor substrate; A plurality of high voltage transistors arranged to be orthogonal to the word lines between the word lines; A plurality of actives respectively formed under the high voltage transistors and orthogonal to the high voltage transistors; And A flash memory device comprising a plurality of contact plugs formed on top of the exposed actives. The method of claim 1, And a distance between the high voltage transistor and the contact is 0.3 [mu] m. The method of claim 1, And a distance between the high voltage transistor and the contact is greater than a distance between the end of the active and the contact. The method of claim 1, 2. The flash memory device of claim 2, wherein the two high voltage transistors are further formed on the active part. The method of claim 1, And the word lines are electrically connected to the contact plugs, respectively. The method of claim 1, And a high voltage is applied to a contact plug that is not electrically connected to the word line among the contact plugs. Providing a semiconductor substrate having active and device isolation films formed thereon; Forming a high voltage transistor on top of the active orthogonal to the active; Performing an ion implantation process to form a junction region in the exposed active; Forming an insulating film on the semiconductor substrate including the high voltage transistor; Forming contact plugs on the junction region; And And forming word lines parallel to the active layer on the insulating layer. The method of claim 7, wherein And the high voltage transistor is formed by stacking a gate oxide film, a first conductive film, a dielectric film, a second conductive film, and a metal film. The method of claim 8, And the metal film is formed of any one of WSix, W, Ta, Ti, TaN or TiN.

Images