JPH11176938A - Semiconductor device pattern generating method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable shortening of a period required for the design of a semiconductor device pattern. SOLUTION: With respect to a layout pattern is given, at least one of the sides which form the layout pattern is designated, and when the designated side is moved by a required amount of movement, the designated side and sides which violate design standards are retrieved, the minimum amount of movement is selected from among the amount of movements of the designates side and the retrieved sides, when the designated side and the retrieved sides start to violate design standards, and the designated side is moved by the selected minimum amount of movement so as not to violate design standards.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for generating a semiconductor device pattern for drawing a basic layout of elements and wirings on a semiconductor substrate surface, and more particularly to an efficient layout design. The present invention relates to a semiconductor device pattern generation method and apparatus.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit becomes large-scale, it becomes difficult to design everything manually.
Computer-aided automation design techniques are commonly used. In the conventional automatic design of a semiconductor integrated circuit, for example, there are a gate array system and a standard cell system in which all gates are laid out using cells prepared in advance.

In the above-described automated design technology, basically, a plurality of cells (Cells) registered in a database called a cell library (CellLibrary) are used.
1) is realized. Such a cell is a circuit that integrates one function in a unit when designing an LSI. Simple cells include an AND circuit and an O
There is a logic circuit such as an R circuit. On the other hand, complex cells include ALUs and multiplexers. In particular, these highly functional and large-scale circuits are referred to as macro cells (Ma
cro Cell). The cells are usually optimally designed in advance to obtain the highest performance with the smallest occupied area. The more types of cells registered in the cell library, the less wasteful LSI can be designed.

Here, the above-described design of the cell itself is usually performed using a polygon editor (Polygon Edit).
r) by manual input. Further, in a symbolic design for creating a mask diagram by efficiently inputting a mask diagram by manual input and creating a mask diagram by inputting a symbol (symbol), a symbolic editor (Symbolic Edit) is used.
r) Further, in order to further reduce the size of the created cell, a layout pattern of such a cell is created using a compactor that compresses a redundant portion of the layout pattern while satisfying design rules.

[0005] Generally, this layout design
Transistor according to given design parameters,
Generating and arranging the layout patterns of semiconductor devices such as resistors and capacitors, and wiring operations between the layout patterns of the generated and arranged semiconductor devices. Conventionally, parametric cells have been widely used as a method for improving efficiency. This parametric cell is
The pattern data of a cell is represented by a variable, and an optimum cell can be realized by changing its value. Usually, a basic master cell is defined in advance with some parameters, and when creating individual cells, specific parameters are given to the master cell and the pattern of the master cell is modified. It is realized by.

As an example of typical software for realizing this method, Cadence (Cadence De., USA)
PCELLs (Sign Systems, Inc) are widely known. In this software, for example, MO
When generating a layout pattern in which the S transistors are AND-connected, the number of gates and the gate length L of the AND-connected layout pattern are different from the layout pattern of the MOS transistor which is the master cell shown in FIG. By giving the parameters and the gate width W as parameters, the AND connection layout pattern satisfying the design rule shown in FIG. 12B is automatically generated.

[0007]

However, the above-mentioned software has the following problems. Hereinafter, the problem will be described using a simple example.

First, as the simplest example, consider a case where a contact layout pattern shown in FIG. 13A is parameterized as a master cell. Here, as shown in FIG. 13A, here, the layout pattern of the contact 1 is composed of the contact hole 2 and the diffusion layer 3,
It is assumed that the contact hole 2 and the diffusion layer 3 form an inclusion relationship satisfying a predetermined design rule.

In the layout pattern obtained by extending this layout pattern in the X direction, for example, a telescopic movable portion (stretch line) indicated by a broken line 4 in FIG. The contact hole 2 and the diffusion layer 3 are formed when the contact hole 2 extends. At the time of the extension, the inclusion relation satisfying the above-described design rule is maintained.

Next, consider the case where the contact layout pattern shown in FIG. 14 is parameterized as a master cell. As shown in FIG. 14, here, the layout pattern of the contact 5 is composed of the contact hole 6, the contact hole 7, and the diffusion layer 8, and the contact hole 6, the contact hole 7, and the diffusion layer 8 form an inclusion relationship satisfying a predetermined design rule.

A layout pattern obtained by extending the layout pattern shown in FIG. 14 in the X direction, for example, as shown in FIG.
Is formed on the layout pattern of the contact 5 and extended symmetrically with respect to the stretch line 9. Here, a problem arises when the width of the contact hole 6 in the X direction and the width of the contact hole 7 in the X direction are independently changed. As shown in FIG. 15B, if the widths of the contact hole 6 and the contact hole 7 are equally extended, the diffusion is performed while maintaining the inclusive relation satisfying the design rule as in the case of FIG. Layer 8 can be stretched. However, FIGS. 15 (c) and (d)
When the width of the contact hole 6 and the width of the contact hole 7 are extended independently as in the above, that is, when the width after the extension is different, the diffusion layer 8 is extended to maintain the inclusion relation satisfying the design rule. In doing so, it is necessary to determine which of the contact holes is shorter in distance and to make the design rule satisfy with the shorter contact hole. For example, in FIG. 15C, since the distance b to the contact hole 7 is shorter than the distance a to the contact hole 6, the diffusion layer 8 extends so as to satisfy the design rule in the positional relationship with the contact hole 7. Must. On the other hand, in FIG. 15D, since the distance c to the contact hole 6 is shorter than the distance d to the contact hole 7, the diffusion layer 8 extends so as to satisfy the design rule in the positional relationship with the contact hole 6. Must.

As described above, even for the layout pattern having the simple inclusion relation as described above, it is necessary to make a very complicated decision depending on the value of the given parameter. Specifically, such a determination requires a new program to be added to the software, and it is a very complicated operation to actually perform the determination.

Although the above parametric cell can be applied to a hierarchical design, the following problem also occurs in such a case.

For example, it is assumed that the contact hole 6 shown in FIGS. 14 and 15 is a parameterized cell. It is assumed that layout patterns of different hierarchies exist inside contact hole 6 and that layout patterns of different hierarchies must maintain a predetermined distance from diffusion layer 8. In such a case, it is necessary to first determine the positions of the layout patterns of different hierarchies. However, since the contact hole 6 is a parameterized cell as described above, the diffusion layer 8 Must be newly added. This is a very complicated operation and is not practical.

The above-mentioned software is for deforming and generating a parameterized cell by a given parameter. However, there are cases where the layout pattern of the generated cell must be deformed after the cell is actually placed. obtain. For example, consider a layout as shown in FIG.

The layout shown in FIG. 16 includes a cell (a layout pattern of an arbitrary cell showing a layout pattern of an arbitrary cell) in which a design rule given between the parameterized cell 10 and the parameterized cell 10 must be satisfied. (Specific figures) 14, 15, 16, and 17 are arranged respectively. Also, the parameterized cell 10 is:
Here, the layout pattern of the capacitor
Specifically, it is composed of a diffusion layer 11, an electrode 12, and an electrode 13. As parameters, a capacitance C and an aspect ratio A are set. The parameter C is given by the size of the area of the electrode 12, and the parameter A is given by the aspect ratio (length / width ratio) of the electrode 12.

When the layout shown in FIG. 16 is created, first, as shown in FIG. 17, the capacitor 10 is generated and temporarily arranged. Then, the electrode 13 and the figure 16 are separated by a predetermined distance e so as to satisfy the design rule. Further, the diffusion layer 11 is separated from the predetermined reference position 18 by a predetermined distance f. Here, the layout pattern of the capacitor 10 must be modified by manipulating the parameters C and A in order to accurately position the capacitor 10, that is, to set the distances e and f to the minimum separation distance. Must. Next, the electrode 12 and the figure 14 satisfy the design rule and are brought as close as possible. Here, similarly to the above, it is necessary to modify the layout pattern of the capacitor 10 by operating the parameters C and A.

As described above, it is a very complicated operation to change the layout pattern in relation to the surrounding figures by manipulating the parameters of the arranged parametric cells.

The present invention has been made in view of the above circumstances, and an object of the present invention is to facilitate generation of a layout pattern of a semiconductor device and to facilitate deformation of the generated layout pattern. Another object of the present invention is to provide a method and an apparatus for generating a semiconductor device pattern capable of shortening a period required for designing a semiconductor device pattern.

[0020]

According to a first aspect of the present invention, at least one side constituting a layout pattern is specified for a given layout pattern. When the specified side is moved by the movement request amount, the specified side and the side that violates the design standard are searched, and the specified side and the amount of movement until the searched side violates the design standard are searched. Among them, the smallest one is selected, and the designated side is moved by the selected minimum movable amount.

According to a second aspect of the present invention, for a given layout pattern, a first step of designating at least one side constituting the layout pattern;
A second step of adding a side that must move at the same time as the specified side to the specified side, and, if all the specified side and the added side are movable, the specified side and addition A third step of searching for a specified side and a side violating the design standard when the specified side is moved by the movement request amount; and until the specified side violates the searched side and the design standard. A fourth step of selecting the smallest one of the movable amounts, and a fifth step of moving the specified side by the selected minimum movable amount and subtracting the minimum movable amount from the required movement amount. In the case where the requested moving amount remains, the specified side is designated as the side which is the target of the minimum movable amount obtained in step 5 and the side which must be moved at the same time. The sixth step to add to the side It has the door, until the amount of movement required is eliminated, and repeating the above steps 3, 4, 5 and 6.

According to a third aspect of the present invention, there is provided an interpreting unit for decomposing a command input from the outside into a moving command of a side of a graphic to be processed, and a designated side receiving a moving command from the interpreting unit. A search unit for finding the specified side and a side that violates the design standard when the specified amount is moved by the movement request amount; and a search side for the specified side and the design standard based on the search result of the search unit. An execution unit that selects the smallest one of the movable amounts up to the violation and moves the specified side by the selected minimum movable amount; and an interpreting unit, the search unit, and the executing unit. It is characterized by including a control unit for controlling the operation, and an interface unit for connecting the interpretation unit, the search unit, the execution unit, and the control unit to the outside.

According to the present invention, when a layout design of a semiconductor device is performed, when at least one side constituting the layout pattern is moved with respect to the layout pattern initially tentatively arranged, the layout pattern is actually designated. If the edge has moved the required amount,
The specified side and the side that violates the design standard can be easily searched by using the search function of the ordinary layout editor. By selecting the smallest one and moving the specified side by the selected minimum movable amount,
Layout patterns can be generated efficiently.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a hardware configuration of a semiconductor device pattern generation device according to an embodiment of the present invention.

As shown in FIG. 1, in the semiconductor device pattern generating apparatus according to the present embodiment, a workstation WS21 is used as an environment in which a layout editor 19 and a partial compactor 20, which is a feature of the present invention, are used. The WS 21 has a central processing unit CPU (not shown) as a basic component thereof, and includes a basic system of the WS 21, a layout editor 19, and a storage device (not shown) such as a ROM in which a program including the partial compactor 20 is stored. I have. The WS 21 is connected to an external storage device 22 such as a hard disk, a display device 23, a keyboard 24, a mouse 25, and the like.

FIG. 2 is a diagram showing a software configuration of a partial compactor which is a characteristic portion of the semiconductor device pattern generation apparatus according to the embodiment of the present invention.

As shown in FIG. 2, it comprises an interpreting unit 26, a searching unit 27, an executing unit 28, a control unit 29, and an interface unit 30. The interpreting unit 26 decomposes a command input via the interface unit 30 into a command for moving a side of the graphic to be processed. In response to the movement command, the search unit 27 obtains an area in which the designated side is movable. Here, the graphic (layout pattern) to be processed by the partial compactor and the given design rules and constraints are stored in the external storage device 22 in FIG. The search unit 27 determines such a design rule,
A search is made for a movable area on the specified side that satisfies the constraint condition. Then, the search unit 27 transfers the search result to the execution unit 28. The execution unit 28 moves the designated side based on the search result transferred from the search unit 27,
Update the target figure. The control unit 29 includes the interpretation unit 2
6. It controls the operations of the search unit 27 and the execution unit 28.

On the other hand, the layout editor of the semiconductor device pattern generating apparatus according to the present embodiment is generally used, and is usually EWS (Engineer).
(Ring Work Station) to create, edit, and modify layout diagrams. The partial compactor, which is a feature of the present invention, has a function for searching for a figure including coordinate values (x, y), a region ((x1,
The operation of the partial compactor as described above is realized by utilizing the function of searching for a figure existing in (y1), (x2, y2)).

Next, the operation of the partial compactor, which is a feature of the present invention, will be described with reference to the drawings. FIG. 3 is a flowchart showing a processing procedure of the operation of the partial compactor. It is assumed that, prior to this processing, the layout positions of the target graphic and the peripheral graphics have been once determined.

In FIG. 3, first, in step 1,
A set of sides to be moved, a moving direction, a required moving amount, a design rule, and an arrangement position of a figure are set. The movement target side set is a set of sides requested to be moved specified by the designer. The moving direction is the moving direction of the specified side requested by the designer. The movement request amount is a movement amount of the designated side requested by the designer. The design rule is a design standard given in advance. The arrangement position of a figure is a provisional arrangement position of a figure to be subjected to the partial compactor and a figure around the figure.

Next, in step 2, from the predetermined constraint conditions, a side which must be moved at the same time as the side in the set of moving sides set in step 1 is selected, and the selected side is selected as a moving object. Add to the side.

Next, in step 3, it is determined whether or not a fixed edge exists in the set of moving target edges set in steps 1 and 2, and if there is a fixed edge, the process ends.

Next, if it is determined in step 3 that there is no fixed edge, then in step 4 the movable amount is determined for each edge in the set of target edges determined in step 1 above. . Then, the smallest value is selected from the obtained movable amounts. Here, specifically, when calculating the movable amount of each side, the search function of the layout editor described above is used, and the moving direction, the required moving amount, and the design rule set in step 1 are considered. Then, all the sides existing in the determined search area are selected, and the movable amount for each side is calculated. Then, the one with the smallest moving amount is set as the minimum value.

Next, in step 5, each side of the moving target side set is moved by the minimum value of the movable amount obtained in step 4 above. Then, the above step 1
Updates the temporary arrangement position of the figure set in. Further, the minimum value of the movable amount actually moved here is subtracted from the required movement amount set in step 1 and the result is updated as the required movement amount.

Next, in step 6, it is determined whether or not the requested movement amount has become 0 as a result of the movement in step 5 described above. If it is determined that the value has become 0, the process ends here.

Next, if it is determined in step 6 that it is not 0, then in step 7 the side that is the object of the minimum movable amount obtained in step 4 and the side Edges that need to be moved at the same time are newly added to the set of edges to be moved, and the process returns to step 3.

In this way, the steps 3 to 7 are repeated until there is a fixed edge in the set of edges to be moved in the above step 3 or the requested moving amount at that time becomes 0 in the above step 6. Will repeat.

Next, the operation of the partial compactor will be described in more detail using a specific example. For example, the side 32 which is one side of the figure 31 as shown in FIG.
Consider a case in which the object moves by a distance g in the direction. Side 32
If there are no obstacles when moving,
The figure shown in FIG. 4B is obtained.

On the other hand, when there is a figure which becomes an obstacle, the processing by the partial compactor is performed as follows. For example, it is assumed that there are a graphic 33 and a graphic 34 which become obstacles as shown in FIG. It is assumed that there is a separation request between the graphic 33 and the graphic 31 and between the graphic 34 and the graphic 31 based on the design rule. In such a case,
Request for separation between FIG. 31 and FIG. 33, ie, FIG.
As shown in FIG.
It can be seen that No. 2 cannot move the entire distance g in the X direction. As a result, the movement of the side 32 ends at a position before the position where all the distances g have moved. In this movement, the figure 34 is not considered at all, and moving the side 32 in this manner is a partial compactor.

More specifically, as shown in FIG. 6A, a search area 36 obtained by expanding a rectangular area formed by a side 32 and a distance (movement request amount) g in consideration of a design rule is used as the layout editor. And the side 35 can be taken out. Then, the side 32 may be moved by the value obtained by subtracting the design rule (minimum separation distance) from the x coordinate of the side 35. In general,
For example, as shown in FIG.
When the user wants to move the object by a predetermined distance in the direction, a plurality of figures (here, FIG. 40 and FIG.
There is a case where 1) exists. In such a case, it is only necessary to select the one with the smallest moving amount. Further, a figure which does not hinder the movement of the side 38 can be efficiently removed from the search object by using the search function of the layout editor.

Next, a description will be given of the operation of the partial compactor in the case where the obstructive figure is movable, which is different from the above case. For example, as shown in FIG. 7A, a case where the figure 45, the figure 46, and the figure 47 are temporarily arranged, and a case where the figure 45 is moved by the distance i in the x direction. In such a case, if the figure 45 is to be moved, the figure 46 and the figure 47 become obstacles, but since both are movable, the figure arrangement is as shown in FIG. 7B.

More specifically, first, the movable amount of the figure 45 is obtained. Here, the movable amount is a distance until the graphic 45 collides with the graphic 46. That is, FIG.
The arrangement is as shown in FIG. Then, the actual movement amount is subtracted from the distance i, which is the first movement request amount, and the result is updated as a new movement request amount. Then, if the updated movement request amount is not 0, the movement is further performed. At this time, the graphic 46 is added to the graphic 45 and moves at the same time.

Further, the movable amount of each of the figures 45 and 46 is obtained. Here, the movable amount is a distance until the graphic 45 collides with the graphic 47 and a distance until the graphic 46 collides with the graphic 47. Since it is necessary to move the figures 45 and 46 at the same time, two figures are moved by the smallest one of them.

Thereafter, in the same manner, the movement request amount is updated, the figure 47 is added to the figures 45 and 46, the respective movement request amounts are calculated, and the smallest one of them is regarded as the total movement amount. For example, the arrangement shown in FIG. 7B is obtained.

Here, in FIGS. 4, 5 and 6, the operation of the partial compactor is described as movement of a side, while in FIG. 7, movement of a figure is described as movement of a figure instead of movement of a side. This corresponds to, for example, the side 49 in FIG.
Is moved in the x direction, if there is no constraint between the side 49 and the side 50,
Even if the side 49 moves, the side 50 does not move, which means that the width of the figure 48 eventually becomes narrower. On the other hand, if the width is fixed, that is, if the side 49 moves, the side 50 moves. The case where the figure also moves corresponds to the case where the figure of the side 49 and the figure of the side 50 move at the same time. This constraint condition can be represented, for example, by an equation or an inequality between the coordinate values of the sides.

Next, an example in which the above-mentioned partial compactor is applied to deform the layout pattern of the generated cell will be described. The layout pattern shown in FIG. 9 is specifically a capacitor and has two rectangles 57 and 58.
And an electrode 55 made of one rectangle,
Diffusion layer 5 which is an outer frame including electrode 54 and electrode 55
6. As parameters, a capacitance C and an aspect ratio A are set, the parameter C is given by the size of the area of the electrode 55, and the parameter A is
5, respectively. As the constraint conditions, the left side of the rectangle 57 and the left side of the rectangle 58, the lower side of the rectangle 57 and the lower side of the rectangle 58 are made to match each other, and the upper side of the electrode 55, the upper side of the rectangle 58, and the electrode 5
5 and the right side of the rectangle 57. Others are based on given design rules.

When such a layout pattern is actually arranged, various modifications are necessary due to the relationship with the surroundings.
By keeping the area of the area constant and moving the upper and lower sides, appropriate deformation can be performed.

For example, assume that the generated layout pattern of FIG. 9 is arranged in relation to the periphery as shown in FIG. FIG. 59, FIG. 60, FIG. 61, and FIG. 62 are figures which become obstacles when the layout pattern of FIG. 9 is deformed. FIG. 10B shows the layout pattern of FIG. 9 first moved to the lower left, and then the upper side is moved upward. During this movement, the upper side of the electrode 55
And stop at a position separated by the design rule (minimum separation distance). Then, the right side position of the electrode 55 is recalculated so that the area of the electrode 55 becomes constant. The result is shown in FIG.
This is the layout pattern shown in FIG.

Similarly, FIG. 11C shows the layout pattern shown in FIG. 9 first moved to the upper left, and then the lower side is moved downward. FIG. 11D shows FIG.
This is the result of moving the figure 59 downward in (b).
The layout pattern of FIG. 9 is pushed down by the partial compactor, and the electrode 55
Has been recalculated.

[0050]

As described above, according to the present invention,
It is possible to move the side of a given layout pattern without causing a design standard violation, thereby making it possible to easily and efficiently generate a semiconductor device pattern.

[Brief description of the drawings]

FIG. 1 is a diagram showing a hardware configuration of a semiconductor device pattern generation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a software configuration of a partial compactor which is a characteristic portion of the semiconductor device pattern generation device according to the embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure of an operation of the partial compactor of FIG. 1;

FIG. 4 is a diagram for explaining the operation of the partial compactor of FIG.

FIG. 5 is a diagram for explaining an operation of the partial compactor of FIG. 1;

FIG. 6 is a diagram for explaining the operation of the partial compactor of FIG.

FIG. 7 is a diagram for explaining an operation of the partial compactor of FIG. 1;

FIG. 8 is a diagram for explaining the operation of the partial compactor of FIG. 1;

FIG. 9 is a diagram for explaining the operation of the partial compactor of FIG. 1;

FIG. 10 is a diagram for explaining the operation of the partial compactor of FIG. 1;

FIG. 11 is a diagram for explaining the operation of the partial compactor of FIG. 1;

FIG. 12 is a diagram for explaining a conventional semiconductor device pattern generation method.

FIG. 13 is a diagram for explaining a problem of a conventional semiconductor device pattern generation method.

FIG. 14 is a diagram for explaining a problem of a conventional semiconductor device pattern generation method.

FIG. 15 is a diagram illustrating a problem of a conventional semiconductor device pattern generation method.

FIG. 16 is a diagram for explaining a problem of a conventional semiconductor device pattern generation method.

FIG. 17 is a diagram for explaining a problem of a conventional semiconductor device pattern generation method.

[Explanation of symbols]

1, 5 Contact layout pattern 2, 6, 7 Contact hole 3, 8, 11, 56 Diffusion layer 4, 9 Stretch line 10 Parameterized cell 12, 13, 54, 55 Electrode 14, 15, 16, 17, 31, 33, 34, 37, 4
0, 41, 42, 43, 44, 45, 46, 47, 4
8, 51, 57, 58, 59, 60, 61, 62 FIG. 18 Reference position 19 Layout editor 20 Partial compactor 21 Workstation 22 External storage device 23 Display device 24 Keyboard 25 Mouse 26 Interpretation unit 27 Search unit 28 Execution unit 29 Control Unit 30 Interface unit 32, 35, 38, 49, 50, 52, 53 Side 36, 39 Search area

Claims (3)

[Claims] At least one side constituting a layout pattern is designated for a given layout pattern, and when the designated side is moved by a movement request amount, the designated side and a design standard are moved. Search for the offending side, select the smallest one of the specified sides and the movable amount until the specified standard is violated, and specify only the selected minimum movable amount. A method for generating a semiconductor device pattern, comprising moving a side. 2. A first step of designating at least one side constituting the layout pattern for a given layout pattern, and a step of moving the designated side to the designated side simultaneously with the designated side. A second step of adding, and when all of the specified side and the added side are movable, if the specified side and the added side are moved by the movement request amount, A third step of searching for a side and a side that violates the design standard; and a fourth step of selecting the smallest one of the searched side and a movable amount until the specified side violates the design standard. And the fifth step of moving the specified side by the selected minimum movable amount and subtracting the minimum movable amount from the required movement amount, and if the required moving amount remains, the fifth side The above A sixth step of adding to the specified side the side that is the target of the minimum movable amount obtained in step 5 and the side that must move at the same time as that side, and the required movement amount is eliminated. A method for generating a semiconductor device pattern, comprising repeating steps 3, 4, 5, and 6 until the above. 3. An interpreter for decomposing a command input from the outside into a command for moving a side of a graphic to be processed, and receiving a move command from the interpreter, moving a designated side by a requested movement amount. In this case, a search unit that seeks the specified side and a side that violates the design standard; and, based on the search result of the search unit, can move the specified side until the specified side becomes a searched side and violates the design standard. An execution unit that selects the smallest one of the amounts and moves the specified side by the selected minimum movable amount; and a control unit that controls operations of the interpretation unit, the search unit, and the execution unit. A semiconductor device pattern generation apparatus, comprising: an interface unit that connects an external unit to the interpretation unit, the search unit, the execution unit, and the control unit.