CN112928160B - Forming method of transistor device layout - Google Patents
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- CN112928160B CN112928160B CN202110093839.4A CN202110093839A CN112928160B CN 112928160 B CN112928160 B CN 112928160B CN 202110093839 A CN202110093839 A CN 202110093839A CN 112928160 B CN112928160 B CN 112928160B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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Abstract
The invention provides a method for forming a transistor device layout, which increases the distance between a first floating gate sub-pattern and an active region pattern by reducing the length of the first floating gate sub-pattern in a first direction, so that the distance between a floating gate formed by using the floating gate layout and the active region formed by using the active region layout can be increased in the manufacturing process of the transistor device, thereby avoiding shadow areas, reducing electric leakage and reducing the power consumption of the transistor device; and checking the design rule of the reduced first floating gate sub-pattern to determine whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule, if not, performing extension processing on the first floating gate sub-pattern in the first direction along the direction far away from the active region pattern to increase the length of the first floating gate sub-pattern in the first direction, so that the size of the floating gate in the manufacturing process corresponding to the floating gate pattern can be prevented from being too small.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor device layout.
Background
Referring to fig. 1, a schematic diagram of a prior art transistor device is shown. As shown in fig. 1, the conventional transistor device includes: a substrate 10, an active region 11 located within the substrate 10, and a floating gate 12 located on the active region 11, the floating gate 12 comprising a first portion 13 and a second portion 14, the first portion 13 of the floating gate 12 being perpendicular to the second portion 14 and the first portion 13 of the floating gate 12 being parallel to the active region 11, the second portion 14 of the floating gate 12 covering a portion of the active region 11, but there is a shadow region 15 in the active region 11, the shadow region 15 causing leakage and enabling a larger power consumption of the transistor device. Therefore, a new method for forming a transistor device layout is needed to adjust the structure of the transistor device, so as to solve the problems of shadow areas and larger power consumption in the existing transistor device.
Disclosure of Invention
The invention aims to provide a method for forming a transistor device layout, which aims to solve the problems of shadow areas and larger power consumption in the existing transistor device.
In order to solve the technical problems, the invention provides a method for forming a transistor device layout, which comprises the following steps:
acquiring an original layout of a transistor device, wherein the original layout comprises an active region layout and a floating gate layout, the active region layout comprises at least one active region graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises first floating gate sub-graphs, and the first floating gate sub-graphs and the active region graph are arranged at intervals along a first direction and are arranged in parallel;
reducing the length of the first floating gate sub-pattern in the first direction so as to increase the distance between the first floating gate sub-pattern and the active region pattern;
and checking the design rule of the reduced first floating gate sub-pattern to determine whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule, and if not, performing extension processing on the first floating gate sub-pattern in the first direction along the direction far away from the active region pattern so as to increase the length of the first floating gate sub-pattern in the first direction.
Optionally, in the method for forming a transistor device layout, the method for reducing the length of the first floating gate sub-pattern in the first direction includes:
screening all floating gate patterns in the floating gate layout through layout logic operation;
screening out the first floating gate sub-patterns in all the floating gate patterns through layout logic operation;
and reducing the lengths of all the first floating gate sub-patterns in the first direction, wherein the reduced lengths of all the first floating gate sub-patterns in the first direction are the same in size.
Optionally, in the method for forming a transistor device layout, the length of the first floating gate sub-pattern in the first direction is reduced by 20nm to 30nm.
Optionally, in the method for forming a transistor device layout, after the original layout of the transistor device is obtained, before the length of the first floating gate sub-pattern in the first direction is reduced, the method for forming a transistor device layout further includes:
obtaining a design rule of the original layout, wherein the design rule of the original layout comprises a minimum size design rule of the first floating gate sub-graph, and the minimum size design rule of the first floating gate sub-graph comprises: a minimum length of the first floating gate sub-pattern in the first direction and a minimum length of the first floating gate sub-pattern in the second direction; the method comprises the steps of,
and reducing the minimum length of the first floating gate sub-pattern in the first direction in the minimum size design rule of the first floating gate sub-pattern to obtain a design threshold value.
Optionally, in the method for forming a transistor device layout, the method for checking the design rule of the reduced first floating gate sub-pattern includes:
comparing the length of the reduced first floating gate sub-pattern in the first direction with the size of the design threshold value; and determining whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule according to the comparison result.
Optionally, in the method for forming a transistor device layout, the method for determining whether the length of the reduced first floating gate sub-pattern in the first direction meets a design rule includes:
if the length of the reduced first floating gate sub-pattern in the first direction is equal to or greater than the design threshold value, determining that the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule;
if the length of the first floating gate sub-pattern in the first direction after shrinking is smaller than the design threshold value, judging that the length of the first floating gate sub-pattern in the first direction does not accord with the design rule; and when the length of the first floating gate sub-pattern in the first direction is determined not to accord with the design rule, performing extension processing on the modified first floating gate sub-pattern in the first direction.
Optionally, in the method for forming a transistor device layout, the method for performing extension processing on the first floating gate sub-pattern in the first direction includes:
and extending the first floating gate sub-pattern along the first direction in a direction away from the active region pattern so as to increase the length of the first floating gate sub-pattern in the first direction to the design threshold.
Optionally, in the method for forming a transistor device layout, the floating gate pattern is L-shaped.
Optionally, in the method for forming a transistor device layout, one active region pattern corresponds to one floating gate pattern, the floating gate pattern further includes a second floating gate sub-pattern, the second floating gate sub-pattern overlaps and is connected with a portion of the first floating gate sub-pattern into a whole, and the second floating gate sub-pattern covers a portion of the active region pattern.
Optionally, in the method for forming a transistor device layout, the active region pattern and the first floating gate sub-pattern extend along a second direction, the second floating gate sub-pattern extends along the first direction, and the first direction is perpendicular to the second direction.
In the method for forming the transistor device layout, the original layout of the transistor device is obtained firstly, wherein the original layout comprises an active region layout and a floating gate layout, the active region layout comprises at least one active region graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises a first floating gate sub graph, the first floating gate sub graph and the active region graph are arranged at intervals along a first direction and in parallel, and then the length of the first floating gate sub graph in the first direction is reduced so as to increase the distance between the first floating gate sub graph and the active region graph; therefore, in the manufacturing process of the transistor device corresponding to the transistor device layout, the distance between the floating gate and the active region can be increased, and the distance between the floating gate and the conducting channel (between the gate and the active region) can be increased, so that in the manufacturing process of the transistor device, the distance between the floating gate formed by adopting the floating gate layout and the active region formed by adopting the active region layout can be increased, shadow regions can be avoided, electric leakage can be reduced, and the power consumption of the transistor device can be reduced. And then, checking the design rule of the reduced first floating gate sub-pattern to determine whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule, if not, performing extension processing on the first floating gate sub-pattern in the first direction along the direction far away from the active region pattern to increase the length of the first floating gate sub-pattern in the first direction, so that the size of a floating gate in the manufacturing process corresponding to the floating gate pattern can be prevented from being too small in the manufacturing process of the transistor device, and the floating gate is prevented from being broken. Further, by obtaining the original layout of the transistor device and reducing the length of the first floating gate sub-pattern in the first direction according to the original layout, the distance between the first floating gate sub-pattern and the active region pattern is increased, so that the original layout of the transistor device can be prevented from being modified greatly, and the time for forming the layout of the transistor device can be saved.
Drawings
Fig. 1 is a schematic diagram of a prior art transistor device;
FIG. 2 is a schematic flow chart of a method for forming a transistor device layout according to an embodiment of the present invention;
fig. 3 to 5 are schematic structural diagrams formed in a method for forming a transistor device layout according to an embodiment of the present invention;
wherein reference numerals are as follows:
10-a substrate; 11-an active region; 12-floating gate; 13-a first portion of the floating gate; a second portion of the 14-floating gate;
100-original layout; 110-active area pattern; 120-floating gate pattern; 121-a first floating gate sub-pattern; 122-a second floating gate sub-pattern.
Detailed Description
The method for forming the transistor device layout provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The inventors have found that the reason for the existence of a shadow region in the active region of the existing transistor device is that in the manufacturing method of the transistor device, ion implantation is generally performed on the active region of the transistor device to form a source region and a drain region, and if the distance between the first portion of the floating gate and the active region is relatively close, the first portion of the floating gate blocks ions in the ion implantation, thereby causing the shadow region to be formed in the active region, and the distance between the first portion of the floating gate and the active region depends on the layout of the transistor device. Based on the above, the invention provides a method for forming a transistor device layout, which aims to solve the problems of shadow areas and larger power consumption in the existing transistor device.
Fig. 2 is a schematic flow chart of a method for forming a transistor device layout according to the present invention. As shown in fig. 2, the present invention provides a method for forming a transistor device layout, including:
step S1: acquiring an original layout of a transistor device, wherein the original layout comprises an active region layout and a floating gate layout, the active region layout comprises at least one active region graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises first floating gate sub-graphs, and the first floating gate sub-graphs and the active region graph are arranged at intervals along a first direction and are arranged in parallel;
step S2: reducing the length of the first floating gate sub-pattern in the first direction so as to increase the distance between the first floating gate sub-pattern and the active region pattern;
step S3: and checking the design rule of the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction accords with the design rule, and if not, performing extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction.
Next, the above steps will be described in more detail with reference to 3 to 5; fig. 3 to 5 are schematic structural diagrams formed in the method for forming a transistor device layout according to the present invention.
First, step S1 is performed, referring to fig. 3, an original layout 100 of a transistor device is obtained, where the original layout 100 includes an active area layout and a floating gate layout, the active area layout includes at least one active area pattern 110, the floating gate layout includes at least one floating gate pattern 120, and the floating gate pattern 120 includes a first floating gate sub-pattern 121, and the first floating gate sub-pattern 121 and the active area pattern 110 are arranged at intervals along a first direction Y and are arranged in parallel. Wherein one of the active region patterns 110 corresponds to one of the floating gate patterns 120.
The floating gate pattern 120 has an L-shape (inverted), the floating gate pattern 120 further includes a second floating gate sub-pattern 122, the second floating gate sub-pattern 122 covers a portion of the active region pattern 110, and the second floating gate sub-pattern 122 overlaps and is integrally connected with a portion of the first floating gate sub-pattern 121. The second floating gate sub-pattern 122 extends along the first direction Y, and the first floating gate sub-pattern 121 and the active region pattern 110 both extend along a second direction X, where the first direction Y is perpendicular to the second direction X.
Further, when the number of the active region patterns 110 in the active region layout is two or more, the active region patterns 110 are sequentially arranged at intervals along the first direction Y. When the number of the floating gate patterns 120 in the floating gate layout is two or more, the floating gate patterns 120 are sequentially arranged at intervals along the first direction Y. Further, the floating gate pattern 120 is partially the same size as the floating gate pattern in the floating gate layout.
Next, step S2 is performed, referring to fig. 4, to reduce the length a of the first floating gate sub-pattern 121 in the first direction Y, so as to increase the distance b between the first floating gate sub-pattern 121 and the active region pattern 110.
Specifically, the method for reducing the length a of the first floating gate sub-pattern 121 in the first direction Y includes: firstly, screening all floating gate patterns 120 in the floating gate layout through layout logic operation; then, screening out the first floating gate sub-patterns 121 in all the floating gate patterns 120 through layout logic operation; next, the lengths a of all the first floating gate sub-patterns 121 in the first direction Y are reduced, wherein the reduced lengths of all the first floating gate sub-patterns 121 in the first direction Y are the same in size. Since the distance b between the first floating gate sub-pattern 121 and the active region pattern 110 is increased, the distance between the floating gate and the channel can be increased, so that a shadow region can be prevented from occurring in the manufacturing process of the transistor device, leakage current can be reduced, and power consumption of the transistor device can be reduced.
Further, when the lengths a of all the first floating gate sub-patterns 121 in the first direction Y are reduced, the first floating gate sub-patterns 121 are shortened in a direction away from the active region patterns 110 to reduce the lengths a of the first floating gate sub-patterns 121 in the first direction Y. Further, the first floating gate sub-pattern 121 has a reduced length in the first direction Y of 20nm to 30nm.
Next, a design rule of the original layout is obtained, wherein the design rule of the original layout includes a minimum size design rule of the first floating gate sub-graph 121, and the minimum size design rule of the first floating gate sub-graph 121 includes: a minimum length of the first floating gate sub-pattern 121 in the first direction Y and a minimum length of the first floating gate sub-pattern 121 in the second direction X; and reducing the minimum length of the first floating gate sub-pattern 121 in the first direction Y in the minimum size design rule of the first floating gate sub-pattern 121 to obtain a design threshold, wherein the minimum length of the first floating gate sub-pattern 121 in the first direction Y in the minimum size design rule of the first floating gate sub-pattern 121 can be reduced according to the manufacturing process conditions (such as the overlay accuracy of the manufacturing process) corresponding to the floating gate layout, so as to modify the minimum size design rule of the first floating gate sub-pattern 121, i.e. redefine the minimum size design rule of the first floating gate sub-pattern 121. It should be understood that the design threshold is a size that needs to be satisfied by the length of the first floating gate sub-pattern 121 in the first direction Y, so as to ensure the performance of the transistor device, be easy to implement in the process, and achieve a higher yield.
Next, step S3 is executed to perform a Design Rule Check (DRC) on the reduced first floating gate sub-pattern 121 to determine whether the length a 'of the reduced first floating gate sub-pattern 121 in the first direction Y meets the design rule, and if not, performing an extension process on the first floating gate sub-pattern 121 in the first direction Y in a direction away from the active region pattern 110 to increase the length a' of the first floating gate sub-pattern 121 in the first direction Y.
The method for checking the design rule of the reduced first floating gate sub-pattern 121 includes: comparing the length a' of the reduced first floating gate sub-pattern 121 in the first direction Y with the size of the design threshold; and determining whether the length a' of the reduced first floating gate sub-pattern 121 in the first direction Y accords with a design rule according to the comparison result. The purpose of performing design rule inspection on the reduced first floating gate sub-pattern 121 is to ensure that the design of the transistor device layout is reliable in process and can be smoothly produced.
Further, if the length a 'of the reduced first floating gate sub-pattern 121 in the first direction Y is equal to or greater than the design threshold, determining that the length a' of the reduced first floating gate sub-pattern 121 in the first direction Y meets the design rule; if the length a 'of the first floating gate sub-pattern 121 in the first direction Y after shrinking is smaller than the design threshold, determining that the length a' of the first floating gate sub-pattern 121 in the first direction Y does not conform to the design rule; and performing extension processing on the reduced first floating gate sub-pattern 121 when it is determined that the length a' of the first floating gate sub-pattern 121 in the first direction Y does not conform to the design rule.
Further, the method for performing the extension process on the first floating gate sub-pattern 121 in the first direction Y includes: referring to fig. 5, first, the first floating gate sub-pattern 121 is extended in the first direction Y in a direction away from the active region pattern 110 such that a length a' of the first floating gate sub-pattern 121 in the first direction Y increases to the design threshold, i.e., a length a″ of the extended first floating gate sub-pattern 121 in the first direction Y is equal to the design threshold. In this way, the length of the first floating gate sub-pattern 121 in the first direction Y may be increased, and thus, in the manufacturing process of the transistor device, the size of the floating gate in the manufacturing process corresponding to the floating gate pattern 120 may be prevented from being too small, thereby preventing the floating gate from being broken, for example, preventing the corner of the floating gate (the location of the floating gate corresponding to the interface between the first floating gate sub-pattern 121 and the second floating gate sub-pattern 122) from being broken, and preventing the contact hole formed later from breaking through the floating gate.
In addition, the steps can be realized through an automatic program or software as a standardized step, so that labor can be saved, and further, the original layout of the transistor device can be saved by acquiring the original layout of the transistor device and reducing the length of the first floating gate sub-graph in the first direction according to the original layout so as to increase the distance between the first floating gate sub-graph and the active region graph, so that the original layout of the transistor device can be prevented from being greatly modified, and the time for forming the layout of the transistor device is saved. Furthermore, the floating gate layout is modified on the basis of the original layout, so that the layout does not need to be redesigned, and the overall area of the transistor device layout can be prevented from being increased.
In summary, according to the method for forming the transistor device layout provided by the invention, an original layout of a transistor device is obtained, the original layout comprises an active region layout and a floating gate layout, the active region layout comprises at least one active region graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises first floating gate sub-graphs, the first floating gate sub-graphs and the active region graph are arranged at intervals along a first direction and are arranged in parallel, and then the length of the first floating gate sub-graph in the first direction is reduced so as to increase the distance between the first floating gate sub-graph and the active region graph; therefore, in the manufacturing process of the transistor device corresponding to the transistor device layout, the distance between the floating gate and the active region can be increased, and the distance between the floating gate and the conducting channel (between the gate and the active region) can be increased, so that in the manufacturing process of the transistor device, the distance between the floating gate formed by adopting the floating gate layout and the active region formed by adopting the active region layout can be increased, shadow regions can be avoided, electric leakage can be reduced, and the power consumption of the transistor device can be reduced. And then, checking the design rule of the reduced first floating gate sub-pattern to determine whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule, if not, performing extension processing on the first floating gate sub-pattern in the first direction along the direction far away from the active region pattern to increase the length of the first floating gate sub-pattern in the first direction, so that the size of a floating gate in the manufacturing process corresponding to the floating gate pattern can be prevented from being too small in the manufacturing process of the transistor device, and the floating gate is prevented from being broken.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. The method for forming the transistor device layout is characterized by comprising the following steps of:
acquiring an original layout of a transistor device, wherein the original layout comprises an active region layout and a floating gate layout, the active region layout comprises at least one active region graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises first floating gate sub-graphs, and the first floating gate sub-graphs and the active region graph are arranged at intervals along a first direction and are arranged in parallel;
the method comprises the steps of obtaining a design rule of an original layout, wherein the design rule of the original layout comprises a minimum size design rule of a first floating gate sub-graph, and the minimum size design rule of the first floating gate sub-graph comprises: a minimum length of the first floating gate sub-pattern in the first direction and a minimum length of the first floating gate sub-pattern in the second direction; the method comprises the steps of,
reducing the minimum length of the first floating gate sub-pattern in the first direction in the minimum size design rule of the first floating gate sub-pattern to obtain a design threshold;
reducing the length of the first floating gate sub-pattern in the first direction so as to increase the distance between the first floating gate sub-pattern and the active region pattern;
and checking the design rule of the reduced first floating gate sub-pattern to determine whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule, and if not, performing extension processing on the first floating gate sub-pattern in the first direction along the direction far away from the active region pattern so as to increase the length of the first floating gate sub-pattern in the first direction.
2. The method for forming a transistor device layout according to claim 1, wherein the method for reducing the length of the first floating gate sub-pattern in the first direction comprises:
screening all floating gate patterns in the floating gate layout through layout logic operation;
screening out the first floating gate sub-patterns in all the floating gate patterns through layout logic operation;
and reducing the lengths of all the first floating gate sub-patterns in the first direction, wherein the reduced lengths of all the first floating gate sub-patterns in the first direction are the same in size.
3. The method of forming a transistor device layout according to claim 2, wherein the reduced length of the first floating gate sub-pattern in the first direction is 20nm to 30nm.
4. The method for forming a transistor device layout according to claim 1, wherein the method for checking the design rule of the scaled first floating gate sub-pattern comprises:
comparing the length of the reduced first floating gate sub-pattern in the first direction with the size of the design threshold value; and determining whether the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule according to the comparison result.
5. The method for forming a transistor device layout according to claim 4, wherein the method for determining whether the length of the scaled first floating gate sub-pattern in the first direction meets a design rule comprises:
if the length of the reduced first floating gate sub-pattern in the first direction is equal to or greater than the design threshold value, determining that the length of the reduced first floating gate sub-pattern in the first direction accords with the design rule;
if the length of the first floating gate sub-pattern in the first direction after shrinking is smaller than the design threshold value, judging that the length of the first floating gate sub-pattern in the first direction does not accord with the design rule; and when the length of the first floating gate sub-pattern in the first direction is determined not to accord with the design rule, performing extension processing on the modified first floating gate sub-pattern in the first direction.
6. The method for forming a transistor device layout according to claim 5, wherein the method for performing extension processing in the first direction on the first floating gate sub-pattern comprises:
and extending the first floating gate sub-pattern along the first direction in a direction away from the active region pattern so as to increase the length of the first floating gate sub-pattern in the first direction to the design threshold.
7. The method for forming a transistor device layout according to claim 1, wherein the floating gate pattern has an L-shape.
8. The method of forming a transistor device layout of claim 7, wherein one of said active region patterns corresponds to one of said floating gate patterns, said floating gate pattern further comprising a second floating gate sub-pattern, said second floating gate sub-pattern overlapping and integrally connected with a portion of said first floating gate sub-pattern, and said second floating gate sub-pattern overlaying a portion of said active region pattern.
9. The method of forming a transistor device layout of claim 8, wherein said active region pattern and said first floating gate sub-pattern each extend along a second direction, said second floating gate sub-pattern extending along said first direction, said first direction being perpendicular to said second direction.
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