CN112928160A - Method for forming transistor device layout - Google Patents
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Abstract
The invention provides a method for forming a transistor device layout, which increases the distance between a first floating gate sub-pattern and an active region pattern by reducing the length of the first floating gate sub-pattern in a first direction, so that in the manufacturing process of a transistor device, the distance between a floating gate formed by adopting a floating gate layout and an active region formed by adopting an active region layout can be increased, thereby avoiding a shadow region, further reducing electric leakage and reducing the power consumption of the transistor device; and checking a design rule of the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, performing extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction, so that the floating gate in a manufacturing process corresponding to the floating gate graph can be prevented from being too small in size.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor device layout.
Background
Referring to fig. 1, a schematic diagram of a prior art transistor device is shown. As shown in fig. 1, the conventional transistor device includes: the floating gate structure comprises a substrate 10, an active region 11 located in the substrate 10, and a floating gate 12 located on the active region 11, wherein the floating gate 12 comprises a first portion 13 and a second portion 14, the first portion 13 and the second portion 14 of the floating gate 12 are perpendicular, the first portion 13 of the floating gate 12 is parallel to the active region 11, the second portion 14 of the floating gate 12 covers part of the active region 11, but a shadow region 15 exists in the active region 11, and the shadow region 15 causes current leakage and causes large power consumption of a transistor device. Therefore, it is desirable to provide a new method for forming a transistor device layout to adjust the structure of the transistor device, so as to solve the problems of the existing transistor device, such as the existence of a shadow region and large power consumption.
Disclosure of Invention
The invention aims to provide a method for forming a transistor device layout, which is used for solving the problems of shadow areas and high power consumption in the existing transistor device.
In order to solve the above technical problem, the present invention provides a method for forming a transistor device layout, including:
acquiring an original layout of a transistor device, wherein the original layout comprises an active area layout and a floating gate layout, the active area layout comprises at least one active area pattern, the floating gate layout comprises at least one floating gate pattern, the floating gate pattern comprises a first floating gate sub-pattern, and the first floating gate sub-pattern and the active area pattern are arranged at intervals along a first direction and are arranged in parallel;
reducing the length of the first floating gate sub-pattern in the first direction to increase the distance between the first floating gate sub-pattern and the active region pattern;
and carrying out design rule check on the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, carrying out extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction.
Optionally, in the method for forming the transistor device layout, the method for reducing the length of the first floating gate sub-pattern in the first direction includes:
screening out all floating gate graphs in the floating gate layout through layout logic operation;
screening out the first floating gate sub-graph in all the floating gate graphs through layout logic operation;
and reducing the length of all the first floating gate subpatterns in the first direction, wherein the reduced length of all the first floating gate subpatterns in the first direction is the same.
Optionally, in the method for forming the transistor device layout, the length of the first floating gate sub-pattern in the first direction is reduced by 20nm to 30 nm.
Optionally, in the method for forming a transistor device layout, after obtaining an original layout of the transistor device, before reducing the length of the first floating gate sub-pattern in the first direction, the method for forming a transistor device layout further includes:
obtaining a design rule of the original layout, where the design rule of the original layout includes a minimum size design rule of the first floating gate sub-pattern, and the minimum size design rule of the first floating gate sub-pattern includes: a minimum length of the first floating gate sub-pattern in the first direction and a minimum length of the first floating gate sub-pattern in a second direction; and the number of the first and second groups,
reducing a minimum length of the first floating gate sub-pattern in the first direction in a minimum dimension design rule of the first floating gate sub-pattern to obtain a design threshold.
Optionally, in the method for forming the transistor device layout, the method for checking the design rule of the reduced first floating gate sub-pattern includes:
comparing the length of the shrunk first floating gate sub-graph in the first direction with the size of the design threshold value; and determining whether the length of the first floating gate sub-graph in the first direction after the reduction meets the design rule or not according to the comparison result.
Optionally, in the method for forming the transistor device layout, the method for determining whether the length of the first reduced floating gate sub-pattern in the first direction meets the design rule includes:
if the length of the first floating gate sub-pattern in the first direction after the reduction is equal to or greater than the design threshold, determining that the length of the first floating gate sub-pattern in the first direction after the reduction meets the design rule;
if the length of the first floating gate sub-pattern in the first direction after the reduction is smaller than the design threshold, determining that the length of the first floating gate sub-pattern in the first direction does not accord with the design rule; and when the length of the first floating gate sub-pattern in the first direction is judged to be not in accordance with the design rule, carrying out extension processing on the modified first floating gate sub-pattern in the first direction.
Optionally, in the method for forming the transistor device layout, the method for performing extension processing on the first floating gate sub-pattern in the first direction includes:
and extending the first floating gate sub-pattern in a direction away from the active region pattern along the first direction to increase the length of the first floating gate sub-pattern in the first direction to the design threshold.
Optionally, in the method for forming the transistor device layout, the floating gate pattern is L-shaped.
Optionally, in the method for forming the transistor device layout, one active region pattern corresponds to one floating gate pattern, the floating gate pattern further includes a second floating gate sub-pattern, the second floating gate sub-pattern overlaps and is connected with a portion of the first floating gate sub-pattern, and the second floating gate sub-pattern covers a portion of the active region pattern.
Optionally, in the method for forming the transistor device layout, the active region pattern and the first floating gate sub-pattern both extend along a second direction, the second floating gate sub-pattern extends along the first direction, and the first direction is perpendicular to the second direction.
In the forming method of the transistor device layout, the original layout of the transistor device is obtained firstly, the original layout comprises an active area layout and a floating gate layout, the active area layout comprises at least one active area graph, the floating gate layout comprises at least one floating gate graph, the floating gate graph comprises a first floating gate sub-graph, the first floating gate sub-graph and the active area graph are arranged in parallel at intervals along a first direction, and then the length of the first floating gate sub-graph in the first direction is reduced so as to increase the distance between the first floating gate sub-graph and the active area graph; therefore, in the manufacturing process of the transistor device corresponding to the transistor device layout, the distance between the floating gate and the active region can be increased, and the distance between the floating gate and the conducting channel (located between the gate and the active region) can be increased, so that in the manufacturing process of the transistor device, the distance between the floating gate formed by adopting the floating gate layout and the active region formed by adopting the active region layout can be increased, a shadow region can be avoided, electric leakage can be reduced, and the power consumption of the transistor device can be reduced. And then, carrying out design rule check on the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, carrying out extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction, so that in the manufacturing process of the transistor device, the size of the floating gate in the manufacturing process corresponding to the floating gate graph can be prevented from being too small, and the floating gate is prevented from being broken. Furthermore, the original layout of the transistor device is obtained, and the length of the first floating gate sub-graph in the first direction is reduced according to the original layout so as to increase the distance between the first floating gate sub-graph and the active region graph, so that the original layout of the transistor device can be prevented from being greatly modified, and the time for forming the layout of the transistor device can be saved.
Drawings
FIG. 1 is a schematic diagram of a prior art transistor device;
fig. 2 is a schematic flow chart of a method for forming a transistor device layout according to an embodiment of the present invention;
fig. 3 to 5 are schematic structural diagrams formed in the method for forming a transistor device layout according to the embodiment of the present invention;
wherein the reference numerals are as follows:
10-a substrate; 11-an active region; 12-a floating gate; 13-a first portion of the floating gate; 14-a second portion of the floating gate;
100-original layout; 110-active area pattern; 120-floating gate pattern; 121-a first floating gate subpattern; 122-second floating gate subpattern.
Detailed Description
The following describes the method for forming the layout of the transistor device in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The inventor researches and discovers that the reason why the shadow region exists in the active region of the existing transistor device is that in the manufacturing method of the transistor device, the active region of the transistor device is generally subjected to ion implantation to form a source region and a drain region, if the distance between the first part of the floating gate and the active region is close, the first part of the floating gate blocks ions in the ion implantation, so that the shadow region is formed in the active region, and the distance between the first part of the floating gate and the active region depends on the layout of the transistor device. Based on the above, the invention provides a method for forming a transistor device layout, so as to solve the problems of shadow areas and high power consumption in the existing transistor device.
Please refer to fig. 2, which is a flowchart illustrating a method for forming a layout of a transistor device according to the present invention. As shown in fig. 2, the present invention provides a method for forming a transistor device layout, including:
step S1: acquiring an original layout of a transistor device, wherein the original layout comprises an active area layout and a floating gate layout, the active area layout comprises at least one active area pattern, the floating gate layout comprises at least one floating gate pattern, the floating gate pattern comprises a first floating gate sub-pattern, and the first floating gate sub-pattern and the active area pattern are arranged at intervals along a first direction and are arranged in parallel;
step S2: reducing the length of the first floating gate sub-pattern in the first direction to increase the distance between the first floating gate sub-pattern and the active region pattern;
step S3: and carrying out design rule check on the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, carrying out extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction.
Next, the above steps will be described in more detail with reference to 3 to 5; fig. 3 to 5 are schematic structural diagrams formed in the method for forming a transistor device layout according to the present invention.
Firstly, step S1 is executed, and referring to fig. 3, an original layout 100 of a transistor device is obtained, where the original layout 100 includes an active area layout and a floating gate layout, the active area layout includes at least one active area pattern 110, the floating gate layout includes at least one floating gate pattern 120, the floating gate pattern 120 includes a first floating gate sub-pattern 121, and the first floating gate sub-pattern 121 and the active area pattern 110 are arranged at intervals along a first direction Y and are parallel to each other. Wherein one of the active region patterns 110 corresponds to one of the floating gate patterns 120.
The floating gate pattern 120 is in an L-shape (inverted), the floating gate pattern 120 further includes a second floating gate sub-pattern 122, the second floating gate sub-pattern 122 covers a portion of the active region pattern 110, and the second floating gate sub-pattern 122 overlaps and is integrally connected with a portion of the first floating gate sub-pattern 121. The second floating gate sub-pattern 122 extends along the first direction Y, and both the first floating gate sub-pattern 121 and the active region pattern 110 extend along a second direction X, where the first direction Y is perpendicular to the second direction X.
Further, when the number of the active region patterns 110 in the active region layout is two or more, the active region patterns 110 are sequentially arranged at intervals along the first direction Y. When the number of the floating gate patterns 120 in the floating gate layout is two or more, the floating gate patterns 120 are sequentially arranged at intervals along the first direction Y. Furthermore, the floating gate patterns 120 in the floating gate layout have the same size.
Next, step S2 is executed, referring to fig. 4, to reduce the length a of the first floating gate sub-pattern 121 in the first direction Y, so as to increase the distance b between the first floating gate sub-pattern 121 and the active area pattern 110.
Specifically, the method for reducing the length a of the first floating gate sub-pattern 121 in the first direction Y includes: firstly, screening out all floating gate graphs 120 in the floating gate layout through layout logic operation; then, screening out the first floating gate sub-pattern 121 in all the floating gate patterns 120 through layout logic operation; then, the lengths a of all the first floating gate sub-patterns 121 in the first direction Y are reduced, wherein the lengths of all the first floating gate sub-patterns 121 in the first direction Y are reduced by the same size. Since the distance b between the first floating gate sub-pattern 121 and the active region pattern 110 is increased, the distance between the floating gate and the channel can be increased, thereby preventing a shadow region from occurring in the manufacturing process of the transistor device, reducing leakage current, and reducing power consumption of the transistor device.
Further, when the length a of all the first floating gate sub-patterns 121 in the first direction Y is reduced, the first floating gate sub-patterns 121 are reduced along a direction away from the active region pattern 110, so as to reduce the length a of the first floating gate sub-patterns 121 in the first direction Y. Further, the length of the first floating gate sub-pattern 121 in the first direction Y is reduced to a size of 20nm to 30 nm.
Next, obtaining a design rule of the original layout, where the design rule of the original layout includes a minimum size design rule of the first floating gate sub-pattern 121, and the minimum size design rule of the first floating gate sub-pattern 121 includes: a minimum length of the first floating gate sub-pattern 121 in the first direction Y and a minimum length of the first floating gate sub-pattern 121 in the second direction X; and reducing the minimum length of the first floating gate sub-pattern 121 in the first direction Y in the minimum size design rule of the first floating gate sub-pattern 121 to obtain a design threshold, wherein the minimum length of the first floating gate sub-pattern 121 in the minimum size design rule of the first floating gate sub-pattern 121 in the first direction Y may be reduced according to a manufacturing process condition (e.g., overlay accuracy of a manufacturing process, etc.) corresponding to the floating gate layout, so as to modify the minimum size design rule of the first floating gate sub-pattern 121, that is, redefine the minimum size design rule of the first floating gate sub-pattern 121. It should be understood that the design threshold is a dimension that needs to be satisfied by the length of the first floating gate sub-pattern 121 in the first direction Y to ensure the performance of the transistor device, to be easily realized in the process, and to achieve a high yield.
Next, step S3 is executed to perform a Design Rule Check (DRC) on the scaled first floating gate sub-pattern 121 to determine whether the length a 'of the scaled first floating gate sub-pattern 121 in the first direction Y meets the design rule, and if not, perform an extension process on the first floating gate sub-pattern 121 in the first direction Y along a direction away from the active region pattern 110 to increase the length a' of the first floating gate sub-pattern 121 in the first direction Y.
The method for checking the design rule of the shrunk first floating gate sub-pattern 121 includes: comparing the length a' of the shrunk first floating gate sub-pattern 121 in the first direction Y with the design threshold; and determining whether the length a' of the scaled first floating gate sub-pattern 121 in the first direction Y meets the design rule according to the comparison result. The purpose of checking the design rule of the reduced first floating gate sub-pattern 121 is to ensure that the design of the transistor device layout is reliable and the yield can be successfully achieved.
Further, if the length a 'of the first floating gate sub-pattern 121 in the first direction Y after the reduction is equal to or greater than the design threshold, it is determined that the length a' of the first floating gate sub-pattern 121 in the first direction Y after the reduction meets the design rule; if the length a 'of the first floating gate sub-pattern 121 in the first direction Y after the reduction is smaller than the design threshold, determining that the length a' of the first floating gate sub-pattern 121 in the first direction Y does not meet the design rule; and when the length a' of the first floating gate sub-pattern 121 in the first direction Y is determined not to meet the design rule, performing extension processing on the shrunk first floating gate sub-pattern 121.
Further, the method for performing the extension process on the first floating gate sub-pattern 121 in the first direction Y includes: referring to fig. 5, first, the first floating gate sub-pattern 120 is extended in the first direction Y away from the active region pattern 110, so that the length a' of the first floating gate sub-pattern 121 in the first direction Y is increased to the design threshold, i.e., the length a "of the first floating gate sub-pattern 121 in the first direction Y after the extension process is equal to the design threshold. In this way, the length of the first floating gate sub-pattern 121 in the first direction Y can be increased, so that in the manufacturing process of the transistor device, the floating gate in the manufacturing process corresponding to the floating gate pattern 120 can be prevented from being too small in size, thereby preventing the floating gate from being broken, for example, preventing the corner of the floating gate (the floating gate position corresponding to the boundary between the first floating gate sub-pattern 121 and the second floating gate sub-pattern 122) from being broken, and preventing a contact hole formed subsequently from breaking down the floating gate.
In addition, the steps can be realized through an automatic program or software as a standardization step, so that the labor can be saved, and further, the distance between the first floating gate sub-graph and the active region graph can be increased by obtaining an original layout of the transistor device and reducing the length of the first floating gate sub-graph in the first direction according to the original layout, so that the original layout of the transistor device can be prevented from being greatly modified, and the time for forming the layout of the transistor device can be saved. Furthermore, the floating gate layout is modified on the basis of the original layout, and the layout does not need to be redesigned, so that the increase of the total area of the transistor device layout can be avoided.
In summary, in the method for forming the transistor device layout provided by the invention, the original layout of the transistor device is obtained firstly, the original layout comprises an active area layout and a floating gate layout, the active area layout comprises at least one active area pattern, the floating gate layout comprises at least one floating gate pattern, the floating gate pattern comprises a first floating gate sub-pattern, the first floating gate sub-pattern and the active area pattern are arranged at intervals along a first direction and are arranged in parallel, and then, the length of the first floating gate sub-pattern in the first direction is reduced so as to increase the distance between the first floating gate sub-pattern and the active area pattern; therefore, in the manufacturing process of the transistor device corresponding to the transistor device layout, the distance between the floating gate and the active region can be increased, and the distance between the floating gate and the conducting channel (located between the gate and the active region) can be increased, so that in the manufacturing process of the transistor device, the distance between the floating gate formed by adopting the floating gate layout and the active region formed by adopting the active region layout can be increased, a shadow region can be avoided, electric leakage can be reduced, and the power consumption of the transistor device can be reduced. And then, carrying out design rule check on the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, carrying out extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction, so that in the manufacturing process of the transistor device, the size of the floating gate in the manufacturing process corresponding to the floating gate graph can be prevented from being too small, and the floating gate is prevented from being broken.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for forming a transistor device layout, comprising:
acquiring an original layout of a transistor device, wherein the original layout comprises an active area layout and a floating gate layout, the active area layout comprises at least one active area pattern, the floating gate layout comprises at least one floating gate pattern, the floating gate pattern comprises a first floating gate sub-pattern, and the first floating gate sub-pattern and the active area pattern are arranged at intervals along a first direction and are arranged in parallel;
reducing the length of the first floating gate sub-pattern in the first direction to increase the distance between the first floating gate sub-pattern and the active region pattern;
and carrying out design rule check on the reduced first floating gate sub-graph to determine whether the length of the reduced first floating gate sub-graph in the first direction meets the design rule, if not, carrying out extension processing on the first floating gate sub-graph in the first direction along the direction far away from the active region graph to increase the length of the first floating gate sub-graph in the first direction.
2. The method of forming a transistor device layout of claim 1, wherein the method of reducing the length of said first floating gate sub-pattern in said first direction comprises:
screening out all floating gate graphs in the floating gate layout through layout logic operation;
screening out the first floating gate sub-graph in all the floating gate graphs through layout logic operation;
and reducing the length of all the first floating gate subpatterns in the first direction, wherein the reduced length of all the first floating gate subpatterns in the first direction is the same.
3. The method of forming a transistor device layout of claim 2, wherein a dimension by which a length of the first floating gate sub-pattern in the first direction is reduced is 20nm to 30 nm.
4. The method of forming a transistor device layout of claim 1, wherein after obtaining an original layout of the transistor device, prior to reducing a length of the first floating gate sub-pattern in the first direction, the method of forming the transistor device layout further comprises:
obtaining a design rule of the original layout, where the design rule of the original layout includes a minimum size design rule of the first floating gate sub-pattern, and the minimum size design rule of the first floating gate sub-pattern includes: a minimum length of the first floating gate sub-pattern in the first direction and a minimum length of the first floating gate sub-pattern in a second direction; and the number of the first and second groups,
reducing a minimum length of the first floating gate sub-pattern in the first direction in a minimum dimension design rule of the first floating gate sub-pattern to obtain a design threshold.
5. The method of forming a transistor device layout of claim 4, wherein the method of performing a design rule check on the scaled down first floating gate sub-pattern comprises:
comparing the length of the shrunk first floating gate sub-graph in the first direction with the size of the design threshold value; and determining whether the length of the first floating gate sub-graph in the first direction after the reduction meets the design rule or not according to the comparison result.
6. The method of forming a transistor device layout of claim 5, wherein the method of determining whether the length of the scaled down first floating gate sub-pattern in the first direction meets design rules comprises:
if the length of the first floating gate sub-pattern in the first direction after the reduction is equal to or greater than the design threshold, determining that the length of the first floating gate sub-pattern in the first direction after the reduction meets the design rule;
if the length of the first floating gate sub-pattern in the first direction after the reduction is smaller than the design threshold, determining that the length of the first floating gate sub-pattern in the first direction does not accord with the design rule; and when the length of the first floating gate sub-pattern in the first direction is judged to be not in accordance with the design rule, carrying out extension processing on the modified first floating gate sub-pattern in the first direction.
7. The method of forming a transistor device layout of claim 6, wherein the method of performing extension processing in a first direction on the first floating gate sub-pattern comprises:
and extending the first floating gate sub-pattern in a direction away from the active region pattern along the first direction to increase the length of the first floating gate sub-pattern in the first direction to the design threshold.
8. The method for forming a transistor device layout according to claim 1, wherein the floating gate pattern is L-shaped.
9. The method of forming a transistor device layout of claim 8, wherein one of said active region patterns corresponds to one of said floating gate patterns, said floating gate pattern further comprises a second floating gate sub-pattern, said second floating gate sub-pattern overlaps and is integrally connected to a portion of said first floating gate sub-pattern, and said second floating gate sub-pattern covers a portion of said active region pattern.
10. The method of forming a transistor device layout of claim 9, wherein both the active region pattern and the first floating gate sub-pattern extend along a second direction, the second floating gate sub-pattern extends along the first direction, and the first direction is perpendicular to the second direction.
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