JPH1117518A - Semiconductor integrated circuit incorporating output impedance adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a transmission efficiency for a prescribed time and to suppress power consumption at signal transmission to a required minimum power matching a transmission line by preventing waveform distortion caused by the reflection resulting from mismatching of an output circuit impedance with respect to the transmission line with respect to an impedance change due to a change of a load form or the like so as to increase the signal transmission rate in the case that the semiconductor interface derives the transmission line. SOLUTION: A voltage detection circuit 6 detects an input signal waveform of a dummy load sent from output circuits 1-8 of the semiconductor integrated circuit via a transmission line 3 provided as a dummy, an output impedance of the output circuits 1-8 is controlled by the detection result and optimum drive capability is obtained matching the impedance of the transmission line to be driven. Thus, waveform distortion at signal transmission is prevented, high speed transmission is attained and the power consumption is suppressed to a required minimum value.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a semiconductor integrated circuit for driving a transmission line, and more particularly to a semiconductor integrated circuit having a built-in output impedance adjusting circuit for reducing waveform distortion due to reflection during signal transmission.

[0001]

2. Description of the Related Art When transmitting a signal between a semiconductor integrated circuit and a semiconductor integrated circuit using a transmission line such as a printed wiring board or a cable, the output impedance of the signal drive circuit and the impedance of the transmission line are matched. If not, waveform distortion due to reflection occurs, and a delay time is required more than necessary.

However, the impedance of an output circuit changes due to manufacturing process variations, power supply voltage variations, and temperature variations. Further, the characteristic impedance of the transmission line connected to the output circuit changes depending on the number and form of the load circuits connected to the line, and impedance mismatch easily occurs between the output circuit and the transmission line.

In the prior art disclosed in Japanese Patent Application Laid-Open No. 8-321969, an output voltage of an output section of an output circuit connected to a transmission line is monitored for impedance matching, and a detected voltage and a reference voltage are compared. A comparison is made, and the output impedance is controlled to obtain an optimum output voltage for driving the transmission line based on the result of the comparison.

[0004]

However, the prior art disclosed in Japanese Unexamined Patent Application Publication No. 8-321969 discloses an output initial voltage obtained by a voltage dividing ratio between a transmission line impedance connected to an output circuit and an output circuit impedance. Therefore, normal control cannot be performed unless the impedance of the transmission line connected to the output circuit is uniform to the load at the farthest end. In other words, although this prior art can support a transmission line having an arbitrary impedance, if the impedance of the transmission line differs between the output circuit end side and the load circuit end side, an appropriate output impedance cannot be obtained and waveform distortion occurs. growing.

FIG. 6 shows an example in which the impedance of the transmission line differs between the output circuit end side and the farthest load circuit end viewed from the output circuit.
Shown in The impedance on the farthest load circuit end side of the transmission line is lower than the impedance on the output circuit end side by an amount corresponding to the load connected. Therefore, when the transmission line of FIG. 6 is driven by the output circuit of the related art, the load appears to be light from the output circuit, so that there is a problem that the drive capability of the output circuit is erroneously controlled to be lower.

[0006] Contrary to FIG. 6, when the impedance at the end of the output circuit is low, the load appears heavy from the output circuit, so that there is a problem in that the driving capability of the output circuit is high and erroneous control is performed.

An object of the present invention is to monitor a waveform at a signal receiving end even if the impedance of a transmission line is uneven,
It is an object of the present invention to provide a semiconductor integrated circuit capable of preventing waveform distortion due to reflection at the time of driver signal transmission, controlling signal transmission speed, and improving transmission efficiency in a given time by controlling the driving capability of an output circuit.

[0008]

According to the present invention, when an integrated circuit drives a transmission line, a driver integrated circuit self-monitors a signal initial amplitude in a receiving section and self-corrects the signal to an optimum output impedance value.

In addition to the transmission line used for actual signal transmission, a dummy transmission line having the same form and the same load as the transmission line and having the same impedance is connected to another output terminal of the driver integrated circuit. The other end of the pattern forming the dummy transmission line is folded back and connected to the input terminal of the same driver integrated circuit, and the impedance of the output circuit is determined based on the signal waveform at the input terminal when the output circuit drives the dummy transmission line. It is configured to have a means for adjusting.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in the embodiment of the present invention, an internal circuit 22 of a semiconductor integrated circuit 20 is connected to an output circuit 8, and furthermore, an impedance of a cable or a printed wiring board or the like is output via an output terminal 9. Is connected to the transmission line 10 having The transmission line 10 is connected to receiving circuits, that is, load circuits 11a, 11b, 11c, and 11d (hereinafter, load circuit group 11), and a signal output from the output circuit 8 is transmitted to the load circuit group 11 via the transmission line 10. Is done. In addition to the signal transmission circuit, in the semiconductor integrated circuit 20, an internal circuit 21 is connected to the output circuit 1, and the output circuit 1 has the same impedance and the same impedance as the transmission line 10 via the output terminal 2. It is connected to a dummy transmission line 3 having a load form.

Here, the dummy load circuits 4a, 4b and 4c (hereinafter referred to as load circuit group 4) are not particularly limited as long as they have the same load capacity as the load circuit group 11, and any may be used. However, since the farthest end of the dummy transmission line 3 is connected to the input terminal 5 of the semiconductor integrated circuit 20, the number of the dummy load circuit groups 4 connected to the dummy transmission line 3 is
The number is one less than the number of ones.

In this embodiment, the transmission line 10 and the transmission line 3 have exactly the same impedance when viewed from a semiconductor integrated circuit. That is, the output circuit 1
And 8 have the same driving capability, the load circuit 11a
And the signal waveform reaching the dummy load 4a is exactly the same. Thereafter, similarly, 11b and 4b, 11c and 4c, 11d
And the input terminal 5 transmit the same waveform.

In the present embodiment, in order to optimize the transmission waveform, the waveform at the farthest load should be optimized. Although the distance from the semiconductor integrated circuit 20 to the farthest end load circuit 11d cannot be monitored because it is actually large, the transmission line having the same load as the signal transmission line 10 is folded back and connected to the input terminal 5. The dummy transmission line 3 has means for monitoring the waveform of the input terminal 5 as the farthest end load. Therefore, if the waveform at the input terminal 5 is optimized, the waveform at the load circuit 11d is also optimized.

As shown in FIG. 3, in an output circuit 1, transistors 30 and 31 are connected in multiple stages in an output stage, and the number of transistors driven by an input signal to a control signal input terminal group 36 is controlled to change the output impedance. It has such a configuration. The output circuit 8 has the same configuration as the output circuit 1 and can change the output impedance at the same rate by the same control signal as the output circuit 1. As another configuration example of the output circuit 1, as shown in FIG. 4, a transistor 42 is connected in series with the last-stage transistors 40 and 41, and the number of transistors to be turned on is controlled by an input signal to the control signal input terminal group 36. Alternatively, a circuit configuration in which the output impedance changes may be used. The driving capability of the output circuit 1 is set such that the number of transistors and the driving capability per transistor are adjusted so as to have an adjustment width equal to or larger than the impedance width of various transmission lines whose driving is actually predicted.

As shown in FIG. 5, a voltage detection circuit 6 is connected to the input terminal 5, and a timing signal output from a delay circuit 57 for applying a certain delay to the rise of the signal received at the input terminal 5. The voltage of the input terminal 5 is taken in.

The input voltage detection circuit 6 is further connected to an impedance control signal generation circuit 7.

Here, the input voltage detection circuit 6 and the impedance control signal generation circuit 7 will be described in detail.

The comparators 53 and 54 have different judgment voltages VREF1 and VREF2, respectively. This determination voltage VRE
F1 and VREF2 may be generated inside the semiconductor integrated circuit 20 or may be input from outside. The outputs of the comparators 53 and 54 are provided to flip-flops (hereinafter referred to as F / F) 55 and 56 that operate on the sampling signal output from the delay circuit 57.

The outputs of the F / Fs 55 and 56 are sent to a holding circuit 59 via a counter circuit 58 in the impedance control circuit 7.

Next, how the difference in the driving capability of the output circuit, that is, the output impedance, affects the distortion of the transmission signal waveform will be described with reference to FIGS.

A waveform 100 in FIG. 2 is a transient voltage waveform at the output terminal 2 when the output impedance value of the output circuit 1 is larger than the impedance value of the transmission line 3 to which the circuit 1 is connected. The receiving side waveform of the farthest end load 5 at that time is the waveform 101 in FIG.

In this case, the voltage at the time tL1 when the signal first reaches the farthest end load 5 (hereinafter referred to as the initial amplitude of the farthest load) does not reach the voltages VREF1 and VREF2. It takes time until time tL4 to reach voltages VREF1 and VREF2.

Further, the output impedance is lowered, and the driving capability is increased until the waveform 110 shown in FIG. 2 is obtained. Even in this case, the initial amplitude of the farthest end load is equal to the voltages VREF1 and VREF2.
Has not reached. It takes time until time tL3 to reach the voltages VREF1 and VREF2.

Further, the output impedance is reduced, and the driving capability is increased until the waveform 120 shown in FIG. 2 is obtained. In this case, in the voltage waveform on the receiving side, the voltages VREF1 and VRE1 at time tL1.
The intermediate voltage of F2 has been reached, and the output waveform is the waveform 10 in FIG.
The signal is determined earlier on the receiving side than at 0 and 110.

Further, the output impedance is further reduced,
The received waveform when the driving capability is increased to the waveform 130 in FIG. 2 is the waveform 131 in FIG. Then, the waveform 1 in FIG.
21, the voltages VREF1 and VREF1 at time tL1 on the receiving side.
In spite of reaching REF2, at the time tL2, the voltage conversely drops below the voltage VREF1. Thereafter, the voltage exceeds the voltage VREF1 after time tL3.

That is, the condition under which the signal output from the output circuit 1 can be reliably received by the load circuit 5 is earliest when the output waveform is the waveform 120 in FIG.

Therefore, in order to obtain an optimum transmission waveform at the input terminal, it can be said that the initial amplitude at the input terminal should be an intermediate voltage between VREF1 and VREF2.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4 and 5.

The detection timing of the input voltage detection circuit 6 is the time tLS which is delayed from the time tL1 when the transmission waveform first arrives.
Set to. This delay amount is set to a fixed time by the delay circuit 57 in the voltage detection circuit 6. However, the detection timing tLS must not exceed the time tL2.

First, before the semiconductor integrated circuit 20 connected to the transmission line starts signal transmission, for example, immediately after the power supply of the semiconductor integrated circuit 20 is turned on, the initial state of the output circuit is determined by the output impedance being maximum, that is, the driving capability. Is set to be minimum.

Now, an output impedance adjustment sequence starts.

The internal circuit 21 sends a test pattern signal to the output circuit so that the output terminal 2 outputs a repetition signal of Low level → High level → Low level → High level. The test pattern signal may be generated by dividing the frequency of the clock input from the internal circuit clock terminal 23.

When the output transitions from the low level to the high level, the voltage detector 6 detects the initial amplitude appearing at the input terminal 5 at the sampling timing tLS described above. When the detected initial amplitude voltage is lower than the determination voltages VREF1 and VREF2 as shown by the waveform 100 in FIG. 2, the two F / Fs 55 and 56 in the voltage detection circuit 6 are "0".
And "0" are set. The voltage detection circuit 6 generates a detection signal (F / F 55, 56) indicating that the current driving capability is too low.
Is set to "0", "0") to the control circuit 7. In the control circuit 7, "0",
Upon receiving the "0" signal, an instruction signal generated by the counter circuit to increase the driving capability by one stage is output to the output circuit 1, and the output circuit increases the driving capability by one stage. Thereafter, the detection operation is similarly performed at the next rising edge of the signal.

The drive capability is increased step by step. When the initial amplitude voltage becomes intermediate between the determination voltages VREF1 and VREF2 at the detection timing tLS as shown by the waveform 120 in FIG. F / F55 and 5
6 is set to "1" and "0", respectively. In the control circuit 7, the signals "1" and "0" from the voltage detection circuit are output.
Then, the output impedance is determined to be the optimum value, and the driving capability control operation is stopped. The driving capability adjustment signal at this time is held by a holding circuit 59 such as a flip-flop or a RAM arranged in the control circuit.

At this point, the output circuit has been set to have the optimum driving capability for the transmission line to be connected, and the waveform at the receiving section has no distortion as shown by the waveform 121 in FIG.

This completes the drive capacity adjustment sequence, and the output impedance of the signal output circuit 8 is optimally set by the control signal set in the holding circuit 59, and can be used for actual signal transmission. .

In the above description, the case where the output drivability is adjusted at the rising edge of the signal has been described. However, the adjustment procedure at the falling edge of the signal is the same as the procedure except that the determination level is different.

It should be noted that a procedure may be adopted in which the driving capability in the initial state is maximized and the output impedance is increased by control.

As shown in FIG. 5, as an example of the output circuit, when there are drive capacity adjustment mechanisms on the High side and the Low side of the output stage, it is necessary to adjust the High side and the Low side separately. High side of the step and Lo
By setting the drive capability per one stage on the w side to the same value, it is possible to complete the drive capability adjustment on both the High side and the Low side based on either the rising or falling detection result.

Also, as shown in FIG. 5, as an example of an output circuit, even when a drive adjustment circuit is provided in series with output transistors 40 and 41, adjustment is similarly performed based on either the rising or falling detection result. Can be completed.

[0042]

The first effect of the present invention is that in a semiconductor integrated circuit for driving a transmission line, the transmission line can be changed,
Even if the impedance of the transmission line is not uniform due to the change of the load connected to the transmission line, the output impedance can always be controlled to the optimum without changing the semiconductor integrated circuit. And high-speed signal transmission becomes possible.

The second effect of the present invention is that, by adjusting the output impedance to an optimum value in accordance with the impedance of the transmission line to be connected, it is possible to suppress the transient output current to the minimum necessary, Since a termination circuit is not required in the circuit section, the steady current flowing through the termination circuit,
That is, there can be no steady-state current flowing through the output circuit.

Thus, the power consumption of the output circuit can be minimized in accordance with the transmission line.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of an output circuit unit according to the present invention.

FIG. 4 is a diagram showing another configuration of the output circuit unit according to the present invention.

FIG. 5 is a diagram showing a configuration of an initial voltage detection circuit according to the present invention.

FIG. 6 is a diagram showing a conventional technique.

[Explanation of symbols]

1,8 output circuit 2,9 output terminal 3 dummy transmission line 4a, 4b, 4c dummy load 5 input terminal 6 voltage detection circuit 7 impedance control signal generation circuit 10 signal transmission line 11a, 11b, 11c, 11d load circuit 20 semiconductor integrated Circuits 21 and 22 Internal circuit 23 Internal circuit clock terminal 30 LOW voltage output drive capability adjustment transistor 31 HIGH voltage output drive capability adjustment transistor 32 LOW voltage output transistor 33 HIGH voltage output transistor 34 Output circuit input terminal 35 Output circuit Output terminal 36 Control signal input terminal group 40 LOW voltage output transistor 41 HIGH voltage output transistor 42 Output drive capability adjustment transistor 51, 52 Judgment voltage input terminal 53, 54 Comparator 55, 56 Flip-flop 57 Extension circuit 58 Counter circuit 59 Holding circuit 60 Control signal output terminal 61 Clock terminal for impedance control signal generation circuit 100 Signal rising waveform at output terminal (in the case of small driving ability) 101 Farthest end load circuit input signal rising waveform (Small driving ability) 110) Signal rising waveform at output terminal (when driving capability is small) 111 Signal rising waveform at input terminal of farthest end load circuit (when driving capability is small) 120 Signal rising waveform at output terminal (when driving capability is appropriate) 121 Rise waveform of input signal at far end load circuit (when drive capability is appropriate) 130 Rise waveform at output terminal (when drive capability is large) 131 Rise waveform at input terminal of far end load circuit (when drive capability is large)

Claims (1)

[Claims] An output circuit whose output impedance can be varied by a control signal; an output terminal having one end connected to the output circuit to a dummy transmission line equivalent to an actual load transmission line; An input terminal to which the other end of the line is feedback-connected, a voltage detection path for detecting an initial voltage amplitude of a signal transmitted through the dummy transmission line, and a voltage value detected by the detection circuit, A semiconductor integrated circuit with a built-in output impedance adjustment circuit, comprising: an impedance control signal generation circuit that generates the control signal for controlling the output impedance of the output circuit.