JPH1117167A - Field-effect transistor and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor with a fine gate electrode, in which the gate electrode hardly falls down in a fine manufacturing step, while an increase in resistance of the gate electrode is prevented. SOLUTION: An SiO2 film 2 as an insulating film with thickness of 3 to 10 nm is formed on a semiconductor substrate 3. A gate electrode 5 is formed on the SiO2 film 2. A source region 7s and a drain region 7d are formed on both lower sides of the gate electrode 5. The gate electrode 5 with a rectangular cross section has an oval pole-shaped electrode 6 buried at the center thereof. Since the gate electrode 5 is supported by the oval pole-shaped electrode 6, the gate electrode 5 hardly falls down.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a structure in which a gate electrode is formed finer than the resolution, a resistance of the gate electrode is suppressed, and a defect is prevented from occurring in a manufacturing process. It is about.

[0002]

2. Description of the Related Art In recent years, as the performance of electronic devices such as computers has become higher, semiconductor integrated circuits have been required to have higher integration, higher speed, and lower power consumption. Most of these semiconductor integrated circuits are composed of semiconductor elements called MOS transistors.

Hereinafter, an example of the above-mentioned conventional MOS type semiconductor device will be described with reference to the drawings.

FIGS. 3A to 3D are cross-sectional views showing steps of manufacturing a conventional field-effect transistor.

First, as shown in FIG. 3A, a gate oxide film 1 is formed on a semiconductor substrate 3, and polysilicon as a gate electrode material is deposited to a thickness of about 100 to 300 nm by a CVD method. Next, as shown in FIG. 3B, a resist used in lithography is applied on the gate electrode material, and a resist pattern 4 is formed by lithography.

Next, as shown in FIG. 3C, the gate electrode is processed by anisotropic etching so that the cross section of the gate electrode becomes rectangular or trapezoidal. Finally, as shown in FIG. 3D, the resist mask remaining on the gate electrode is removed.

[0007]

However, the above configuration has the following problems.

In a lithography process for forming a gate electrode, particularly when the gate length is short, the ratio of the resist film thickness to the gate length is large, so that the portion supporting the resist after development is weak, and the possibility of the resist falling down increases. I will. Further, when forming an extremely fine gate, the height of the gate electrode is almost always about 1 or less than or equal to 1 with respect to the gate length, and is limited to the gate length. Therefore, the cross-sectional area of the gate electrode increases, and as a result, the gate resistance increases. A method of increasing the aspect ratio of the gate electrode to avoid the above-described increase in resistance can be considered, but in this case, the gate electrode having a large aspect ratio is difficult to manufacture, and the portion supporting the gate electrode is weak, and the gate The possibility of the electrode falling down increases.

In view of the above problems, the present invention provides a field effect transistor which is formed by thinning the gate length and which suppresses a rise in gate electrode resistance and improves a yield in a process. The purpose is to:

[0010]

Means taken by the present invention to achieve the above object is to have at least one or more columnar projections on the side surface of the gate electrode. Specifically, the first field-effect transistor according to the present invention has a columnar protrusion on the side surface of the gate electrode and supports the gate electrode so as not to fall down in the manufacturing process, as described in claim 1. It has a structure.

According to the present invention, with the above structure, the gate electrode is less likely to fall down by the structure in which the projection provided on the side surface of the gate electrode supports the gate electrode, so that a decrease in transistor yield is suppressed. In addition, since the shape of the projection to support the gate electrode is derived from the resist mask pattern in the lithography process, the structure is included in the lithography mask pattern, so the resist pattern after resist development in the lithography process can collapse And the yield is improved.

Further, the method of manufacturing a field effect transistor according to the present invention includes a step of forming a gate electrode having an inverted mesa structure by isotropic etching. According to this method, a gate electrode having a gate width smaller than the fine line width of the resist mask for the gate electrode obtained in the lithography process can be obtained.

According to the present invention, the resistance of the gate electrode can be prevented from increasing by the above-described structure. Further, by forming a gate electrode thinner than the resolution of lithography, the gate electrode can be thinned.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a field effect transistor according to one embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a perspective view showing the structure of a field effect transistor according to a first embodiment of the present invention. 3n on the surface of the semiconductor substrate and the semiconductor substrate
An SiO2 film serving as an insulating film having a thickness of m to 10 nm is formed, and a gate electrode is formed on the SiO2 film. The semiconductor regions below both sides of the gate electrode are source and drain regions, respectively.

The gate electrode has a rectangular or inverted mesa cross section. The lower part of the gate electrode has a thickness of 0.05 to 0.10 μm as shown in FIG.
m and above the gate electrode is 0.05 to 0.10 μm as shown in FIG. 1b. The upper length of the gate electrode is greater than or equal to the lower length. The gate electrode has a gate length of 0.05 to 0.10 μm, and the height of the gate electrode is 0.1 to 0.3 μm. The gate electrode has a structure in which an elliptical columnar gate electrode is embedded in the center portion of the gate electrode. The gate electrode is supported by the elliptical columnar gate electrode to prevent the gate electrode from falling down. The size of the elliptic gate electrode is 0.10 in the gate length direction.
０．１0.15 μm, and the width in the gate width direction is 0.05〜0.10 μm.

On the surface of the semiconductor substrate 3, 3 nm to 10 nm
An SiO 2 film 2 serving as an insulating film having a thickness of
A gate electrode 5 is formed on the film 2. The semiconductor regions below both sides of the gate electrode 5 are a source 7s and a drain region 7d, respectively.

(Embodiment 2) FIGS. 2A to 2D are cross-sectional views showing steps of manufacturing a field effect transistor according to a second embodiment of the present invention.

First, as shown in FIG. 2A, a gate oxide film 2 made of a silicon oxide film having a thickness of 2 to 10 nm is formed on a semiconductor substrate 3 and a poly oxide film having a thickness of 0.1 to 0.3 μm is formed. A gate electrode material 1 made of a silicon film is deposited.

Next, as shown in FIG. 2B, a resist is formed. At this time, the thickness of the resist mask is 0.4 to
1.0 μm. When a resist pattern is formed, a lithography process is performed, and a mask pattern having at least one protrusion 6 at a gate portion as shown in FIG. 4 is used as a mask pattern used in lithography. . The size of the protrusion is 0.10 μm to 0.15 μm in the direction of the gate length, and 0.05 μm to 0.15 μm in the direction of the gate width.

Next, as shown in FIG. 2C, dry etching is performed to form a gate electrode 5. At this time, an electrode is formed in an inverted mesa structure by using a condition in which an element of isotropic etching is strengthened as a condition of dry etching. At this time, the gate electrode of the inverted mesa structure
5 to 0.10 μm, and 0.03 to 0.05 μm below. Note that a gate electrode having a rectangular cross section can be formed by performing dry etching under anisotropic etching conditions.

Next, as shown in FIG. 2D, the resist is removed. Although the following steps are omitted, the semiconductor device is formed by performing some kind of ion implantation into the source / drain region, forming a metal electrode on the source / drain region, and forming several layers of metal wiring via an interlayer insulating film. Is formed.

In the field-effect transistor manufactured through the above steps, the possibility that the formed gate electrode falls down in the step of forming the gate electrode or any subsequent step is reduced, and the yield can be suppressed. Further, the aspect ratio can be increased and the gate resistance can be reduced. Further, a gate electrode thinner than the resolution of lithography can be obtained.

[0024]

As described above, according to the present invention, the following effects can be obtained.

As a first effect, it is possible to prevent the resist pattern and the gate electrode having a fine gate length from collapsing due to the support of the projection in the fine gate pattern lithography step.

As a second effect, by forming an inverted mesa structure by isotropic etching, an electrode having a gate length smaller than the resolution of lithography can be formed.

As a third effect, by increasing the aspect ratio with respect to the gate electrode having a fine gate length and by adopting an inverted mesa structure, it is possible to suppress an increase in the thin line resistance of the gate electrode.

As a fourth effect, by increasing the aspect ratio with respect to the gate electrode having a fine gate length, it is not necessary to form the deposited film thinly and accurately at the time of depositing the gate electrode.

With the above effects, a field effect transistor having a fine gate length can be formed reliably and easily. If the gate length is shortened and the gate height is increased, the effect of the present invention is increased.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structure of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a process of manufacturing a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a perspective view showing a process of manufacturing a conventional field-effect transistor.

FIG. 4 is a plan view showing a mask pattern for lithography according to the first embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gate electrode material 2 gate oxide film 3 semiconductor substrate 4 resist mask 5 gate electrode 6 protrusion 7 s source region 7 d drain region

Claims (5)

[Claims] A gate insulating film formed on the semiconductor substrate; a gate electrode on the gate insulating film; and a source region and a drain region formed on both sides of the gate electrode. A field effect transistor with a columnar protrusion on the side of the electrode. 2. The field effect transistor according to claim 1, wherein a cross section of the gate electrode has an inverted mesa structure. 3. The field effect transistor according to claim 2, wherein the ratio of the height of the gate electrode to the gate length is large. 4. A step of forming a gate insulating film on a semiconductor substrate, a step of depositing a gate electrode material on the gate insulating film, a step of forming a gate mask having projections, and using the mask. Forming a gate electrode by etching the gate insulating material. 5. The method for manufacturing a field effect transistor according to claim 4, wherein in the step of forming the gate electrode, the gate electrode material is formed into an inverted mesa structure by isotropic etching.