JPH1117033A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the shape stability and reproducibility of characteristics of a nonvolatile semiconductor device at forming of floating gate electrodes. SOLUTION: The manufacturing method comprises implanting impurity ions in a non-single crystal Si layer for floating gate electrodes, oxidizing, removing resultant oxide film, processing this Si layer, forming wells 112 and element isolation regions 111 on a semiconductor substrate, forming a tunneling oxide film 101, forming a polysilicon layer 102 for floating gate electrodes on the oxide film 101, implanting impurity ions in the polysilicon layer 102, and oxidizing this layer 102. The two-step oxidizing reduces the thickness of the oxide film 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nonvolatile semiconductor device having a structure in which a floating gate electrode is provided below a gate electrode.

[0002]

2. Description of the Related Art A conventional method for manufacturing a non-volatile semiconductor device will be described step by step. FIG. 2 is a process cross-sectional view showing a conventional method of manufacturing a nonvolatile semiconductor device in the order of processes. The left-side diagram is a cross-sectional view of a nonvolatile semiconductor device to be formed as viewed from a direction parallel to a gate electrode. It is sectional drawing seen from the direction perpendicular | vertical to an electrode.

FIG. 2A shows a state in which a tunnel oxide film 201 of a nonvolatile semiconductor is formed. This tunnel oxide film is formed by forming a well and an element isolation region by LOCOS oxidation on a semiconductor substrate and then thermally oxidizing the silicon substrate in the same manner as in a process for forming a normal MIS type semiconductor device. .

FIG. 2B shows a polysilicon layer 202 serving as a floating gate electrode on a tunnel oxide film 201 and an oxide film 203 serving as a permeable film for ion implantation in a step of introducing impurities into the polysilicon layer by ion implantation. Is a state in which is formed.

FIG. 2C shows a step of introducing impurities into the polysilicon layer 202 for forming a floating gate electrode by ion implantation. This ion implantation prevents impurities to be introduced from penetrating into the substrate and damaging the tunnel oxide film 201.
The peak of the distribution of the impurity to be introduced is
The implantation conditions are set so as to be near the oxide film 203 in the inside.

FIG. 2D shows a state where a pattern is formed by etching the polysilicon layer 202.
After removing the oxide film 203 by wet etching,
A pattern is formed by a normal photo process, and the polysilicon layer 202 is etched by dry etching.
Etching here facilitates processing in later steps,
In order to prevent stress from occurring due to steps, isotropic etching is used so that the side surface of the pattern is tapered.

FIG. 2E shows a state in which a layer for forming a control gate electrode of the nonvolatile semiconductor device is formed on the floating gate electrode. An oxide film 204 is formed on the patterned polysilicon layer 202 by thermal oxidation, and a polysilicon layer 205 and a WSi (tungsten silicide) layer 206 serving as a gate electrode are formed thereon, and an oxidation serving as a mask for etching the gate electrode. The film 207 is formed.

FIG. 2F shows a state in which a nonvolatile semiconductor device is formed. Polysilicon layer 20
5, after the control gate electrode 209 and the floating gate electrode 108 are formed by etching the WSi layer 206 and the polysilicon layer 202, the source and drain regions 210 are formed by ion implantation, and the interlayer insulating film 213 is formed. The wiring process has been completed.

[0009]

When a non-volatile semiconductor device is to be manufactured with such a configuration, the thickness of the oxide film 203 serving as an ion-implanted transmission film in the ion-implantation step shown in FIG. There is a problem that it is easily affected by variations. Since the peak of the ion implantation is set near the boundary with the oxide film, the effective dose amount of the impurity introduced into the polysilicon layer 202 and the distribution of the impurity are affected by the thickness of the oxide film serving as the transmission film. Depends heavily. For the formation of the permeable membrane, a method such as reduced pressure CVD is usually used.
It is very difficult to accurately control the film thickness in a unit of several nm and with good reproducibility by these methods. A change in the thickness of this oxide film of several nm causes a change in the sheet resistance of the non-single-crystal silicon layer serving as the floating gate by nearly 50%. When the concentration of the impurity in the silicon film greatly fluctuates, the characteristics of the nonvolatile semiconductor device are affected and dry etching of isotropic silicon is sensitive to the concentration of the introduced impurity. The reproducibility of the etching shape in the etching step d) is deteriorated.

There is another problem that the thickness of the floating gate electrode cannot be reduced to a certain extent. When impurities are implanted in polysilicon, the distribution becomes considerably wide. For this reason, if the margin of the thickness of the polysilicon layer 202 is not sufficient, in the ion implantation step shown in (c), some of the impurities implanted in the polysilicon layer 202 penetrate into the tunnel oxide film 201 and the substrate. As a result, the tunnel oxide film 201 is damaged, and the threshold voltage of the MIS semiconductor device to be formed is affected. Even when the oxide film 203 serving as a permeable film of about 20 nm is provided as in this example, the thickness of the polysilicon film is required to be 140 nm or more in order to prevent penetration of the implanted ions. On the other hand, in order to facilitate processing in a later step, particularly in a wiring step, it is desirable that the step of the element is as small as possible. In particular, when miniaturization of an element is to be achieved, it is a serious problem in processing that the thickness of the layer serving as the floating gate electrode cannot be reduced.

[0011]

In order to solve the above-mentioned problems, a method for manufacturing a nonvolatile semiconductor device according to the present invention comprises (1) a step of forming non-single-crystal silicon, and (2)
A step of introducing impurities into the non-single-crystal silicon film by ion implantation, (3) a step of oxidizing the non-single-crystal silicon film, (4) a step of removing the oxide film, and (5) the non-single-crystal silicon film And forming a pattern by etching.

[0012] The film thickness of the non-single-crystal silicon film of (1) is not less than 150 nm and not more than 250 nm.

The impurity introduced in the above (2) is P (phosphorus)
It is characterized by being.

The oxidation of (3) is performed at least at 800 ° C.
It is characterized by including an oxidation step in a nitrogen or argon atmosphere having an oxygen concentration of not more than 900 ° C and an oxygen concentration of not more than 50%, and a wet oxidation step in an atmosphere of not less than 850 ° C and not more than 950 ° C.

The film thickness of the non-single-crystal silicon film after the oxidation of the above (3) is 130 nm or less.

In the etching step (5), CF ₄ ,
It is characterized by isotropic or low-anisotropic etching using O ₂ .

[0017]

According to the method of manufacturing a nonvolatile semiconductor device of the present invention, the stability of the shape during processing of the floating gate electrode can be improved, and the reproducibility of the characteristics of the nonvolatile semiconductor device can be improved. Further, the thickness of the floating gate electrode can be reduced, and it is possible to cope with miniaturization of the element.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a nonvolatile semiconductor device according to the present invention will be described step by step. FIG. 1 is a process cross-sectional view showing a method of manufacturing a nonvolatile semiconductor device according to the present invention in the order of processes. The left-hand drawing is a cross-sectional view of a non-volatile semiconductor device to be formed as viewed from a direction parallel to a gate electrode. FIG. 3 is a cross-sectional view as viewed from a direction perpendicular to a gate electrode.

FIG. 1A shows a well 112 and a device isolation region 111 formed by LOCOS oxidation on a semiconductor substrate as in the prior art, and then a tunnel oxide film 10 of a nonvolatile semiconductor.
1 shows a state where 1 is formed. The tunnel oxide film is formed by dry oxidation at 900 ° C., and has a thickness of 9.5 nm.

FIG. 1B shows a state in which a polysilicon layer 102 serving as a floating gate electrode is formed on the tunnel oxide film 101. This polysilicon layer has a reduced pressure CV
The film is formed at a film forming temperature of 620 ° C. by the method D, and the film thickness is 180 nm. Here, the conditions for forming the polysilicon film are not particularly related to the gist of the present invention, and are set to 550.
An amorphous silicon film formed at a temperature of about ℃ and a microcrystalline silicon film formed at a temperature of about 580 ° C., and a polysilicon film formed at a temperature higher than that can be similarly applied.

FIG. 1C shows a step of introducing impurities into the polysilicon layer 102 for forming a floating gate electrode by ion implantation. Here, P
(Phosphorus) ions at an acceleration voltage of 30 keV and a dose of 2 ×
10 ¹⁵ hits. This ion implantation is desirably performed at a position as shallow as possible in order to avoid the influence on the tunnel oxide film 101, and an acceleration voltage of 30 keV or less,
If possible, it is desirable to use an acceleration voltage of 20 to 10 keV. However, if such an acceleration voltage is used, there is a problem in mass production such as the stability of the apparatus. Therefore, an acceleration voltage of 30 keV is used as a practical condition. When a lower accelerating voltage is used in this step, the thickness of the polysilicon layer 102 formed in the step (b) can be further reduced. In this embodiment, a permeable film for ion implantation is not particularly provided on the polysilicon layer 102 for simplification of the process. However, a process in which a permeable film is provided may be employed. Good results are obtained when the dose of the implanted impurity is in the range of 5 × 10 ¹⁴ to 3 × 10 ¹⁵ . 180n as shown in this embodiment
1 m when the thickness of the polysilicon 102 is
It is desirable to use a dose amount of × 10 ¹⁵ or more.

FIG. 1D shows a state where the polysilicon layer 102 serving as a floating gate is oxidized. Oxidation is performed in a first-stage heat treatment at 800 ° C. for 30 minutes in a nitrogen atmosphere with an oxygen concentration of 5%, and in a second-stage heat treatment at 80 ° C. in a 70% wet atmosphere at 900 ° C. Is continuously going on. By this oxidation, an oxide film of about 180 nm is formed on the polysilicon, and the thickness of the remaining polysilicon layer 102 is about 120 nm. By using such oxidation conditions of the two-stage heat treatment, the reproducibility and uniformity of the thickness of the oxide film 103 formed in this step can be improved. Good results can be obtained by performing the first heat treatment at a temperature of 800 to 900 ° C. for about 10 to 30 minutes. In this embodiment, an atmosphere to which oxygen is added during the first heat treatment is used in order to prevent impurities from diffusing from the polysilicon 102 into the furnace atmosphere. In order to suppress the formation of an oxide film in the initial stage, the first heat treatment is performed in an atmosphere of an inert gas such as nitrogen or argon, and the amount of oxygen to be added should be 50% or less. desirable. In the second heat treatment, wet oxidation treatment is performed to secure an oxidation rate. In order to reduce the influence on the reliability and the like of the tunnel oxide film 101, it is necessary to perform the processing at least at 950 ° C. or less.
Processing at the lowest possible temperature is desirable. On the other hand, 100
In order to perform oxidation at a wavelength of at least 850 nm, a treatment at 850 ° C. or more is practical.
Processing at ℃. By adjusting the thickness of the oxide film 103 in this step, the final thickness of the floating gate electrode can be adjusted. However, if the oxide film 103 is too thick, The reproducibility and uniformity of the thickness of the floating gate electrode are deteriorated. Practically, it is desirable to configure the process so that the thickness of the oxide film 103 is 200 nm or less.

FIG. 1E shows a state in which the polysilicon layer 102 is etched to form a pattern.
After removing the oxide film 103 by wet etching with hydrofluoric acid, a pattern is formed by a normal photo process,
Dry etching is performed. The etching in this step facilitates the processing in a later step, and in order to prevent a stress from being generated in the control gate electrode layer due to the steps of the polysilicon layer 102, the side surface of the pattern is tapered. Isotropic or low anisotropic etching conditions are used. When the surface is oxidized in the step (d) as in the present invention, the distribution is such that the impurity concentration near the surface of the silicon layer 102 increases with good reproducibility. In the case of etching polysilicon, the etching rate is usually higher when the impurity concentration is higher. Therefore, it is effective to combine isotropic or low-anisotropic etching with polysilicon having such an impurity distribution. Can be tapered. In this embodiment, a very good side shape is obtained by performing etching using a Freon (CF ₄ ) in which oxygen (O ₂ ) is added to an etching gas with a down-flow type etching apparatus.

FIG. 1F shows a state in which a layer for forming a control gate electrode of the nonvolatile semiconductor device is formed on the floating gate electrode. An oxide film 104 is formed by thermal oxidation on the patterned polysilicon layer 102, and a polysilicon layer 105 and a WSi (tungsten silicide) layer 106 serving as a gate electrode are formed thereon, and an oxidation serving as a mask for etching the gate electrode. The film 107 is formed.

FIG. 1 (g) shows a state in which a nonvolatile semiconductor device according to the present invention has been formed. After forming the pattern of the control electrode by a normal photo process, the oxide film 107, the WSi layer 106, and the polysilicon layer 105 are etched. In this step, the gate electrodes of the MIS semiconductor devices other than the nonvolatile semiconductor device formed on the same substrate are processed. After covering another MIS type semiconductor device with a resist, the oxide film 104 and the polysilicon layer 102 are etched using the oxide film 107 as a mask to form a floating gate electrode 108. The source / drain regions 110 of the semiconductor device are formed by ion implantation, the interlayer insulating film 113 is formed, and then a wiring process is performed. Thus, a nonvolatile semiconductor device according to the present invention can be formed.

The film thickness of the polysilicon layer 102 to be formed in (b) is set to an acceleration voltage of 30 k for the ion implantation in (c).
In the case of eV, the thickness needs to be 150 nm or more in order to prevent penetration of ions into the channel portion. In consideration of margins such as variations in film thickness, 1
It is desirable to be 70 nm or more. However, it is possible to make the polysilicon layer 102 thinner by lowering the acceleration voltage for ion implantation in (c). When such conditions are used, the oxide film 103 in FIG.
Can be suppressed to a small thickness, and the reproducibility and uniformity of the final film thickness of the floating gate electrode can be improved.

[0027]

According to the method for manufacturing a nonvolatile semiconductor device of the present invention, the stability of the shape at the time of processing the floating gate electrode can be improved, and the reproducibility of the characteristics of the nonvolatile semiconductor device can be improved. . Further, the thickness of the floating gate electrode can be reduced, and it is possible to cope with miniaturization of elements.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a nonvolatile semiconductor device according to an example of the present invention in the order of processes.

FIG. 2 is a process sectional view showing a conventional method for manufacturing a nonvolatile semiconductor device in the order of processes.

[Explanation of symbols]

101, 201: tunnel oxide film 102, 202: polysilicon layer 103: oxide film (film obtained by oxidizing polysilicon) 203: oxide film (of ion implantation) Oxide film 105, 205 ... Polysilicon layer 106, 206 ... WSi (tungsten silicide) layer 107, 207 ... Oxide film (mask layer at the time of gate electrode processing) 108 , 208: floating gate electrode 109, 209: control gate electrode 110, 210: source / drain 111, 211: element isolation region (LOCOS oxide film) 112, 212: P well

Claims (6)

[Claims] In a method of manufacturing a nonvolatile semiconductor device having a structure in which a floating gate electrode is provided below a gate electrode, (1)
Forming a non-single-crystal silicon film, (2) introducing an impurity into the non-single-crystal silicon film by ion implantation, (3) oxidizing the non-single-crystal silicon film,
(4) A method of manufacturing a semiconductor device, comprising: a step of removing the oxide film; and (5) a step of forming a pattern by etching the non-single-crystal silicon film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said non-single-crystal silicon film has a thickness of 150 nm or more and 250 nm or less. 3. The method according to claim 2, wherein the impurity introduced in the step (2) is P (phosphorus).
A method for manufacturing a semiconductor device. 4. The method according to claim 1, wherein the oxidation of (3) is at least 800 ° C.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising: an oxidation step in a nitrogen or argon atmosphere having an oxygen concentration of not more than 900 ° C. and not more than 50%; and a wet oxidation step of not less than 850 ° C. and not more than 950 ° C. Method. 5. The method according to claim 1, wherein the thickness of the non-single-crystal silicon film after the oxidation in the step (3) is 130 nm or less. 6. The method according to claim 5, wherein the etching step (5) is performed by using CF ₄ ,
_{2. The} method for manufacturing a semiconductor device according to claim 1, wherein isotropic or low-anisotropic etching using O ₂ is performed.