JPH1116970A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate electrically the performance of the operating speeds of transistors and the current-voltage characteristics of the first transistor without considering an irregularity in the sizes of the gates of the transistor by a method wherein a first logic level of a voltage is fed to a first pad, an oscillation means is activated and the second transistor is connected with the first pad. SOLUTION: In the case where the performance of the operating speeds of transistors is evaluated, a voltage VDD is made to apply to pads 105 and 106 and a ring oscillator 201 is oscillated. An oscilloscope is connected with a pad 104 and the oscillation waveform of the ring oscillator 201 is observed. In the case where the drain current-drain voltage (ID-VD) characteristics of the P-channel MOS transistor 301 are evaluated, an earth voltage GND is fed to the pads 105 and 106. A supply voltage to a pad 102 is changed and the ID-VD characteristics at the time when the transistor 301 is turned on are measured by the pad 106. Thereby, the performance of the operating speeds of the transistors and the current-voltage characteristics can be evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit for evaluating process performance, and more particularly to a semiconductor integrated circuit for evaluating operation speed performance and transistor characteristics.

[0002]

2. Description of the Related Art As a circuit for evaluating various characteristics of a CMOS type semiconductor integrated circuit, transistor characteristics (current / voltage (I
-V) Characteristics) There is an evaluation circuit and an operation speed performance evaluation circuit.

Here, in the transistor characteristic evaluation circuit, as shown in FIGS. 7 and 8, the voltage supplied to terminals 1 to 8 connected to each node of the transistor and the flowing current are measured to measure the transistor. I-
The V characteristic is evaluated, and the operation speed performance evaluation circuit evaluates the operation speed performance of the transistor by measuring the oscillation frequency of the ring oscillator as shown in FIG.

FIG. 10 is a circuit diagram showing a specific configuration of NAND circuit 9 included in the ring oscillator shown in FIG. 9, and FIG. 11 is a circuit diagram showing inverter 1 shown in FIG.
FIG. 3 is a circuit diagram showing a specific configuration of 0, 11, and 12. FIG.
As shown by 0, when voltage VDD is supplied to power supply node V1, N-channel MOS transistor 90 is turned on, NAND circuit 9 is activated, and the ring oscillator shown in FIG. 9 starts oscillating.

[0005]

FIG. 12 shows a wafer 13
FIG. 13 is a diagram showing a chip 14 formed thereon, and FIG.
FIG. 13 is a block diagram showing a configuration of a chip 14 shown in FIG.

As shown in FIG. 13, the transistor characteristic evaluation circuit group 15 and the speed performance evaluation circuit group 16 are located in the same chip 14 but at different positions.

Therefore, the transistors constituting these circuit groups are affected by manufacturing variations within the same chip in the process.

However, in recent ultra-miniaturized processes, manufacturing variations within the same chip have a large effect on the circuit. For example, a variation of 0.05 μm for a gate size of 1 μm and a variation of 0.5 μm
In this case, the influence of the variation of 0.05 μm on the gate size is different.

Therefore, in order to correctly evaluate the relationship between the operation speed performance of the transistor and the IV characteristics of the transistor, the gate size of the transistor included in the speed performance evaluation circuit group 16 and the transistor performance evaluation circuit group 15 included in the speed performance evaluation circuit group 16 are required. There is a problem that the gate dimensions of the transistors contained therein must be measured by a scanning electron microscope or the like.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem.
It is an object of the present invention to provide a semiconductor integrated circuit capable of electrically evaluating V characteristics without considering variations in gate dimensions.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first pad, a first transistor, and a voltage having a first logic level supplied to the first pad. It comprises an oscillating means to be activated and a second transistor connected to the first pad.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second transistor has a gate connected to the first pad, and a second pad connected to the first pad. Is turned on when a voltage having a logic level of?

[0013] A semiconductor integrated circuit according to a third aspect is the semiconductor integrated circuit according to the second aspect, wherein the second transistor is a P-channel MOS transistor.

A semiconductor integrated circuit according to a fourth aspect is the semiconductor integrated circuit according to the second aspect, wherein the second transistor is an N-channel MOS transistor.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the second transistor has a gate connected to the first pad and a second pad connected to the first pad. And a third transistor of the second conductivity type, the gate of which is connected to the output node of the oscillating means, of the first conductivity type, which is rendered conductive when a voltage having the logic level of is supplied. .

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the second transistor is a P-channel MOS transistor and the third transistor is an N-channel MOS transistor. It is.

A semiconductor integrated circuit according to claim 7 is the semiconductor integrated circuit according to claim 5, wherein the second transistor is an N-channel MOS transistor and the third transistor is a P-channel MOS transistor. It is.

The semiconductor integrated circuit according to claim 8 is the semiconductor integrated circuit according to claim 1, wherein the second pad,
A third transistor having a gate connected to the third pad, the second transistor being connected between the first pad and the second pad, the gate being connected to the third pad; The third transistor is connected to the third pad and has the same conductivity type as the third transistor.

A semiconductor integrated circuit according to a ninth aspect is the semiconductor integrated circuit according to the eighth aspect, wherein the third transistor is a P-channel MOS transistor.

A semiconductor integrated circuit according to a tenth aspect is the semiconductor integrated circuit according to the eighth aspect, wherein the third transistor is an N-channel MOS transistor.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. The same reference numerals in the drawings denote the same or corresponding parts.

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor integrated circuit includes a ring oscillator 201 and a buffer 202. The ring oscillator 201 has an output node N3,
The buffer 202 includes a transistor characteristic evaluation circuit 4 connected to an output node N3 of the ring oscillator 201.
10 and inverters 420 and 430 connected in series to the transistor characteristic evaluation circuit 410.

The semiconductor integrated circuit according to the present embodiment has two input NANs included in ring oscillator 201.
A pad 101 for supplying the voltage V1 to the D circuit 300; and a transistor characteristic evaluation circuit 41 included in the buffer 202.
0, the pad 102 for supplying the voltage V2 to each of the inverters 420 and 430, the two-input NAND circuit 300,
Transistor characteristic evaluation circuit 410 and inverter 42
A pad 103 for supplying the ground voltage GND to each of the inverters 0 and 430, a pad 104 connected to the output node of the inverter 430, and pads 105 and 106 are provided.

Here, each two-input NAND circuit 300 includes:
The input node N1, the output node N2, the P-channel MOS transistors 301 and 302 of the same size connected in parallel between the pad 101 and the node N2, and the same size connected in series between the node N2 and the pad 103. N channel MOS transistors 303 and 304 are included. The gates of P-channel MOS transistor 301 and N-channel MOS transistor 303 are connected to input node N1.
, The P-channel MOS transistor 302 and N
Each gate of the channel MOS transistor 304 is connected to the pad 105.

The transistor characteristic evaluation circuit 410
The output node N4, the gate is connected to the pad 105, the source is connected to the pad 102, and the drain is connected to the pad 106. The P-channel MOS transistor 301 whose characteristics are to be evaluated, and the gate is the ring oscillator 201
, The source is at the pad 106, and the drain is the output node N4 of the transistor characteristic evaluation circuit 410.
P-channel MOS transistors 3 respectively connected to
02, the gate is at the output node N3, and the source is the pad 1
03 includes an N-channel MOS transistor 303 having a drain connected to output node N4.

The operation of the semiconductor integrated circuit will be described below. First, when evaluating the operation speed performance of the transistor, the voltage VDD is applied to the pad 105 and the pad 106. As a result, the N-channel MOS transistor 304 of each of the two-input NAND circuits 300 included in the ring oscillator 201 is turned on and activated, and the ring oscillator 201 oscillates. At this time, by connecting an oscilloscope to the pad 104, the ring oscillator 2
01 oscillation waveform (oscillation frequency) is observed.

Next, when evaluating the drain current / drain voltage (ID-VD) characteristics of the P-channel MOS transistor 301 in the transistor characteristic evaluation circuit 410, the ground voltage GND is supplied to the pads 105 and 106. As a result, the N-channel MOS transistor 304 of each two-input NAND circuit 300 included in the ring oscillator 201 is turned off, so that the ring oscillator 201 is turned off.
Are inactivated, and P-channel MOS transistor 301 is turned on. On the other hand, the ring oscillator 20
1 is turned on, the voltage V1 is applied to the output node N3, and the P-channel MOS transistor 302 in the transistor characteristic evaluation circuit 410 is turned on.
Is turned off. At this time, the voltage V2 supplied to the pad 102 is changed from 0 V to the voltage VDD, and the P-channel MOS
The ID-VD characteristic when the transistor 301 is turned on is measured using the pad 106.

In the semiconductor integrated circuit according to the present embodiment, since the pad 106 used for measuring the transistor characteristics is connected to the buffer 202, the influence of the capacitance of the pad 106 on the operation of the ring oscillator 201 is avoided. can do.

The gate of the P-channel MOS transistor 301 whose transistor characteristics are to be evaluated is connected to each of the two-input NAND circuits 3 included in the ring oscillator 201.
00 and the gates of the P-channel MOS transistor 302 and the N-channel MOS transistor 304, the antenna ratio [P-channel MOS transistor 30
1 gate area / (total of gate areas of P-channel MOS transistor 302 and N-channel MOS transistor 304 of each two-input NAND circuit 300 included in ring oscillator 201 + P-channel MOS transistor 30
1) to reduce the plasma damage to the gate of P-channel MOS transistor 301 from pad 105, thereby avoiding the effect on the drain current characteristics.

[Second Embodiment] FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

As shown in FIG. 2, the semiconductor integrated circuit includes a ring oscillator 203 and a buffer 204. The ring oscillator 203 has an output node N3,
A buffer 204 including a two-input NOR circuit 400 connected in a loop and a transistor characteristic evaluation circuit 51 connected to an output node N3 of the ring oscillator 203.
0 and inverters 420 and 430 connected in series to the transistor characteristic evaluation circuit 510.

The semiconductor integrated circuit according to the present embodiment has a two-input NOR circuit included in ring oscillator 203.
A pad 101 for supplying the voltage V1 to the circuit 400; and a transistor characteristic evaluation circuit 510 included in the buffer 204.
102 for supplying voltage V2 to each of inverters 420 and 430, two-input NOR circuit 400, transistor characteristic evaluation circuit 510, and inverters 420 and 430.
430 that supplies ground voltage GND to each of
03, a pad 104 connected to the output node of the inverter 430, and pads 105 and 107.

Here, each two-input NOR circuit 400 includes an input node N1, an output node N2, and a P channel M of the same size connected in series between pad 101 and node N2.
OS transistors 301 and 302 and N-channel MOS transistors 303 and 304 of the same size connected in parallel between node N2 and pad 103 are included. And
P-channel MOS transistor 301 and N-channel MO
Each gate of S transistor 303 is connected to input node N1, and each gate of P channel MOS transistor 302 and N channel MOS transistor 304 is connected to pad 10
5 is connected.

The transistor characteristic evaluation circuit 510
The output node N4, the gate is connected to the pad 105, the source is connected to the pad 103, and the drain is connected to the pad 107. The N-channel MOS transistor 304 whose characteristics are to be evaluated, and the gate is the ring oscillator 203
, The source is at the pad 107, and the drain is the output node N4 of the transistor characteristic evaluation circuit 510.
N-channel MOS transistors 3 respectively connected to
03, the gate is the output node N3, and the source is the pad 1
02 includes a P-channel MOS transistor 301 having a drain connected to output node N4.

The operation of the semiconductor integrated circuit will be described below. First, when evaluating the operation speed performance of the transistor, the ground voltage GND is applied to the pads 105 and 107.
Is applied. As a result, the P-channel MOS transistor 302 of each of the two-input NOR circuits 400 included in the ring oscillator 203 is turned on and activated, and the ring oscillator 203 oscillates. At this time, by connecting an oscilloscope to the pad 104, the oscillation waveform (oscillation frequency) of the ring oscillator 203 is observed.

Next, when evaluating the ID-VDD characteristic of the N-channel MOS transistor 304 in the transistor characteristic evaluation circuit 510, the voltage VDD is applied to the pad 105. As a result, the P-channel MOS transistor 302 of each two-input NOR circuit 400 included in the ring oscillator 203 is turned off, so that the ring oscillator 203 is inactivated and the N-channel MOS transistor 304 is turned on. On the other hand, the ring oscillator 203
N-channel MO of each two-input NOR circuit 400 included in
When S transistor 304 is turned on, ground voltage GND is supplied to output node N3, and N-channel MOS transistor 3 in transistor characteristic evaluation circuit 510 is turned on.
03 is turned off. At this time, the voltage supplied to the pad 107 is changed from 0 V to the voltage VDD so that the N-channel MOS
The ID-VD characteristic when the transistor 304 is turned on is measured using the pad 107.

Note that also in the semiconductor integrated circuit according to the present embodiment, since the pad 107 used for measuring the transistor characteristics is connected to the buffer 204, the influence of the capacitance of the pad 107 on the operation of the ring oscillator 203 is avoided. can do.

The gate of the N-channel MOS transistor 304 whose transistor characteristics are to be evaluated is connected to each two-input NOR circuit 40 included in the ring oscillator 203.
0 is connected to the gates of the P-channel MOS transistor 302 and the N-channel MOS transistor 304, the antenna ratio is reduced, and the gate damage of the N-channel MOS transistor 304 is reduced by reducing the plasma damage received from the pad 105. The effect is avoided.

[Third Embodiment] FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

As shown in FIG. 3, this semiconductor integrated circuit has the same configuration as the semiconductor integrated circuit according to the first embodiment shown in FIG. In that the transistor characteristic evaluation circuit 610 having the above configuration and the pads 107 and 108 are provided.

Here, the transistor characteristic evaluation circuit 610
The gates of P-channel MOS transistor 301 and N-channel MOS transistor 303 are connected to output node N3, and P-channel MOS transistor 30
2 and each gate of N-channel MOS transistor 304 are connected to pad 105.

A pad 108 is connected to the output node N4.
Pad 107 is connected to the drain of N-channel MOS transistor 304 and the source of N-channel MOS transistor 303, respectively.

With the above configuration, the P-channel MOS transistor 302 and the N-channel MOS transistor 303 are subjected to transistor characteristic evaluation.

The operation of the semiconductor integrated circuit according to the present embodiment will be described below. First, when evaluating the operation speed performance of the transistor, the voltage VDD is applied to the pad 105,
The ground voltage GND is supplied to the pad 107, and the pad 108 is brought into a floating state. As a result, the N-channel MOS transistor 304 of each of the two-input NAND circuits 300 included in the ring oscillator 201 is turned on and activated, and the ring oscillator 201 oscillates. At this time, by connecting an oscilloscope to the pad 104, the oscillation waveform (oscillation frequency) of the ring oscillator 201 is observed.

Next, when evaluating the ID-VD characteristics of the P-channel MOS transistor 302 in the transistor characteristic evaluation circuit 610, the ground voltage GND is supplied to the pads 105 and 108.

Thus, the N-channel MOS of each 2-input NAND circuit 300 included in ring oscillator 201
Since the transistor 304 is turned off, the ring oscillator 2
01 is inactivated, the P-channel MOS transistor 302 is turned on, and the P-channel MOS transistor 301 is turned off. At this time, since the N-channel MOS transistor 303 is turned on, the ground voltage GND is supplied to the pad 107 and the voltage V2 supplied to the pad 102 is supplied.
Is changed from 0 V to the voltage VDD, and the ID-VDD characteristic when the P-channel MOS transistor 302 is turned on is measured using the pad 108.

On the other hand, the source current of N-channel MOS transistor 303 in transistor characteristic evaluation circuit 610
When evaluating the source voltage (IS-VS) characteristics, the ground voltage GND is supplied to the pads 105 and 107. As a result, ring oscillator 201 is inactivated, and P-channel MOS transistor 302 and N-channel MOS transistor 303 are turned on.
N channel MOS transistor 304 is turned off. At this time, the voltage V2 supplied to the pad 102 and the pad 108
At the same time when the N-channel MOS transistor 303 is turned on.
The S-VS characteristic is measured using the pad 107.

In the semiconductor integrated circuit according to the present embodiment, the gate of P-channel MOS transistor 302 whose transistor characteristics are to be evaluated is connected to each of two-input NAND circuits 300 included in ring oscillator 201.
Are connected to the gates of P-channel MOS transistor 302 and N-channel MOS transistor 304, thereby reducing the antenna ratio and reducing the plasma damage to the gate of P-channel MOS transistor 302 from pad 105, thereby giving drain current characteristics. The effects are avoided.

[Fourth Embodiment] FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

As shown in FIG. 4, this semiconductor integrated circuit has a configuration similar to that of the semiconductor integrated circuit according to the second embodiment shown in FIG. And a pad 109 and a pad 110 are provided.

Here, the transistor characteristic evaluation circuit 710
The gates of P-channel MOS transistor 301 and N-channel MOS transistor 303 are connected to output node N3, and P-channel MOS transistor 30
2 and each gate of N-channel MOS transistor 304 are connected to pad 105.

A pad 110 is connected to the output node N4.
Pad 109 is connected to the drain of P-channel MOS transistor 302 and the source of P-channel MOS transistor 301, respectively.

With the above configuration, the P-channel MOS transistor 301 and the N-channel MOS transistor 304 are subjected to transistor characteristic evaluation.

The operation of the semiconductor integrated circuit according to the present embodiment will be described below. First, when evaluating the operation speed performance of a transistor, the ground voltage GND is applied to the pad 105.
Is supplied to the pad 109 and the pad 110 is brought into a floating state. Thereby, the ring oscillator 203 is activated and oscillates. At this time, by connecting an oscilloscope to the pad 104, the oscillation waveform (oscillation frequency) of the ring oscillator 203 is obtained.
Is observed.

Next, when evaluating the ID-VDD characteristic of the N-channel MOS transistor 304 in the transistor characteristic evaluation circuit 710, the voltage VDD is supplied to the pad 105. As a result, ring oscillator 203 is inactivated and N-channel MOS transistor 30
4 is turned on, and the N-channel MOS transistor 303 is turned off. At this time, since the P-channel MOS transistor 301 is also turned on, a voltage that changes from 0 V to the voltage VDD is supplied to both the pad 109 and the pad 110 at the same time, and the ID-VD characteristic when the N-channel MOS transistor 304 is turned on is measured. Measure using 110.

On the other hand, when evaluating the IS-VS characteristic of the P-channel MOS transistor 301 in the transistor characteristic evaluation circuit 710, the voltage VDD is applied to the pad 105,
The ground voltage GND is supplied to the pad 110. As a result, ring oscillator 203 is inactivated, and N channel MOS transistor 304 and P
The channel MOS transistor 301 is turned on, and the P-channel MOS transistor 302 is turned off. At this time, the voltage supplied to the pad 109 is changed from 0 V to the voltage VDD, and the IS-VS characteristic when the P-channel MOS transistor 301 is turned on is measured using the pad 109.

In the semiconductor integrated circuit according to the present embodiment, the gate of N-channel MOS transistor 304 whose transistor characteristics are to be evaluated is connected to the P-channel MOS transistor of each two-input NOR circuit 400 included in ring oscillator 203. Connected to the gates of transistor 302 and N-channel MOS transistor 304,
By reducing the antenna ratio and reducing the plasma damage to the gate of the N-channel MOS transistor 304 from the pad 105, the influence on the drain current characteristic is avoided.

[Fifth Embodiment] FIG. 5 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

As shown in FIG. 5, this semiconductor integrated circuit has the same configuration as the semiconductor integrated circuit according to the first embodiment shown in FIG. 1, except that pad 105 is included in transistor characteristic evaluation circuit 810. Inverter 44 connected to the drain of P-channel MOS transistor 302 to be evaluated and included in buffer 207
0,450 and a P-channel M
Pad 1 connected to the gate of OS transistor 302
11 is provided.

In order to avoid the influence of the plasma damage on the threshold voltage (Vth) and the drain current characteristic in the transistor characteristic evaluation, the pad 111
Is connected to the gate of a dummy P-channel MOS transistor 801. Here, “dummy” refers to an arbitrary P-channel MOS transistor included in another circuit (the same applies hereinafter).

The operation of the semiconductor integrated circuit according to the present embodiment will be described below. First, when evaluating the operation speed performance of the transistor, the voltage VDD is applied to the pad 105 as the voltage C. Thus, the ring oscillator 2
01 is activated and oscillates. At this time, the oscillation waveform (oscillation frequency) of the ring oscillator 201 using the pad 104
Is observed.

Next, when evaluating the IV characteristics of the P-channel MOS transistor 302 in the transistor characteristic evaluation circuit 810, the ground voltage GND is supplied to the pad 105. As a result, ring oscillator 201 is inactivated, and P-channel MOS transistor 301 in transistor characteristic evaluation circuit 810 is turned off.
At this time, by changing the voltage supplied to the pad 102 and the pad 111 from 0V to the voltage VDD,
The ID-VD characteristics and the drain current / gate voltage (ID-VG) characteristics of the P-channel MOS transistor 302 can be evaluated.

[Sixth Embodiment] FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

As shown in FIG. 6, this semiconductor integrated circuit has the same structure as the semiconductor integrated circuit according to the fifth embodiment shown in FIG.
An N-channel MOS transistor 304 is connected between them, and the pad 111 has an N-channel MOS transistor 3 connected thereto.
04 and a dummy N-channel MOS transistor 802 for avoiding the influence of plasma damage on threshold voltage (Vth) and drain current characteristics
In that they are connected to the gates of the two.

The operation of the semiconductor integrated circuit according to the present embodiment will be described below. First, when evaluating the operation speed performance of the transistor, the voltage VDD is applied to the pad 105 as the voltage C. Thus, the ring oscillator 2
01 is activated and oscillates, and its oscillation waveform (oscillation frequency) is observed using the pad 104.

Next, when the IV characteristic of the N-channel MOS transistor 304 in the transistor characteristic evaluation circuit 910 is to be evaluated, the ground voltage GND is supplied to the pad 105. As a result, ring oscillator 201 is inactivated, and P-channel MOS transistor 301 in transistor characteristic evaluation circuit 910 is turned off.
At this time, by changing the voltage supplied to the pad 102 and the pad 111 from 0V to the voltage VDD,
The ID-VD characteristics and the ID-VG characteristics of the N-channel MOS transistor 304 can be evaluated.

[0068]

According to the semiconductor integrated circuit of the first aspect, the operating speed performance of the transistors manufactured with the same dimensions without considering the variation in the gate dimensions of the first transistor and the second transistor. Current / voltage characteristics can be evaluated.

Further, the second relationship is obtained from the relationship between the transistor characteristics and the actually measured gate dimensions and circuit simulation.
The gate size of the first transistor included in the oscillating means can be electrically estimated based on the current / voltage characteristics measured by the transistor.

According to the semiconductor integrated circuit of the second aspect,
The operating speed performance and the drain current / drain voltage characteristics of transistors manufactured with the same dimensions can be evaluated without considering the variation in the gate dimensions of the first transistor and the second transistor.

According to the semiconductor integrated circuit of the third aspect,
Operating speed performance of first transistor and P-channel MOS
The drain current / drain voltage characteristics of the transistor can be evaluated.

According to the semiconductor integrated circuit of the fourth aspect,
Operating speed performance of first transistor and N-channel MOS
The drain current / drain voltage characteristics of the transistor can be evaluated.

According to the semiconductor integrated circuit of the fifth aspect,
The operating speed performance of the first transistor, the drain current / drain voltage characteristics of the second transistor, and the source current / source voltage characteristics of the third transistor can be evaluated.

According to the semiconductor integrated circuit of the sixth aspect,
The operating speed performance of the first transistor and the P-channel MO
Drain current / drain voltage characteristics of the S transistor,
The source current / source voltage characteristics of the N-channel MOS transistor can be evaluated.

According to the semiconductor integrated circuit of the seventh aspect,
The operating speed performance of the first transistor and the N-channel MO
Drain current / drain voltage characteristics of the S transistor,
The source current / source voltage characteristics of the P-channel MOS transistor can be evaluated.

According to the semiconductor integrated circuit of the eighth aspect,
The operating speed performance of the first transistor and the drain current / drain voltage characteristics and the drain current / gate voltage characteristics of the second transistor can be evaluated.

According to the semiconductor integrated circuit of the ninth aspect,
Operating speed performance of first transistor and P-channel MOS
The drain current / drain voltage characteristics and the drain current / gate voltage characteristics of the transistor can be evaluated.

According to the semiconductor integrated circuit of the tenth aspect, the operating speed performance of the first transistor and the N-channel M
The drain current / drain voltage characteristics and the drain current / gate voltage characteristics of the OS transistor can be evaluated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration for evaluating characteristics of a conventional P-channel MOS transistor.

FIG. 8 is a diagram showing a configuration for evaluating characteristics of a conventional N-channel MOS transistor.

FIG. 9 is a circuit diagram showing a configuration of a conventional ring oscillator for evaluating the operation speed performance of a transistor.

FIG. 10 is a circuit diagram showing a specific configuration of the NAND circuit shown in FIG. 9;

11 is a circuit diagram showing a specific configuration of the inverter shown in FIG.

FIG. 12 is a view showing a chip formed on a conventional wafer.

FIG. 13 is a block diagram showing a configuration of the chip shown in FIG.

[Explanation of symbols]

102, 105, 111 pads, 201, 203 ring oscillators, 301, 302, 801 P-channel MOS transistors, 303, 304, 802 N-channel MOS transistors.

Claims (10)

[Claims] An oscillating means including a first pad, a first transistor, and activated when a voltage having a first logic level is supplied to the first pad; And a second transistor connected to the pad. 2. The second transistor, wherein a gate of the second transistor is connected to the first pad, and the second transistor is turned on when a voltage having a second logic level is supplied to the first pad. Item 2. The semiconductor integrated circuit according to item 1. 3. The method according to claim 1, wherein the second transistor is a P-channel transistor.
3. The semiconductor integrated circuit according to claim 2, which is an OS transistor. 4. The semiconductor device according to claim 1, wherein said second transistor is an N-channel transistor.
3. The semiconductor integrated circuit according to claim 2, which is an OS transistor. 5. The first transistor has a gate connected to the first pad, and is turned on when a voltage having a second logic level is supplied to the first pad. 2. The semiconductor integrated circuit according to claim 1, further comprising a third transistor of a conductivity type, a second conductivity type having a gate connected to an output node of the oscillation unit. 3. 6. The second transistor is a P-channel transistor.
An OS transistor, wherein the third transistor is N
The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is a channel MOS transistor. 7. The second transistor is an N-channel transistor.
An OS transistor, wherein the third transistor is P
The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is a channel MOS transistor. 8. The semiconductor device further comprising a second pad, a third pad, and a third transistor having a gate connected to the third pad, wherein the second transistor is connected to the first pad. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to the second pad, a gate is connected to the third pad, and has the same conductivity type as the third transistor. 3. 9. The semiconductor device according to claim 1, wherein the third transistor is a P-channel transistor.
The semiconductor integrated circuit according to claim 8, wherein the semiconductor integrated circuit is an OS transistor. 10. The semiconductor integrated circuit according to claim 8, wherein said third transistor is an N-channel MOS transistor.