JPH1116963A - Test method and equipment for semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method and an equipment for a semiconductor wafer, wherein simultaneous test of a plurality of semiconductor chips is facilitated while corresponding to a very large aperture semiconductor wafer, and the shortening of test time and further reduction of moving distance are also enabled. SOLUTION: A probe card 101 has four probe groups 202. The four probe groups 202 divide a semiconductor chip 203 formed on a semiconductor wafer 201 into four blocks of 4×4 and arrange the four blocks, to as to have relative positioned relations (i.e., the same positions are obtained in the respective blocks). By performing an operation test in the order indicated an arrow, operation test of the semiconductor chip 203 wherein a plurality of semiconductor chips can be simultaneously tested, test time is shortened and moving distance of the semiconductor wafer 201 is reduced is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for testing a semiconductor wafer, and more particularly, to a method for testing a plurality of semiconductor chips while reducing an absolute movement error resulting from movement of the semiconductor wafer during the test. The present invention relates to a method and an apparatus for testing a semiconductor wafer which facilitates simultaneous testing of semiconductor wafers and enables measurement of an ultra-large-diameter semiconductor wafer.

[0002]

2. Description of the Related Art Generally, an operation test of a semiconductor chip is performed in a state of a semiconductor wafer (a plurality of semiconductor chips are formed) before being cut for each semiconductor chip. An operation test of each semiconductor chip formed on the semiconductor wafer is performed electrically by pressing a stylus into contact with each connection terminal (hereinafter, referred to as a pad) of the semiconductor chip.

FIG. 4 is a block diagram showing a simple configuration of a conventional semiconductor wafer test apparatus. In FIG. 4, a conventional semiconductor wafer test apparatus 400 includes a probe card 401, a semiconductor wafer moving device 102, an electric circuit 103, and a CPU 104. In FIG. 4, the probe card 401 and the semiconductor wafer moving device 1
The dashed arrow connecting 02 has a mechanical connection relationship.

FIG. 5 shows an example of the configuration of the probe card 401. As shown in FIG. FIG. 5A is a view of the probe card 401 as viewed from below, and FIG.
It is the figure which showed the A section. In FIG. 5, a probe card 401 basically includes a stylus 202a and a substrate 501. As a material of the stylus 202a, a hard good conductor such as tungsten is used. Also, the stylus 202a
Is one end (FIG. 5B) as shown in FIG.
The part B in the middle is processed so as to be able to press and contact the pad, and the other end (the part C in the figure) is electrically connected to the substrate 501 by solder 503 or the like so that signals and the like can be exchanged. Connected. A plurality of the styluses 202a are arranged on a substrate 501 (hereinafter, referred to as a stylus group 202) in such a manner as to correspond to the positions of pads (not shown) for one semiconductor chip to be tested. In addition, each stylus 2
02a is fixed to the substrate 501 using a thermosetting resin 502 or the like. It should be noted that the probe card 401 is fixedly attached to the test device 400 (the attachment method is not directly related to the present invention, and therefore the description is omitted here).

FIG. 8 shows an example of the functions of the semiconductor wafer moving apparatus 102. In FIG. 8, a semiconductor wafer moving apparatus 102 includes a chuck 801 on which a semiconductor wafer 201 is mounted by means such as vacuum suction, and a chuck 8.
01 and the rail 802 that allow the chuck 801 to slide in the Y direction.
3 is provided. Further, the semiconductor wafer moving device 102
Although not shown, has a means for raising and lowering the chuck 801. Thus, the semiconductor wafer 2
01 can move freely in a three-dimensional space. Note that the semiconductor wafer moving apparatus 102 includes a chuck 801.
So that the plane is parallel to the probe card 401 plane,
It is fixedly attached to the test device 400 (the attaching method is not directly related to the present invention, and therefore, the description is omitted here).

In FIG. 4, an electric circuit 103 supplies a power supply or a signal for an operation test to a stylus 202 a of a probe card 401. The CPU 104 controls the movement so that each pad of the semiconductor chip formed on the semiconductor wafer 201 placed on the chuck 801 of the semiconductor wafer moving device 102 comes into pressure contact with the stylus 202a. Further, the CPU 104 gives an instruction to start an operation test of the semiconductor chip to the electric circuit 103 and determines whether the operation test has been completed normally.

FIG. 6 shows a conventional method for testing a semiconductor wafer performed by the test apparatus 400 having the above configuration.
There is a test method shown below. FIG. 6 illustrates a conventional method for testing a semiconductor wafer.
FIG. 2 is a diagram showing a vertical positional relationship between a semiconductor wafer 201 and a probe card 401 on the first embodiment. Note that, in FIG. 6, the semiconductor wafer 201 and the probe card 401 are arranged at a constant interval. The conventional test method in FIG. 6 (hereinafter, referred to as a first conventional test method) includes a stylus group 202 for one semiconductor chip 203.
The operation test is performed on all the semiconductor chips 203 formed on the semiconductor wafer 201 by using the probe card 401 on which is formed. On the semiconductor wafer 201, 8 × 8 semiconductor chips 203 are formed (in FIG. 6, blocks in which the semiconductor chips 203 exist are denoted by a to a).
Defined in h rows and 1 to 8 columns, the position is hereinafter referred to as "a1"
Etc.). In each block in FIG.
1 "is present (note that the semiconductor wafer 201 has a circular shape, so that there are only 32 semiconductor chips 203 in the perfect shape at the center). The operation will be described.

First, the semiconductor wafer 201 is moved to insert the semiconductor chip 203 of “a1” into the probe card 401.
(The position where each pad 203a and the stylus 202a coincide with each other). Then, the semiconductor wafer 201 is raised by the chuck 801, and the operation test is performed by pressing the pad 203 a of the semiconductor chip 203 of “a 1” into contact with the stylus 202 a of the probe card 401. After the operation test of the “a1” semiconductor chip 203 is completed, the semiconductor wafer 201 is lowered, and then the semiconductor wafer 201 is moved by one (one pitch) of the semiconductor chip 203 to remove the “a2” semiconductor chip 203. Bring it just below the probe card 401. Then, the operation test of the semiconductor chip 203 of “a2” is performed as described above. This operation is repeated, and in the order of the arrows shown in FIG.
The operation test of all the semiconductor chips 203 is performed.

As described above, the first conventional test method uses the probe card 401 having one stylus group 202.
By using 63 times, the movement of the semiconductor wafer 201 and the operation test of 64 times
3 operation test. However, this first
In the conventional test method of (1), since the movement and operation test are performed for each semiconductor chip 203, it takes time.

In order to solve the above problem, a probe card 401 provided with a plurality of stylus groups 202 corresponding to a plurality of adjacent semiconductor chips 203 is used. A method of performing an operation test of 203 is used. FIG. 7 shows an example of this test method. FIG. 7 is a view similar to FIG. 6 for explaining a conventional method of testing a semiconductor wafer.
FIG. 3 is a diagram illustrating a vertical positional relationship between a probe card 701 and a probe card 701; The conventional test method shown in FIG. 7 (hereinafter, referred to as a second conventional test method) uses a probe card 701 provided with four stylus groups 202 adjacent to one probe card 701. The four semiconductor chips 203 (“a1”, “b1”,
An operation test of “c1” and “d1”) is performed. As a result, in the second conventional test method, the operation test of all 64 semiconductor chips 203 can be performed only by the movement 15 times and the operation test 16 times in the order of the arrows shown in FIG.

[0011]

In recent years, with the remarkable progress of the technology for increasing the degree of integration of semiconductors, reductions in the size of semiconductor elements and finer wiring dimensions have been made. Along with this,
The number of semiconductor chips 203 formed on one semiconductor wafer 201 has also increased, and the size of the semiconductor wafer has also been reduced from the currently mainstream 6 inches to 8 inches or the next generation 1 inch.
It is expanding to 2 inches.

However, in the above-described first conventional test method, as the number of semiconductor chips 203 formed on one semiconductor wafer 201 increases, the number of operation tests increases and it takes time. In the first conventional test method, the probe card 401 is located at all positions of the semiconductor chips 203 formed on the semiconductor wafer 201.
Must be moved (actually, the chuck 801 is moved), and therefore, there is a problem in that absolute movement accuracy is deteriorated. That is, even if the relative error for one pitch is small, the absolute error increases in proportion to the size of the semiconductor wafer 201 (specifically, from “a1” to “h8” in FIG. 6). Is 7 times the relative error for one pitch). Further, since the probe card 401 must be moved to all positions of the semiconductor chip 203 formed on the semiconductor wafer 201, the size of the test device 400 is
01, the size of the test apparatus 400 cannot be reduced due to an increase in the size of the semiconductor wafer.

In the above-described second conventional test method, a probe card provided with a plurality of adjacent stylus groups 202 is provided in order to reduce the number of operation tests and the moving distance in the first conventional test method. 701 is used to test the operation in parallel. However, the above-described semiconductor high integration technology not only reduces the size of the semiconductor element and the wiring size, but also reduces the pad size and the interval between adjacent pads. It is sufficient to reduce the interval between adjacent pads if only one stylus group 202 is provided on the probe card 701. However, it is preferable to provide a plurality of adjacent stylus groups 202 in parallel (especially, pads on adjacent sides). Is extremely difficult. For example, when the operation test of four semiconductor chips 203 having 64 pads is performed simultaneously by the second conventional test method, 64 × 4 = 256 stylus 202a
Must be centrally located next to each other, which is quite difficult.

Therefore, an object of the present invention is to provide a probe having a sufficient margin while supporting a super-large-diameter semiconductor wafer, to enable simultaneous testing of a plurality of semiconductor chips, and An object of the present invention is to provide a method and an apparatus for testing a semiconductor wafer, which can shorten the test time and further reduce the moving distance (ie, moving error).

[0015]

Means for Solving the Problems and Effects of the Invention According to a first aspect of the present invention, a plurality of semiconductor chips formed on a semiconductor wafer are tested by bringing a plurality of contact pads of the semiconductor chips into contact with a group of styluses. A semiconductor wafer test method, wherein a plurality of semiconductor chips are divided into a plurality of blocks of the same shape, and a plurality of styluses capable of simultaneously pressing and contacting the plurality of semiconductor chips at predetermined positions of the blocks. By using a probe card in which a group is integrally formed two-dimensionally, a stylus group corresponding to one of the blocks is sequentially tested only for semiconductor chips existing within the range of the one block. In addition, all of the plurality of semiconductor chips formed on the semiconductor wafer can be tested by the plurality of stylus groups.

According to a second aspect of the present invention, there is provided a semiconductor wafer test apparatus for testing a plurality of semiconductor chips formed on a semiconductor wafer by bringing a plurality of semiconductor chips into press contact with connection pads of the semiconductor chips and stylus groups. A plurality of semiconductor chips are divided into a plurality of blocks of the same shape, and a plurality of stylus groups capable of simultaneously pressing and contacting the plurality of semiconductor chips at predetermined positions of the plurality of blocks are integrally formed two-dimensionally. A probe card, a moving device for mounting the semiconductor wafer, and three-dimensionally moving the semiconductor wafer so that the plurality of connection pads formed on the semiconductor wafer and the plurality of stylus groups can be brought into press contact with each other; And the stylus group corresponding to one of the blocks is related only to the semiconductor chips existing within the range of the one block. By performing sequential testing, and wherein the possible all the tests of the plurality of semiconductor chips formed into semiconductor wafers by a plurality of probe groups.

According to a third aspect of the present invention, there is provided a probe card used for testing a semiconductor wafer on which a plurality of semiconductor chips are formed, wherein a plurality of stylus groups capable of simultaneously contacting some of the plurality of semiconductor chips are provided. It is characterized by being formed two-dimensionally and integrally with an arbitrary relative positional relationship.

As described above, the first to third inventions relate to a probe card provided with a plurality of stylus groups at predetermined positions in arbitrary blocks, and a test method using each probe card. And the invention of the test device and the probe card itself. By using this probe card, a large number of semiconductor chips can be tested for operation at the same time, and a dedicated stylus group corresponding to each block is provided, so only by moving the semiconductor wafer within the block range The operation test of all the semiconductor chips formed on the semiconductor wafer can be performed. Further, the moving range of the semiconductor wafer required for the operation test can be reduced to within the block range, so that the operation test time can be shortened, the moving accuracy can be improved, and the size of the moving device mechanism and the entire device can be reduced. Furthermore, the fact that the moving distance is small means that the use of this probe card makes it possible to use an 8 inch or 1 inch in an apparatus for a semiconductor wafer having a size of 6 inches.
It is also possible to use semiconductor wafers up to 2 inches in size.

[0019]

FIG. 1 is a block diagram showing a configuration example of a test apparatus for realizing a semiconductor wafer test method according to an embodiment of the present invention. Referring to FIG. 1, a test apparatus 100 for realizing a semiconductor wafer test method according to an embodiment of the present invention includes a probe card 101, a semiconductor wafer moving apparatus 102, an electric circuit 103, and a CPU 104. In FIG. 1, a probe card 101 and a semiconductor wafer moving device 1 are shown.
The dashed arrow connecting 02 has a mechanical connection relationship. Since the configuration other than the probe card 101 is the same as that of the conventional test apparatus 400 shown in FIG. 4, the same reference numerals are given below, and description thereof will be omitted. Further, the semiconductor wafer 201 used in the following description is also described in the related art,
An 8 × 8 semiconductor chip 203 is formed.

FIG. 2 shows a method for testing a semiconductor wafer according to an embodiment of the present invention, which is implemented by the test apparatus 100 having the above configuration. FIG. 2 illustrates a method of testing a semiconductor wafer according to an embodiment of the present invention.
FIG. 6 is a diagram showing a vertical positional relationship with the image data 01. In FIG. 2, the semiconductor wafer 201 and the probe card 101
And are arranged at regular intervals.

As shown in FIG. 2, the probe card 101
Has four stylus groups 202 that are not adjacent to each other. The four stylus groups 202 divide 64 semiconductor chips 203 of “a1” to “h8” into four 4 × 4 blocks of the same shape (abcd rows × 1234 columns, efgh rows × 1234).
Columns, abcd rows x 5678 columns, efgh rows x 5678
The four blocks are arranged so as to have a relative positional relationship (that is, the same position in each block, which is the upper left in FIG. 2).

Semiconductor wafer 201 and probe card 1
The initial state of 01 is at the position shown in FIG. In this state, the semiconductor wafer 201 is lifted by the chuck 801, and “a1” and “a” are respectively
An operation test is performed on the semiconductor chip 203 at the positions of "5", "e1", and "e5". When the operation test at this position is completed, the chuck 801 is lowered, and the semiconductor wafer 201 is moved by one pitch (FIG. 2 is to the left as viewed in the figure) and then “a2”,
The operation proceeds to the operation test of the semiconductor chip 203 at the positions of “a6”, “e2” and “e6”. As described above, the operation test is performed in the order of the arrows shown in FIG. 2, and the operation test of the semiconductor chip 203 at the last positions “d1”, “d5”, “h1”, and “h5” is performed. Thus, the operation test of all 64 semiconductor chips 203 is completed.

As described above, in the method of testing a semiconductor wafer according to one embodiment of the present invention, a plurality of stylus groups 202 are set in a two-dimensional relative positional relationship on the probe card 101 used for the operation test. By doing so, there is an effect that the moving distance of the semiconductor wafer 201 (that is, the chuck 801) can be reduced.

The above effect will be specifically described by comparing FIG. 2 and FIG. In the second test method in FIG. 7, in order to perform operation tests on all the semiconductor chips 203,
The semiconductor wafer 201 must be moved by four rows in the row direction and by seven columns in the column direction (since the stylus group 202 which is initially in the “a1” position must be moved to the “e8” position) Is). On the other hand, in the test method according to the embodiment of the present invention in FIG. 2, in order to perform an operation test on all the semiconductor chips 203, three rows in the row direction are required.
It is only necessary to move three rows in the column direction (because the stylus group 202 initially at the position "a1" can be moved to the position "d4" even at the farthest position). Therefore, the moving distance of the semiconductor wafer 201 is about 1/2 (= √ (18/65)) in the linear distance in the test method according to the embodiment of the present invention, compared with the second conventional test method. Will be done. As a result, the absolute movement error resulting from the integration of the relative movement errors for one pitch can be reduced, that is, the accuracy of the operation test itself can be improved. In addition, the fact that the movement distance of the semiconductor wafer 201 can be reduced means that the mechanism of the test apparatus 100 (that is, the size of the test apparatus 100 itself, the test installation 100
Floor area, etc.) can be reduced. The test apparatus 10 in the test method according to one embodiment of the present invention
The reduction ratio of the zero mechanism is about 1/3 (= 9/28).

In the comparison between FIG. 2 and FIG. 7, the reduction of the moving distance of the semiconductor wafer 201 is about 1/2.
It is about. However, as described above, with the integration of semiconductors, trends such as an increase in the number of semiconductor chips 203 formed on one semiconductor wafer 201 and an increase in the inch size of the semiconductor wafer 201 itself are considered in the future. The test method according to an embodiment of the present invention was invented in view of these trends, and has a feature that the larger the size of the test target from the trends, the more remarkable the above-mentioned effects are exhibited. ing.

The method for testing a semiconductor wafer according to one embodiment of the present invention is such that a plurality of stylus groups are two-dimensionally arranged at an arbitrary interval on a probe card 101 used for an operation test. Each stylus group 202 can be configured with a margin without being affected by the high integration of the semiconductor. That is, as in the second conventional test method, the stylus group 202 is one-dimensionally placed on the probe card 701.
Are arranged, the stylus 202 to test the pad 203a existing on the side where the semiconductor chips 203 are in contact with each other
As for a, it is not easy to configure because the styluses 202a are too dense. For this reason, there is a high possibility that the second conventional test method will not be able to cope with high integration of semiconductors in the future. On the other hand, the probe card 101 in the method for testing a semiconductor wafer according to one embodiment of the present invention can form the plurality of stylus groups 202 without being affected by the high integration of semiconductors. .

Further, the method for testing a semiconductor wafer according to one embodiment of the present invention has the following features. Second
As in the conventional test method of
If the stylus group 202 is arranged in a dimension, the number of stylus groups 202 that can be configured is limited. That is, in FIG. 7, only up to eight stylus groups 202, which is the number of rows or columns, can be configured on the probe card 701 (because it does not make sense to configure more than eight). On the other hand, the semiconductor wafer test method according to one embodiment of the present invention can simultaneously perform operation tests on more semiconductor chips 203 by changing the configuration of the divided blocks. For example, in a 2 × 2 block, 16
In the case of division, the stylus group is
It is possible to configure six, and in this case, it is possible to perform an operation test on 16 semiconductor chips 203 simultaneously by one movement of the semiconductor wafer 201.

Since the semiconductor wafer 201 is generally circular, the corners in the above description (for example, “a1”, “a2”, “b1”, etc. in FIG. 2) have no product. No complete semiconductor chip 203 exists. Therefore, it is not necessary to perform an operation test on the corner portion. Therefore, in the method of testing a semiconductor wafer according to the present invention, as shown in FIG. 3, it is possible to omit the test of the corner portion by devising the block division. In FIG. 3, 3
The × 3 blocks are sectioned along the circular shape of the semiconductor wafer 201, and a stylus group 202 (indicated by ● in FIG. 3) is provided. As a result, it is possible to omit a test of a useless portion (a hatched portion in FIG. 3) and to improve the efficiency of the entire test.

In the above description, with respect to the pressing contact operation between the stylus 202a and the pad 203a, the chuck 8
01, the semiconductor wafer 201 was raised, but the probe card 101
It is also possible to go down. The initial state of the probe card 101 in the semiconductor wafer test method according to the embodiment of the present invention is such that the stylus group 202 comes to the positions of “a1”, “a5”, “e1” and “e5”, respectively. However, the position is not limited to these, and if it can be moved in a continuous operation in the divided block, other positions may be maintained on condition that the relative positional relationship of the plurality of stylus groups 202 is maintained. The position can be set to the initial state.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one configuration example of a test apparatus for realizing a semiconductor wafer test method according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of testing a semiconductor wafer according to one embodiment of the present invention.

FIG. 3 is a view illustrating a method of testing a semiconductor wafer according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a test apparatus for realizing a conventional semiconductor wafer test method.

FIG. 5 is a diagram showing an example of the structure and shape of a probe card.

FIG. 6 is a diagram showing a first conventional semiconductor wafer test method.

FIG. 7 is a diagram showing a second conventional semiconductor wafer test method.

FIG. 8 is a view showing a slide mechanism of a chuck for mounting a semiconductor wafer.

[Explanation of symbols]

 100, 400: Test device 101, 401, 701: Probe card 102: Semiconductor wafer moving device 103: Electric circuit 104: CPU 201: Semiconductor wafer 202: Stylus group 202a: Stylus 203: Semiconductor chip 203a: Pad 501: Substrate 502: thermosetting resin 503: solder 801: chuck 802, 803: rail

Claims (3)

[Claims] 1. A method for testing a semiconductor wafer by testing a plurality of semiconductor chips formed on a semiconductor wafer by pressing a plurality of semiconductor chips into contact with a group of stylus pads, said plurality of semiconductor chips comprising: A probe in which a chip is divided into a plurality of blocks having the same shape, and a plurality of the stylus groups capable of simultaneously pressing and contacting the semiconductor chips at predetermined positions of the plurality of blocks are integrally formed two-dimensionally. By using a card, the stylus group corresponding to one of the blocks sequentially performs the test only on the semiconductor chips existing within the range of the one block, thereby providing a plurality of the stylus groups. By the test of all of the plurality of semiconductor chips formed on the semiconductor wafer is possible,
Test method for semiconductor wafer. 2. A semiconductor wafer test apparatus for testing a plurality of semiconductor chips formed on a semiconductor wafer by bringing a plurality of semiconductor chips into press contact with a group of styluses and a plurality of said semiconductor chips. A probe in which a chip is divided into a plurality of blocks having the same shape, and a plurality of the stylus groups capable of simultaneously pressing and contacting the semiconductor chips at predetermined positions of the plurality of blocks are integrally formed two-dimensionally. A card, on which the semiconductor wafer is mounted, and a movement for three-dimensionally moving the semiconductor wafer such that the plurality of connection pads formed on the semiconductor wafer and the plurality of stylus groups can be in press contact with each other. A stylus group corresponding to one of the blocks is present within the range of the one block By performing the test sequentially only on the semiconductor chip, the test of all of the plurality of semiconductor chips formed on the semiconductor wafer by the plurality of stylus groups is possible,
Test equipment for semiconductor wafers. 3. A probe card used for testing a semiconductor wafer formed with a plurality of semiconductor chips,
A probe card, wherein a plurality of stylus groups capable of simultaneously contacting some of the plurality of semiconductor chips are integrally formed two-dimensionally with an arbitrary relative positional relationship.