JPH11167516A - System and method for multiple memory access and recording medium where control method thereof it recorded - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the processing performance of a processor which has load store units by reducing the hardware quantity of a store buffer and also eliminating false dependency relation generated between load instructions. SOLUTION: An address comparator 103 compares the store instruction 101 with the address stored in an effective entry of an alias table 102 and a matching entry is read out. The alias address of the read matching entry and the address of the instruction 101 are registered in a reorder buffer 106 and the store value of the instruction 101 is registered in a store buffer 107. Then one unused alias address is read out of a release table 105 and stored in the entry of the alias entry and the entry of the store buffer 107. When the store instruction 101 is completed, the alias address of the entry of the alias table 10s 102 is registered as an unused alias address in the release table 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex memory access system, an access method, and a recording medium on which a control method thereof is recorded, and more particularly to a multiplex memory access system of a processor having a plurality of load / store units, an access method, and a control method thereof. It relates to a recording medium on which is recorded.

[0002]

2. Description of the Related Art In a current super scalar processor,
In order to access the main memory at high speed, it is common to mount a plurality of load store units and execute load store processing in random order (parallel). In this case, the dependence relation (direct dependence, inverse dependence, and output dependence) on the memory address between the instructions can be detected when the address is determined after the instruction is issued.

[0003] Here, the direct dependency is a dependency that occurs when a preceding store instruction and a subsequent load instruction in the program order access the same memory address. The reverse dependence is a dependence relationship that occurs when a preceding load instruction and a subsequent store instruction in the program order access the same memory address in any order.
Further, the output dependency is a dependency that occurs when a preceding store instruction and a subsequent store instruction in the program order access the same memory address in any order.

[0004] Instructions having these dependencies cannot be executed in parallel because the correct result cannot be obtained unless they are executed in the program order. However, regarding the inverse dependence and the output dependence, even if the instructions are executed out of order with the preceding instruction having the dependence, the store address and the store value are held in a temporary buffer without accessing the main memory,
After the preceding instruction has completed the access to the main memory, the store address and the stored value are taken out from the buffer to access the main memory, thereby guaranteeing the main memory access in the program order. That is, parallel execution of load store instructions that are inversely dependent or output dependent is possible.

In a conventional processor, this temporary buffer is implemented as a store buffer as shown in FIG. The store buffer 302 stores a store address (AD
R) and a buffer for storing the store instruction in which the store value (VAL) is determined in the program order. The load instruction or the store instruction 301 whose address has been determined is compared by an address comparator 303 with an address stored in a valid entry of a store buffer 302 having a plurality of entries for storing a store address and a store value,
The matching entry detector 304 detects the presence or absence of a dependency and the entry number whose address matches.

When the instruction 301 is a load instruction following all valid store instructions existing in the store buffer 302 and a matching entry exists (a direct dependency), the main memory is not accessed and the matching entry is deleted. The store data (VAL) can be forwarded (used as a forwarding value) and used.

When the instruction 301 is a preceding load instruction, even if there is an entry having the same address in the store buffer 302 (an inverse dependency), the instruction is ignored and the main memory is accessed to access the main memory. The dependent load instruction and the subsequent store instruction can be executed out of order.

When the instruction 301 is a store instruction, even if it is executed in any order, it is stored in the store buffer 302 in the program order, so that the output dependency is eliminated in the store buffer 302 as a result. Become.

That is, the reverse dependence and the output dependence on the memory access are eliminated by renaming the address of the store instruction in the store buffer 302 (holding the same store address as a different address in the program order). And the like can be executed in parallel to improve the processing performance of the processor.

[0010]

However, the detection of the dependency and the renaming of the store address need only be performed on the address, and need not be performed on the store value.
Further, the memory space is larger than the register space (at most 32), and there is a possibility that a plurality of dependencies may occur in a wide range. Therefore, a large number of entries are required to store the store address. Therefore, when a store buffer is used, a field of a store value unnecessary for renaming is included in the store buffer, so that there is a problem that the amount of hardware is unnecessarily increased with an increase in the number of entries. .

In addition, since the number of entries in the store buffer is related to the number of simultaneous instructions issued, there is a problem that even if the number of entries is excessively increased, it does not contribute to performance improvement. For example, in superscalar processing in which four instructions are issued simultaneously, at most four entries are sufficient, and even if a larger number of entries are implemented, it does not contribute to performance improvement.

An object of the present invention is to separate the hardware for renaming addresses from the function of a store buffer, thereby increasing the number of store instructions capable of renaming addresses, and the hardware of the store buffer. It is an object of the present invention to provide a multiplex memory access system capable of saving an amount, a method thereof, and a recording medium recording the control method thereof.

[0013]

According to the present invention, there is provided a multiplex memory access system in a processor having a plurality of load store processing units for executing load store processing to a memory in random order. A multiple memory access system is obtained in which different short bit length alias addresses are managed in association with store instructions.

An alias table having a plurality of entries for storing a set of a store address accessed by the store instruction and an alias address associated with the store address, a corresponding alias provided corresponding to the alias address An open table indicating whether an address has been used, a store buffer having a plurality of entries for storing a set of the latest alias address and a store value of the store instruction, and a set of an old alias address and a store address are stored. A reorder buffer having a plurality of entries, a store address of a store instruction determined after address calculation is given to the alias table and the reorder buffer, and a store value of the store instruction is given to the store buffer. Replace the alias address with the old alias address in the reorder buffer. Means for giving an unused alias address of the release table to the alias table and the store buffer, respectively, and controlling to transmit a store value of the store buffer and a store address of the reorder buffer to a memory. It is characterized by the following.

According to the present invention, there is provided an alias table having a plurality of entries for storing a set of a store address accessed by a store instruction and an alias address associated with the store address. An open table indicating whether the corresponding alias address has been used, a store buffer having a plurality of entries for storing a set of the latest alias address and the store value of the store instruction, an old alias address and a store address. And a reorder buffer having a plurality of entries for storing sets of data, and a multiple memory access method in a processor having a plurality of load store processing units for executing load store processing to a memory in random order, Assign unused entries in the reorder buffer at times Registering the store address determined by the address calculation as a valid entry in the valid entry; and comparing the store address with the store addresses stored in all the valid entries of the alias table, there is an entry that matches. Reading the alias address of the matching entry and registering it in the old alias address portion of the valid entry in the reorder buffer; and obtaining an unused alias address from the release table to obtain the matching entry in the alias table. Registering in the alias address portion of the storage buffer and also in the latest alias address portion of the specific entry of the store buffer; and when the store data of the store instruction is determined, the store data is stored in the entry of the store buffer. Store in the store value part of Multiple memory access method which comprises the step is obtained.

According to the present invention, there is provided an alias table having a plurality of entries for storing a set of a store address accessed by a store instruction and an alias address associated with the store address. An open table indicating whether the corresponding alias address has been used, a store buffer having a plurality of entries for storing a set of the latest alias address and the store value of the store instruction, an old alias address and a store address. And a reorder buffer having a plurality of entries for storing a set of sets, and a program for causing a computer to execute a multiple memory access method in a processor having a plurality of load store processing units for executing load store processing on a memory in random order. A storage medium on which the storage order is stored. Assigning an unused entry in the reorder buffer as a valid entry at the time of decoding, and registering the store address determined by address calculation in the valid entry; and storing the store address and all the valid entries in the alias table in the alias table. If there is an entry that matches with the stored address, the alias address of the matching entry is read and registered in the old alias address portion of the valid entry in the reorder buffer; Acquiring the alias address and registering it in the alias address portion of the matching entry in the alias table, and also registering it in the latest alias address portion of the specific entry in the store buffer; and determining the store data of the store instruction. At this point, the store Recording medium for recording a program and storing the data in the store value of the entries of the store buffer is obtained.

According to the present invention, the hardware for renaming the store address is provided separately from the store buffer, so that the number of entries of the alias address is increased without increasing the hardware regardless of the number of entries in the store buffer. It becomes possible. Further, since the store value is not necessary for renaming the address, the amount of hardware can be reduced as compared with the case where the number of entries in the store buffer is increased and the address renaming of a plurality of store instructions is performed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. Referring to FIG. 1, a store instruction 101
Is generated from an instruction issuing function unit (not shown), and the content STORE of the instruction, the store address ADR, and the store value V
AL. Alias table 102 has store address A
There is provided an entry which can store a plurality of sets of DR and a corresponding alias address ADR 'as a set. The release table 105 stores the status of use (NOT FREE) / unused (FREE ADR ') of the alias address ADR' of each entry of the alias table 102. Alias address is store address ADR of store instruction
It is assumed that the bit length is set shorter than.

The address comparator 103 has an address part (ADR) of the store instruction 101 whose address has been determined and an address part (AD) of all valid entries of the alias table 102.
R). Match entry detector 10
Reference numeral 4 denotes an entry whose store address matches from the result of the address comparator 103.

The reorder buffer 106 stores a set of an old alias address (OLD ADR ') and a corresponding store address in a program order. The store buffer 107 stores a set of the latest alias address (NEW ADR ') and a store value (VAL) in a program order.

When the store instruction 101 is decoded in the processor, entries are secured in the reorder buffer 106 and the store buffer 107, respectively. After that, the store instruction 101 whose address calculation is completed is compared with the addresses stored in all valid entries in the alias table 102 by the comparator 103 provided for each entry. The comparison result is supplied to the matching entry detector 104, and an entry matching the address of the store instruction 101 is detected.

Next, the alias address of the matching entry is read from the alias table 102, and is read from the reorder buffer 10.
6 is registered as the old alias address in the entry of the store instruction 101 already reserved in the storage unit 6. After the registration is completed, one unused alias address is read from the release table 105 and registered as a new alias address in the alias address in the matching entry of the alias table 102 and the alias address of the store buffer 107.

The store value (VAL) of the instruction 101 is stored in an entry already allocated to the store buffer 107 after the value is determined. The store address of the instruction 101 is stored in the reorder buffer 106 after the value is determined.
Is stored in an entry assigned in advance. After all the preceding instructions have been completed, the store instruction 101 sends the address of the corresponding entry in the reorder buffer 106 and the store value of the corresponding entry in the store buffer 107 to the cache or main storage, thereby completing the processing. .

FIG. 2 is a functional diagram for explaining the operation of the block in FIG. 1, and the same parts as those in FIG. 1 are denoted by the same reference numerals. FIGS. 3 and 4 are flowcharts showing details of the operation of the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to these drawings.

First, the initial state of each unit will be described. In the alias table 102, all entries are undefined at the initial stage, and each time the address calculation of the store instruction is completed, additional registration to the entry is performed. In the release table 105, all entries are unused (FREE ADR ') at the initial stage.
When the instruction execution ends (the store instruction is removed from the reorder buffer 106), the state returns to the free state (FREE ADR ').

In the reorder buffer 106, all entries are initially undefined, and are additionally registered each time a store instruction is decoded. All entries of the store buffer 107 are also undefined at the initial stage, and are additionally registered each time the alias address (ADR ') and the value (VAL) of the store instruction are determined.

Referring to FIG. 3, there is shown a procedure of a method of renaming a memory address. First, when a store instruction 101 whose address is undetermined is issued (step S
1), reorder buffer 106 and store buffer 107
Each entry is allocated within. At this time, a number (ID) for identifying the store instruction is added to the entry in the reorder buffer 106 (step S2).
Since these entries are assigned at the time of decoding the instruction, for example, even in a superscalar processor which is executed in parallel in any order, the assignment is made in the program order.

When the undetermined address (ADR) of the instruction 101 is calculated and determined by the address adder 202 (steps S3 and S4), the same instruction identification number ID is detected by the reorder buffer 106 (the same ID is detected by the ID comparator 203). (Step S5), and is compared with the addresses of all valid entries in the alias table 102 (step S6).

As a result of this comparison, if a matching entry exists (step S7), the alias address (ADR ') of the entry is read, and the old alias address (OLD ADR) is stored in the entry in the reorder buffer 106.
(Step S8).

Thereafter, one unused alias address (FREE ADR ') is read from the release table 105 (step S10), the alias address of the corresponding entry of the alias address table 102 is replaced (step S11), and the store buffer is stored. 107 is stored as a new alias address (NEW ADR ') (step S1).
2). At this time, the store value of the store instruction 101 (VA
L) is stored in the relevant entry of the store buffer 107 after the instruction is issued.

If there is no matching entry in step S7, the address (ADR) of the instruction 101 is stored in the unused entry of the alias table 102 (step S8), and the subsequent operations are the same as in the case of the matching entry. The process proceeds to steps S10 to S12.

FIG. 4 is a flowchart showing a method of executing a memory access instruction based on the renaming process of FIG. When the processing of FIG. 3 is completed, and finally, all instructions preceding the store instruction 101 are completed and the store instruction 101 can be completed, the store address of the entry (the lowermost end) in the reorder buffer 106 and The store value of the entry (the lowermost end) of the store buffer 107 is derived (step S21) and sent to the cache or the main memory (step S22). Then, the old alias address of the entry in the reorder buffer 106 is registered in the release table 105 as an unused address (step S23).
With the above processing, the store instruction 101 is completed.

Here, for example, when the present invention is applied to a 32-bit microprocessor, the normal address length is 32 bits. In the conventional example of FIG. 5, since the store buffer 302 stores the 32-bit address ADR and the store value VAL, the amount of hardware increases as the number of entries increases.

On the other hand, in the present invention, the alias address ADR '
Is determined by the number of entries in the alias table 102. For example, assuming that the number of entries is 16, the length is 4 bits, and the number of entries is 32, the length is 5 bits. The capacity of 107 decreases. Conversely, even if the number of store instructions whose addresses can be renamed is increased, the increase in the amount of hardware is smaller than in the past, so that the number of simultaneous instructions issued can be increased.

Although not shown, the control operation according to the processing procedure shown in FIGS. 3 and 4 can be realized by reading out the recording program from a recording medium recorded as a program procedure in advance by a computer and executing the program. Is obvious.

The processor to which the present invention can be applied is a superscalar processor in the current technology, but will be
As the integration degree of SI is further improved, a plurality of
The present invention is similarly applicable to a processor mounted in an SI and executing a plurality of instructions in parallel.

[0038]

As described above, according to the present invention, an alias address having a shorter bit length is stored in the store buffer instead of storing the address itself specified by the store instruction in the store buffer. This has the effect that the amount of hardware can be reduced.

Further, there is an effect that the dependency between a plurality of load store instructions can be eliminated without increasing the amount of hardware of the store buffer. Therefore, even if there are many store instructions having a dependency on the same address, this can be easily resolved and a plurality of load store instructions can be executed in parallel. The reason is that by providing an alias table by separating the address renaming function from the store buffer, if the number of entries in the alias table is increased regardless of the number of entries in the store buffer, many aliases can be assigned to the same address. This is because addresses can be assigned.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the block in FIG. 1;

FIG. 3 is a flowchart showing an operation of the embodiment of the present invention, which is a procedure for explaining a method of renaming a memory address.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention, which is a procedure for explaining a method of executing a memory access instruction based on the renaming of the memory address in FIG. 3;

FIG. 5 is a block diagram showing an example of a conventional memory access method.

[Explanation of symbols]

 101 Instruction 102 Alias Table 103 Address Comparator 104 Match Entry Detector 105 Release Table 106 Reorder Buffer 107 Store Buffer 202 Address Adder

Claims (6)

[Claims] 1. A multiple memory access system in a processor having a plurality of load store processing units for executing load store processing in a memory in random order, wherein different short bit lengths are different for a plurality of store instructions for the same address. A multi-memory access system wherein the alias addresses are managed in association with each other. 2. An alias table having a plurality of entries for storing a set of a store address accessed by the store instruction and an alias address associated with the store address, and a corresponding alias provided corresponding to the alias address. An open table indicating whether the address has been used, a store buffer having a plurality of entries for storing a set of the latest alias address and a store value of the store instruction, and a set of an old alias address and a store address are stored. A reorder buffer having a plurality of entries, a store address of a store instruction determined after calculating the address is given to the alias table and the reorder buffer, respectively, and a store value of the store instruction is given to the store buffer. To the old alias address in the reorder buffer Means for giving an unused alias address of the release table to the alias table and the store buffer, respectively, and controlling the store value of the store buffer and the store address of the reorder buffer to be sent to the memory. 2. The multiple memory access system according to claim 1, wherein: 3. An alias table having a plurality of entries for storing a set of a store address accessed by a store instruction and an alias address associated with the store address, and a corresponding alias address provided corresponding to the alias address. Table that indicates whether or not is used, a store buffer having a plurality of entries for storing pairs of the latest alias address and the store value of the store instruction, and an entry for storing a pair of old alias addresses and store addresses And a reorder buffer having a plurality of reorder buffers, and a multiple memory access method in a processor having a plurality of load store processing units for executing load store processing to a memory in random order, wherein the reorder buffer is not decoded when the store instruction is decoded. Assign a use entry to make it a valid entry, Registering the store address determined by the dress calculation in the valid entry; and if there is an entry that matches the store address and the store address stored in all the valid entries of the alias table, Reading the alias address of the matching entry and registering it in the old alias address portion of the valid entry in the reorder buffer; acquiring an unused alias address from the release table to obtain the alias address portion of the matching entry in the alias table And registering in the latest alias address portion of the specific entry of the store buffer. When the store data of the store instruction is determined, the store data is stored in the store value portion of the entry of the store buffer. Storing in the And a multiple memory access method. 4. Accessing a memory using a store value stored in an entry of the store buffer in response to the store instruction and a store address stored in the reorder buffer, and then accessing the memory. 4. The method according to claim 3, further comprising the step of registering an old alias address as an unused alias address in the release table. 5. An alias table having a plurality of entries for storing a set of a store address accessed by a store instruction and an alias address associated with the store address, and a corresponding alias address provided corresponding to the alias address. Table that indicates whether or not is used, a store buffer having a plurality of entries for storing pairs of the latest alias address and the store value of the store instruction, and an entry for storing a pair of old alias addresses and store addresses A reorder buffer having a plurality of memory units, and a recording medium for recording a program for causing a computer to execute a multiple memory access method in a processor having a plurality of load store processing units for executing load store processing on a memory in random order. When decoding the store instruction, Allocating an unused entry in the order buffer as a valid entry, and registering the store address determined by address calculation in the valid entry; and a store address stored in the valid address of the store address and the alias table. Reading an alias address of the matching entry and registering the same in the old alias address portion of the valid entry in the reorder buffer; and obtaining an unused alias address from the release table. Registering in the alias address portion of the matching entry in the alias table and also registering the same in the latest alias address portion of the specific entry in the store buffer. Store data in the store Storing the program in a store value portion of the entry. 6. Accessing a memory using a store value stored in an entry of the store buffer and a store address stored in the reorder buffer in response to the store instruction, and then accessing the memory. 6. The recording medium according to claim 5, further comprising a step of registering an old alias address as an unused alias address in the release table.