JPH11166106A - Encapsulation material and semiconductor device of loc structure therewith - Google Patents
Encapsulation material and semiconductor device of loc structure therewithInfo
- Publication number
- JPH11166106A JPH11166106A JP10276338A JP27633898A JPH11166106A JP H11166106 A JPH11166106 A JP H11166106A JP 10276338 A JP10276338 A JP 10276338A JP 27633898 A JP27633898 A JP 27633898A JP H11166106 A JPH11166106 A JP H11166106A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- gap
- sealing material
- inner lead
- filler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Compositions Of Macromolecular Compounds (AREA)
- Epoxy Resins (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、充填材が原因で発
生するＬＯＣ構造の半導体装置のパッシベーション膜と
その下の拡散層損傷による電気特性不良がなく、且つ半
田耐熱性に優れた封止材及びそれを用いたＬＯＣ構造の
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sealing material which is free from defective electrical characteristics due to damage of a passivation film and a diffusion layer thereunder of a semiconductor device having a LOC structure caused by a filler, and which is excellent in solder heat resistance. And a semiconductor device having a LOC structure using the same.
【０００２】[0002]
【従来の技術】ＩＣ，ＬＳＩ等の半導体チップは、チッ
プの集積度の向上と共に、チップサイズの大型化、半導
体装置の小型化、薄型化が進んでいる。同時に半導体装
置を基板へ取り付ける時に、半導体装置自体が短時間の
内に２００℃以上の高温に晒されるようになってきた。
この時、封止材中に含まれる水分が気化し、ここで発生
する蒸気圧が封止材とチップ、リードフレーム等のイン
サートとの界面において、剥離応力として働き、封止材
とインサートとの間で剥離が発生し、特に薄型の半導体
装置においては、半導体装置のフクレやクラックに至っ
てしまうことになる。この様な剥離起因によるフクレ、
クラツクの防止策として、エポキシ樹脂及び硬化剤の低
粘度化（低分子化）、封止材とインサートとの接着カの
向上検討、あるいは無機充填材の形状を球形化して高充
填化を図り、吸水率の低減検討が行われている。また、
半導体装置の小型化及び半田耐熱性の向上のため、半導
体装置構造が従来のリードの上にチップを配置する構造
から図１に示すようなＬＯＣ（リードオンチップ）構造
に変わりつつある。この構造の半導体装置はインナーリ
ードの下側にＬＯＣテープと呼ばれる接着剤を介して半
導体チップを固着し、ワイヤーボンデングしたものを封
止材によりパッケージしたものでインナーリードと半導
体チップとの間にはＬＯＣテープの厚み分の隙間が空い
ている。しかし、従来の手法では、封止材の充填材の内
粗い粒子が、図２に示すように、チップとインナーリー
ドの間隙に挟まり、成形時の圧カ、成形収縮、半導体装
置を基板へ取り付ける時の熱応力等のストレスがチップ
に働き、パッシベーション膜の損傷及び酷い場合は拡散
層まで損傷し電気特性不良の原因となる。2. Description of the Related Art As semiconductor chips such as ICs and LSIs have been improved in chip integration, the chip size has been increased, and semiconductor devices have been reduced in size and thickness. At the same time, when attaching a semiconductor device to a substrate, the semiconductor device itself has been exposed to a high temperature of 200 ° C. or more within a short time.
At this time, the moisture contained in the sealing material is vaporized, and the vapor pressure generated here acts as a peeling stress at an interface between the sealing material and the insert such as a chip and a lead frame, and the gap between the sealing material and the insert. Separation occurs between them, and particularly in a thin semiconductor device, blistering or cracking of the semiconductor device may occur. Blisters caused by such peeling,
As measures to prevent cracking, lower the viscosity (lower molecular weight) of the epoxy resin and curing agent, consider improving the bonding power between the sealing material and the insert, or make the shape of the inorganic filler spherical to increase the filling. Studies are underway to reduce the water absorption. Also,
In order to reduce the size of the semiconductor device and improve the solder heat resistance, the semiconductor device structure is changing from a conventional structure in which a chip is arranged on a lead to a LOC (lead-on-chip) structure as shown in FIG. In a semiconductor device of this structure, a semiconductor chip is fixed to the lower side of an inner lead via an adhesive called a LOC tape, and a wire-bonded product is packaged with a sealing material. Has a gap corresponding to the thickness of the LOC tape. However, in the conventional method, the coarse particles in the filler of the sealing material are caught in the gap between the chip and the inner lead, as shown in FIG. 2, and the pressure during molding, the molding shrinkage, and the attachment of the semiconductor device to the substrate are performed. Stress such as thermal stress at the time acts on the chip, which damages the passivation film and, in severe cases, damages the diffusion layer and causes poor electrical characteristics.
【０００３】[0003]
【発明が解決しようとする課題】本発明は、かかる状況
に鑑みてなされたもので、充填材起因のバッシベーショ
ンとその下の拡散層損傷による電気特性不良がなく、且
つ半田耐熱性に優れた封止材及びそれを用いたＬＯＣ構
造の半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has no defective electrical characteristics due to a filler-induced basalization and a damage of a diffusion layer thereunder, and has excellent solder heat resistance. It is an object to provide a sealing material and a semiconductor device having a LOC structure using the same.
【０００４】[0004]
【課題を解決するための手段】すなわち本発明は、ＬＯ
Ｃ構造を有する半導体装置に用いられる封止材であっ
て、エポキシ樹脂、硬化剤、硬化促進剤及び無機充填材
からなり、インナーリードと半導体チップ間隙よりも小
粒径の無機充填材を８０〜９５重量％含有してなること
を特徴とする封止材及び該封止材により封止したＬＯＣ
構造の半導体装置に関する。That is, the present invention provides an LO
A sealing material used for a semiconductor device having a C structure, comprising an epoxy resin, a curing agent, a curing accelerator, and an inorganic filler, wherein an inorganic filler having a particle diameter smaller than the gap between the inner lead and the semiconductor chip is 80 to 80%. Sealing material characterized by containing 95% by weight and LOC sealed by the sealing material
The present invention relates to a semiconductor device having a structure.
【０００５】[0005]
【発明の実施の形態】本発明で用いられるエポキシ樹脂
としては、オルソクレゾールノボラツク型、ビフェニル
型、ジシクロ型、臭素化エポキシ樹脂等を単独又は併用
して用いることができるが、特にビフェニル型エポキシ
樹脂がインサートとの接着性が良いことから好適であ
る。硬化剤としては、フェノールノボラツク型、アラル
キル型、テルペン型等を単独又は併用して用いることが
できるが、特にアラルキル型がインサートとの接着性が
良好である。硬化促進剤としては、特に制限はなく、テ
トラフェニルホスホニウム−テトラフェニルボレート、
トリフェニルホスフィン、トリフェニルホスフィンとベ
ンゾキノンの付加物、１，８−ジアザービシクロ（５，
４，０）−ウンデセン−７，２−フェニル−４メチル−
イミダゾール、トリフェニルホスホニウム−トリフェニ
ルボラン等を単独又は併用して用いることができるが、
特にトリフェニルホスフィンとベンゾキノンの付加物
が、ボイドや充填性といった成形性の面から好適であ
る。カツプリング剤については、特に制限はなく、シラ
ンカツプリング剤を単独又は併用して用いることができ
るが、特にエポキシシランとアルキルシランとメルカプ
トシランの組み合わせが好適である。離型剤について
も、特に制限はないが、高級脂肪酸例えぱカルナバワッ
クス等とポリエチレン系ワックスを単独又は併用して用
いることができる。DETAILED DESCRIPTION OF THE INVENTION As the epoxy resin used in the present invention, orthocresol novolak type, biphenyl type, dicyclo type, brominated epoxy resin and the like can be used alone or in combination. Resin is preferred because it has good adhesion to the insert. As the curing agent, a phenol novolak type, an aralkyl type, a terpene type, or the like can be used alone or in combination. In particular, the aralkyl type has good adhesiveness to the insert. There is no particular limitation on the curing accelerator, and tetraphenylphosphonium-tetraphenylborate,
Triphenylphosphine, an adduct of triphenylphosphine and benzoquinone, 1,8-diazabicyclo (5,
(4,0) -undecene-7,2-phenyl-4methyl-
Imidazole, triphenylphosphonium-triphenylborane and the like can be used alone or in combination,
In particular, an adduct of triphenylphosphine and benzoquinone is preferred from the viewpoint of moldability such as voids and filling properties. The coupling agent is not particularly limited, and a silane coupling agent can be used alone or in combination, and a combination of epoxysilane, alkylsilane, and mercaptosilane is particularly preferable. There is no particular limitation on the release agent, but higher fatty acids such as carnauba wax and polyethylene wax can be used alone or in combination.
【０００６】無機充填材は、チップとインナーリードの
間隙を考慮してその粒径、形状を決める必要があり、イ
ンナーリードと半導体チップ間隙が７０μm以上の場合
はその値の９０％以下、好ましくは８０％以下、インナ
ーリードと半導体チップ間隙が７０μm未満の場合はそ
の値の９５％以下、好ましくは８５％以下とするのがよ
い。例えばインナーリードとチップとの接着に１００ミ
クロン厚のＬＯＣテープを用いる場合には、７５ミクロ
ンより上の粒子をカットした充填材を、又５０ミクロン
厚のＬＯＣテープを用いる場合には、４５ミクロンより
上の粒子をカットした充填材を使用する。更にその配合
量は封止材全体にたいし８０〜９５ｗｔ％配合する。配
合量が８０％未満では半田耐熱性が劣る。また９５％を
超えると流動性が極端に低下し成形が出来なくなる。充
填材形状はその５０％以上が球状であることが望まし
く、その材質としては、溶融シリカ、結晶シリカ、アル
ミナ等を単独及び併用して用いることができる。特に溶
融シリカ単独が好適である。その他の添加物として、着
色剤（カーボンブラツク等）、難燃助剤（三酸化アンチ
モン等）、改質剤（シリコーン、シリコーンゴム等）、
イオントラツパー（ハイドロタルサイト、アンチモンー
ビスマム等）を用いることができる。上記手段を用いて
製造した封止材は、充填材起因のパッシベーションとそ
の下の拡散層損傷による電気特性不良がなく、且つ半田
耐熱性を向上させることができる。封止材の製造方法と
しては特に制限はなく、通常行われているロール混練
法、ニーダー混練法等により混練した後冷却粉砕し、こ
のままあるいはタブレット化して使用に供される。It is necessary to determine the particle size and shape of the inorganic filler in consideration of the gap between the chip and the inner lead. When the gap between the inner lead and the semiconductor chip is 70 μm or more, 90% or less of the value, preferably 90% or less. When the gap between the inner lead and the semiconductor chip is less than 70 μm, the value is preferably 95% or less, more preferably 85% or less. For example, when a 100 micron thick LOC tape is used for bonding the inner lead and the chip, a filler material cut from particles above 75 microns is used. When a 50 micron thick LOC tape is used, 45 micron thick LOC tape is used. Use the filler with the above particles cut. Further, the compounding amount is 80 to 95% by weight based on the whole sealing material. If the amount is less than 80%, the solder heat resistance is inferior. On the other hand, if it exceeds 95%, the fluidity is extremely reduced and molding cannot be performed. It is preferable that 50% or more of the filler is spherical, and fused silica, crystalline silica, alumina or the like can be used alone or in combination. Particularly, fused silica alone is preferred. Other additives include a colorant (carbon black, etc.), a flame retardant aid (antimony trioxide, etc.), a modifier (silicone, silicone rubber, etc.),
An ion trapper (hydrotalcite, antimony-bismuth, or the like) can be used. The encapsulant manufactured by using the above-described means has no electrical characteristics failure due to passivation due to the filler and damage to the diffusion layer thereunder, and can improve solder heat resistance. The method for producing the sealing material is not particularly limited, and the material is kneaded by a usual roll kneading method, kneader kneading method or the like, then cooled and pulverized, and used as it is or in the form of tablets.
【０００７】[0007]
【実施例】以下に本発明の実施例について説明するが、
本発明はこれに限定されるものではない。 実施例１〜６ 比較例１〜９ まず、表１、２に示す各種の素材を予備混合（ドライブ
レンド）した後、二軸ロール（ロール表面温度約８０
℃）で１０分間混練し、冷却粉砕して製造した。この封
止材を用い、チップサイズが５．９ｘ１０．８ｍｍの半
導体チップを固着した４２アロイ材のリードフレームを
トランスファー成形機に装着し、金型温度１８０℃、成
形圧カ１００ｋｇｆ／ｃｍ2、硬化時間９０秒の条件で
成形を行った。その後、ポストキュアを１８０℃／５ｈ
行った。電気特性を直接測定できないので、パッシベー
ション膜の損傷を観察した。バッシベーション膜の損傷
の検査に用いた半導体装置は、２６ピンＳＯＪ及び２６
ピンＴＳＯＰのＬＯＣ構造の半導体装置である。チップ
表面には、パッシベーション膜（約５ミクロン）があ
り、ＬＯＣテープの厚さは、２６ピンＳＯＪの場合約１
００ミクロン、２６ピンＴＳＯＰの場合約５０ミクロン
を使用した。この様にして得られた樹脂封止型半導体装
置（ＬＯＣ構造）について、チップ上の封止材層を研磨
し、封止材層を僅かに残した状態で、熱濃硫酸に浸漬
し、パッシベーション膜の損傷を実体顕微鏡及び電子顕
微鏡により観察した。EXAMPLES Examples of the present invention will be described below.
The present invention is not limited to this. Examples 1 to 6 Comparative Examples 1 to 9 First, after premixing (dry blending) various materials shown in Tables 1 and 2, a biaxial roll (roll surface temperature of about 80) was obtained.
C.) for 10 minutes, and then cooled and pulverized to produce. Using this sealing material, a lead frame of 42 alloy material chip size is stuck to semiconductor chip 5.9x10.8mm mounted on transfer molding machine, a mold temperature of 180 ° C., forming pressures 100 kgf / cm 2, curing The molding was performed under the condition of a time of 90 seconds. Thereafter, the post cure is performed at 180 ° C. for 5 hours.
went. Since the electrical characteristics could not be measured directly, damage to the passivation film was observed. The semiconductor device used for the inspection of the damage of the passivation film includes 26-pin SOJ and 26-pin SOJ.
This is a semiconductor device having a LOC structure of a pin TSOP. There is a passivation film (about 5 microns) on the chip surface, and the thickness of the LOC tape is about 1 in the case of 26-pin SOJ.
For a 00 micron, 26 pin TSOP, about 50 microns was used. With respect to the resin-encapsulated semiconductor device (LOC structure) thus obtained, the encapsulant layer on the chip is polished and, while leaving the encapsulant layer slightly, immersed in hot concentrated sulfuric acid and passivated. The damage of the film was observed with a stereoscopic microscope and an electron microscope.
【０００８】半田耐熱性に用いた半導体装置は、８０ピ
ンＱＦＰの樹脂封止型半導体装置（外形寸法２０ｘ１４
ｘ２．０ｍｍ）であり、リードフレームは４２アロイ材
（加エなし）で８ｘ１０ｍｍのチップサイズを有するも
のである。この様にして得られた樹脂封止型半導体装置
について、半田耐熱性を以下に示す方法で測定した。１
２５℃／２４ｈべーキング後、８５℃／８５％ＲＨ４８
ｈ吸湿させた後、２４０℃／１０秒の熱処理を行なった
時の樹脂封止型半導体装置のクラック発生率を求めた。
上記の試験結果をまとめて表３に示す。The semiconductor device used for solder heat resistance is an 80-pin QFP resin-encapsulated semiconductor device (external dimensions 20 × 14).
x2.0 mm), and the lead frame is made of 42 alloy material (without heat) and has a chip size of 8 × 10 mm. The solder heat resistance of the resin-encapsulated semiconductor device thus obtained was measured by the following method. 1
After baking at 25 ° C / 24h, 85 ° C / 85% RH48
After moisture absorption, the crack generation rate of the resin-encapsulated semiconductor device when heat treatment was performed at 240 ° C. for 10 seconds was determined.
Table 3 summarizes the above test results.
【０００９】[0009]
【表１】 ビフェニル型エポキシ：油化シェルエポキシ（株）製 臭素化エポキシ：東都化成（株）製 アラルキル型フェノール：三井東圧化学（株）製 トリフェニルホスフィン付加物：北興化学（株）製[Table 1] Biphenyl type epoxy: Yuka Shell Epoxy Co., Ltd. Brominated epoxy: Toto Kasei Co., Ltd. Aralkyl type phenol: Mitsui Toatsu Chemicals Co., Ltd. Triphenylphosphine adduct: Hokuko Chemical Co., Ltd.
【００１０】[0010]
【表２】 [Table 2]
【００１１】[0011]
【表３】 [Table 3]
【００１２】表３に示す結果から明らかなように、イン
ナーリードと半導体チップとの間隙より小さい粒径の充
填材をもちい、かつ充填材の配合量を８０重量％以上と
した封止材を用いることにより耐熱性にすぐれ、電気特
性の良いＬＯＣ構造の半導体装置が得られる。As is evident from the results shown in Table 3, a sealing material which uses a filler having a particle size smaller than the gap between the inner lead and the semiconductor chip and has a compounding amount of the filler of 80% by weight or more is used. Accordingly, a semiconductor device having a LOC structure having excellent heat resistance and excellent electric characteristics can be obtained.
【００１３】[0013]
【発明の効果】本発明によれば、充填材起因のパッシベ
ーション膜とその下の拡散層損傷による電気特性不良が
なく、半田耐熱性を向上させることができる。According to the present invention, the heat resistance of the solder can be improved without the failure of the electrical characteristics due to the damage of the passivation film and the diffusion layer thereunder due to the filler.
【図１】ＬＯＣ構造の半導体装置の１例を示す断面図FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device having a LOC structure.
【図２】パッシベーション膜が破壊される様子を示す断
面図FIG. 2 is a cross-sectional view showing how a passivation film is broken.
１…半導体チップ ２…インナーリード ３…パッシベーション ４…ＬＯＣテープ ５…リードフレーム ６…金線 ７…角状フィラ ８…球状フィラ DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Inner lead 3 ... Passivation 4 ... LOC tape 5 ... Lead frame 6 ... Gold wire 7 ... Square filler 8 ... Spherical filler
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 23/50 (72)発明者 藤井 昌信 茨城県結城市大字鹿窪1772−１ 日立化成 工業株式会社下館工場内 (72)発明者 奈良 直紀 茨城県結城市大字鹿窪1772−１ 日立化成 工業株式会社下館工場内 (72)発明者 塚原 輝巳 茨城県結城市大字鹿窪1772−１ 日立化成 工業株式会社下館工場内 (72)発明者 酒井 裕行 茨城県結城市大字鹿窪1772−１ 日立化成 工業株式会社下館工場内──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. 6 Identification symbol FI H01L 23/50 (72) Inventor Masanobu Fujii 172-1, Kazukaku, Yuki-shi, Ibaraki Pref. Hitachi Chemical Industry Co., Ltd. Shimodate Plant (72) Invention Naoki Nara 1772-1 Okashikubo, Yuki-shi, Ibaraki Prefecture Inside Shimodate Plant, Hitachi Chemical Co., Ltd. (72) Inventor Terumi Tsukahara 172-1 Okakubo, Oki, Yukishi City, Ibaraki Prefecture Hiroyuki Ibaraki Pref.
Claims (6)
る封止材であって、エポキシ樹脂、硬化剤、硬化促進剤
及び無機充填材からなり、インナーリードと半導体チッ
プ間隙よりも小粒径の無機充填材を８０〜９５重量％含
有してなることを特徴とする封止材。1. A sealing material used for a semiconductor device having a LOC structure, comprising an epoxy resin, a hardening agent, a hardening accelerator, and an inorganic filler, and having a smaller particle size than a gap between an inner lead and a semiconductor chip. A sealing material comprising 80 to 95% by weight of a filler.
導体チップ間隙が７０μm以上の場合はその値の９０％
以下、インナーリードと半導体チップ間隙が７０μm未
満の場合はその値の９５％以下とした請求項１記載の封
止材。2. The particle size of the inorganic filler is 90% of the value when the gap between the inner lead and the semiconductor chip is 70 μm or more.
2. The sealing material according to claim 1, wherein when the gap between the inner lead and the semiconductor chip is less than 70 μm, the value is 95% or less of the value.
項１または２記載の封止材。3. The sealing material according to claim 1, wherein at least 50% of the inorganic filler is spherical.
剤がアラルキル型フェノール樹脂であるである請求項１
乃至３のいずれかに記載の封止材。4. The epoxy resin is of a biphenyl type, and the curing agent is an aralkyl type phenol resin.
4. The sealing material according to any one of claims 1 to 3.
ンゾキノンの付加物である請求項１乃至４のいずれかに
記載の封止材。5. The encapsulant according to claim 1, wherein the curing accelerator is an adduct of triphenylphosphine and benzoquinone.
により封止してなるＬＯＣ構造の半導体装置。6. A semiconductor device having a LOC structure, wherein the semiconductor device is sealed with the sealing material according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27633898A JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9-270678 | 1997-10-03 | ||
| JP27067897 | 1997-10-03 | ||
| JP27633898A JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11166106A true JPH11166106A (en) | 1999-06-22 |
| JP4062786B2 JP4062786B2 (en) | 2008-03-19 |
Family
ID=26549310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27633898A Expired - Lifetime JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4062786B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138673B2 (en) | 2002-08-19 | 2006-11-21 | Nec Electronics Corporation | Semiconductor package having encapsulated chip attached to a mounting plate |
-
1998
- 1998-09-30 JP JP27633898A patent/JP4062786B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138673B2 (en) | 2002-08-19 | 2006-11-21 | Nec Electronics Corporation | Semiconductor package having encapsulated chip attached to a mounting plate |
| US7449370B2 (en) | 2002-08-19 | 2008-11-11 | Nec Electronics Corporation | Production process for manufacturing such semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4062786B2 (en) | 2008-03-19 |
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