JP4062786B2 - SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME - Google Patents
SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME Download PDFInfo
- Publication number
- JP4062786B2 JP4062786B2 JP27633898A JP27633898A JP4062786B2 JP 4062786 B2 JP4062786 B2 JP 4062786B2 JP 27633898 A JP27633898 A JP 27633898A JP 27633898 A JP27633898 A JP 27633898A JP 4062786 B2 JP4062786 B2 JP 4062786B2
- Authority
- JP
- Japan
- Prior art keywords
- sealing material
- semiconductor device
- inner lead
- chip
- loc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Landscapes
- Compositions Of Macromolecular Compounds (AREA)
- Epoxy Resins (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、充填材が原因で発生するＬＯＣ構造の半導体装置のパッシベーション膜とその下の拡散層損傷による電気特性不良がなく、且つ半田耐熱性に優れた封止材及びそれを用いたＬＯＣ構造の半導体装置に関する。
【０００２】
【従来の技術】
ＩＣ，ＬＳＩ等の半導体チップは、チップの集積度の向上と共に、チップサイズの大型化、半導体装置の小型化、薄型化が進んでいる。同時に半導体装置を基板へ取り付ける時に、半導体装置自体が短時間の内に２００℃以上の高温に晒されるようになってきた。この時、封止材中に含まれる水分が気化し、ここで発生する蒸気圧が封止材とチップ、リードフレーム等のインサートとの界面において、剥離応力として働き、封止材とインサートとの間で剥離が発生し、特に薄型の半導体装置においては、半導体装置のフクレやクラックに至ってしまうことになる。
この様な剥離起因によるフクレ、クラツクの防止策として、エポキシ樹脂及び硬化剤の低粘度化（低分子化）、封止材とインサートとの接着カの向上検討、あるいは無機充填材の形状を球形化して高充填化を図り、吸水率の低減検討が行われている。また、半導体装置の小型化及び半田耐熱性の向上のため、半導体装置構造が従来のリードの上にチップを配置する構造から図１に示すようなＬＯＣ（リードオンチップ）構造に変わりつつある。
この構造の半導体装置はインナーリードの下側にＬＯＣテープと呼ばれる接着剤を介して半導体チップを固着し、ワイヤーボンデングしたものを封止材によりパッケージしたものでインナーリードと半導体チップとの間にはＬＯＣテープの厚み分の隙間が空いている。
しかし、従来の手法では、封止材の充填材の内粗い粒子が、図２に示すように、チップとインナーリードの間隙に挟まり、成形時の圧カ、成形収縮、半導体装置を基板へ取り付ける時の熱応力等のストレスがチップに働き、パッシベーション膜の損傷及び酷い場合は拡散層まで損傷し電気特性不良の原因となる。
【０００３】
【発明が解決しようとする課題】
本発明は、かかる状況に鑑みてなされたもので、充填材起因のバッシベーションとその下の拡散層損傷による電気特性不良がなく、且つ半田耐熱性に優れた封止材及びそれを用いたＬＯＣ構造の半導体装置を提供することを目的とする。
【０００４】
【課題を解決するための手段】
すなわち本発明は、ＬＯＣ構造を有する半導体装置に用いられる封止材であって、エポキシ樹脂、硬化剤、硬化促進剤及び無機充填材からなり、インナーリードと半導体チップ間隙よりも小粒径の無機充填材を８０〜９５重量％含有してなることを特徴とする封止材及び該封止材により封止したＬＯＣ構造の半導体装置に関する。
【０００５】
【発明の実施の形態】
本発明で用いられるエポキシ樹脂としては、オルソクレゾールノボラツク型、ビフェニル型、ジシクロ型、臭素化エポキシ樹脂等を単独又は併用して用いることができるが、特にビフェニル型エポキシ樹脂がインサートとの接着性が良いことから好適である。
硬化剤としては、フェノールノボラツク型、アラルキル型、テルペン型等を単独又は併用して用いることができるが、特にアラルキル型がインサートとの接着性が良好である。
硬化促進剤としては、特に制限はなく、テトラフェニルホスホニウム−テトラフェニルボレート、トリフェニルホスフィン、トリフェニルホスフィンとベンゾキノンの付加物、１，８−ジアザービシクロ（５，４，０）−ウンデセン−７，２−フェニル−４メチル−イミダゾール、トリフェニルホスホニウム−トリフェニルボラン等を単独又は併用して用いることができるが、特にトリフェニルホスフィンとベンゾキノンの付加物が、ボイドや充填性といった成形性の面から好適である。
カツプリング剤については、特に制限はなく、シランカツプリング剤を単独又は併用して用いることができるが、特にエポキシシランとアルキルシランとメルカプトシランの組み合わせが好適である。
離型剤についても、特に制限はないが、高級脂肪酸例えぱカルナバワックス等とポリエチレン系ワックスを単独又は併用して用いることができる。
【０００６】
無機充填材は、チップとインナーリードの間隙を考慮してその粒径、形状を決める必要があり、インナーリードと半導体チップ間隙が７０μm以上の場合はその値の９０％以下、好ましくは８０％以下、インナーリードと半導体チップ間隙が７０μm未満の場合はその値の９５％以下、好ましくは８５％以下とするのがよい。例えばインナーリードとチップとの接着に１００ミクロン厚のＬＯＣテープを用いる場合には、７５ミクロンより上の粒子をカットした充填材を、又５０ミクロン厚のＬＯＣテープを用いる場合には、４５ミクロンより上の粒子をカットした充填材を使用する。更にその配合量は封止材全体にたいし８０〜９５ｗｔ％配合する。配合量が８０％未満では半田耐熱性が劣る。また９５％を超えると流動性が極端に低下し成形が出来なくなる。
充填材形状はその５０％以上が球状であることが望ましく、その材質としては、溶融シリカ、結晶シリカ、アルミナ等を単独及び併用して用いることができる。特に溶融シリカ単独が好適である。
その他の添加物として、着色剤（カーボンブラツク等）、難燃助剤（三酸化アンチモン等）、改質剤（シリコーン、シリコーンゴム等）、イオントラツパー（ハイドロタルサイト、アンチモンービスマム等）を用いることができる。
上記手段を用いて製造した封止材は、充填材起因のパッシベーションとその下の拡散層損傷による電気特性不良がなく、且つ半田耐熱性を向上させることができる。
封止材の製造方法としては特に制限はなく、通常行われているロール混練法、ニーダー混練法等により混練した後冷却粉砕し、このままあるいはタブレット化して使用に供される。
【０００７】
【実施例】
以下に本発明の実施例について説明するが、本発明はこれに限定されるものではない。
実施例１〜６ 比較例１〜９
まず、表１、２に示す各種の素材を予備混合（ドライブレンド）した後、二軸ロール（ロール表面温度約８０℃）で１０分間混練し、冷却粉砕して製造した。
この封止材を用い、チップサイズが５．９ｘ１０．８ｍｍの半導体チップを固着した４２アロイ材のリードフレームをトランスファー成形機に装着し、金型温度１８０℃、成形圧カ１００ｋｇｆ／ｃｍ2、硬化時間９０秒の条件で成形を行った。その後、ポストキュアを１８０℃／５ｈ行った。
電気特性を直接測定できないので、パッシベーション膜の損傷を観察した。バッシベーション膜の損傷の検査に用いた半導体装置は、２６ピンＳＯＪ及び２６ピンＴＳＯＰのＬＯＣ構造の半導体装置である。
チップ表面には、パッシベーション膜（約５ミクロン）があり、ＬＯＣテープの厚さは、２６ピンＳＯＪの場合約１００ミクロン、２６ピンＴＳＯＰの場合約５０ミクロンを使用した。
この様にして得られた樹脂封止型半導体装置（ＬＯＣ構造）について、チップ上の封止材層を研磨し、封止材層を僅かに残した状態で、熱濃硫酸に浸漬し、パッシベーション膜の損傷を実体顕微鏡及び電子顕微鏡により観察した。
【０００８】
半田耐熱性に用いた半導体装置は、８０ピンＱＦＰの樹脂封止型半導体装置（外形寸法２０ｘ１４ｘ２．０ｍｍ）であり、リードフレームは４２アロイ材（加エなし）で８ｘ１０ｍｍのチップサイズを有するものである。
この様にして得られた樹脂封止型半導体装置について、半田耐熱性を以下に示す方法で測定した。１２５℃／２４ｈべーキング後、８５℃／８５％ＲＨ４８ｈ吸湿させた後、２４０℃／１０秒の熱処理を行なった時の樹脂封止型半導体装置のクラック発生率を求めた。上記の試験結果をまとめて表３に示す。
【０００９】
【表１】
臭素化エポキシ：東都化成（株）製
アラルキル型フェノール：三井東圧化学（株）製
トリフェニルホスフィン付加物：北興化学（株）製
【００１０】
【表２】
【表３】
表３に示す結果から明らかなように、インナーリードと半導体チップとの間隙より小さい粒径の充填材をもちい、かつ充填材の配合量を８０重量％以上とした封止材を用いることにより耐熱性にすぐれ、電気特性の良いＬＯＣ構造の半導体装置が得られる。
【００１３】
【発明の効果】
本発明によれば、充填材起因のパッシベーション膜とその下の拡散層損傷による電気特性不良がなく、半田耐熱性を向上させることができる。
【図面の簡単な説明】
【図１】ＬＯＣ構造の半導体装置の１例を示す断面図
【図２】パッシベーション膜が破壊される様子を示す断面図
【符号の説明】
１…半導体チップ ２…インナーリード
３…パッシベーション ４…ＬＯＣテープ
５…リードフレーム ６…金線
７…角状フィラ ８…球状フィラ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sealing material excellent in soldering heat resistance, having no electrical characteristic failure due to damage to a passivation film and a diffusion layer under the passivation film of a LOC structure generated due to a filler, and a LOC structure using the same The present invention relates to a semiconductor device.
[0002]
[Prior art]
Semiconductor chips such as ICs and LSIs have been increasing in chip integration, chip sizes, semiconductor devices have been made smaller and thinner. At the same time, when the semiconductor device is attached to the substrate, the semiconductor device itself has been exposed to a high temperature of 200 ° C. or more in a short time. At this time, moisture contained in the sealing material is vaporized, and the vapor pressure generated here acts as a peeling stress at the interface between the sealing material and the insert such as the chip and the lead frame. Separation occurs, and particularly in a thin semiconductor device, blisters and cracks of the semiconductor device are reached.
In order to prevent blisters and cracks due to such peeling, the viscosity of the epoxy resin and the curing agent (low molecular weight), the improvement of the adhesion between the sealant and the insert, or the shape of the inorganic filler is spherical. The reduction of water absorption rate is being studied for higher packing. Further, in order to reduce the size of the semiconductor device and improve the soldering heat resistance, the semiconductor device structure is changing from a conventional structure in which a chip is disposed on a lead to a LOC (lead on chip) structure as shown in FIG.
In the semiconductor device having this structure, a semiconductor chip is fixed to an underside of an inner lead via an adhesive called a LOC tape, and a wire bonded product is packaged by a sealing material, and is interposed between the inner lead and the semiconductor chip. Has a gap corresponding to the thickness of the LOC tape.
However, in the conventional method, as shown in FIG. 2, the coarse particles in the filler of the sealing material are sandwiched between the chip and the inner lead, and the pressure during molding, molding shrinkage, and the semiconductor device are attached to the substrate. Stress, such as thermal stress, acts on the chip, and when the passivation film is damaged or severe, even the diffusion layer is damaged, resulting in poor electrical characteristics.
[0003]
[Problems to be solved by the invention]
The present invention has been made in view of such a situation, and there is no electrical characteristic failure due to passivation caused by filler and damage to the diffusion layer below, and a sealing material excellent in solder heat resistance and a LOC using the same. An object is to provide a semiconductor device having a structure.
[0004]
[Means for Solving the Problems]
That is, the present invention is a sealing material used for a semiconductor device having a LOC structure, which is composed of an epoxy resin, a curing agent, a curing accelerator, and an inorganic filler, and has an inorganic particle size smaller than that between the inner lead and the semiconductor chip gap. The present invention relates to a sealing material containing 80 to 95% by weight of a filler, and a LOC structure semiconductor device sealed with the sealing material.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
As the epoxy resin used in the present invention, orthocresol novolak type, biphenyl type, dicyclo type, brominated epoxy resin and the like can be used alone or in combination, but in particular, the biphenyl type epoxy resin has adhesiveness to the insert. Is preferable because it is good.
As the curing agent, a phenol novolak type, an aralkyl type, a terpene type or the like can be used alone or in combination, but the aralkyl type has particularly good adhesion to the insert.
The curing accelerator is not particularly limited and includes tetraphenylphosphonium-tetraphenylborate, triphenylphosphine, an adduct of triphenylphosphine and benzoquinone, 1,8-diazabicyclo (5,4,0) -undecene-7. , 2-phenyl-4methyl-imidazole, triphenylphosphonium-triphenylborane, etc. can be used alone or in combination, but in particular, the adduct of triphenylphosphine and benzoquinone has moldability such as voids and fillability. To preferred.
The coupling agent is not particularly limited, and the silane coupling agent can be used alone or in combination, but a combination of epoxy silane, alkyl silane and mercapto silane is particularly suitable.
The release agent is not particularly limited, and higher fatty acids such as carnauba wax and polyethylene wax can be used alone or in combination.
[0006]
The particle size and shape of the inorganic filler must be determined in consideration of the gap between the chip and the inner lead. When the gap between the inner lead and the semiconductor chip is 70 μm or more, it is 90% or less, preferably 80% or less. When the gap between the inner lead and the semiconductor chip is less than 70 μm, the value is 95% or less, preferably 85% or less. For example, when using a LOC tape with a thickness of 100 microns for bonding the inner lead and the chip, use a filler cut from particles above 75 microns, and when using a LOC tape with a thickness of 50 microns, start with 45 microns. Use a filler cut from the top particles. Furthermore, the compounding quantity mix | blends 80-95 wt% with respect to the whole sealing material. If the blending amount is less than 80%, the solder heat resistance is poor. On the other hand, if it exceeds 95%, the fluidity is drastically lowered and molding becomes impossible.
As for the shape of the filler, it is desirable that 50% or more thereof is spherical, and as the material, fused silica, crystalline silica, alumina or the like can be used alone or in combination. In particular, fused silica alone is preferred.
Other additives include colorants (such as carbon black), flame retardant aids (such as antimony trioxide), modifiers (such as silicone and silicone rubber), and ion trappers (such as hydrotalcite and antimony-bismum). Can be used.
The sealing material manufactured using the above means does not have a defective electrical characteristic due to passivation caused by the filler and damage to the diffusion layer thereunder, and can improve solder heat resistance.
There is no restriction | limiting in particular as a manufacturing method of a sealing material, It knead | mixes by the roll kneading method, the kneader kneading method, etc. which are normally performed, Then, it cools and grind | pulverizes, It uses for it as it is or tableted.
[0007]
【Example】
Examples of the present invention will be described below, but the present invention is not limited thereto.
Examples 1-6 Comparative Examples 1-9
First, various materials shown in Tables 1 and 2 were premixed (dry blended), then kneaded with a biaxial roll (roll surface temperature of about 80 ° C.) for 10 minutes, cooled and pulverized.
Using this sealing material, a 42 alloy lead frame to which a semiconductor chip having a chip size of 5.9 × 10.8 mm is fixed is mounted on a transfer molding machine, the mold temperature is 180 ° C., the molding pressure is 100 kgf / cm 2 , and the curing is performed. Molding was performed under conditions of a time of 90 seconds. Thereafter, post-curing was performed at 180 ° C. for 5 hours.
Since the electrical characteristics could not be measured directly, damage to the passivation film was observed. The semiconductor device used for the inspection of the damage to the passivation film is a 26-pin SOJ and 26-pin TSOP LOC semiconductor device.
The chip surface had a passivation film (about 5 microns), and the thickness of the LOC tape was about 100 microns for 26-pin SOJ and about 50 microns for 26-pin TSOP.
With respect to the resin-encapsulated semiconductor device (LOC structure) thus obtained, the encapsulant layer on the chip is polished and immersed in hot concentrated sulfuric acid in a state where the encapsulant layer is left slightly, and passivation is performed. The damage of the film was observed with a stereoscopic microscope and an electron microscope.
[0008]
The semiconductor device used for soldering heat resistance is an 80-pin QFP resin-encapsulated semiconductor device (outer dimensions 20 × 14 × 2.0 mm), and the lead frame is 42 alloy material (without heat treatment) and has a chip size of 8 × 10 mm. is there.
The resin-sealed semiconductor device thus obtained was measured for solder heat resistance by the following method. After baking at 125 ° C./24 h, after absorbing moisture at 85 ° C./85% RH for 48 h, the crack generation rate of the resin-encapsulated semiconductor device when heat treatment at 240 ° C./10 seconds was performed. The test results are summarized in Table 3.
[0009]
[Table 1]
[Table 2]
[Table 3]
As is apparent from the results shown in Table 3, heat resistance is obtained by using a sealing material having a particle size smaller than the gap between the inner lead and the semiconductor chip and using a filler content of 80% by weight or more. A semiconductor device having an excellent LOC structure with excellent electrical characteristics can be obtained.
[0013]
【The invention's effect】
According to the present invention, there is no electrical characteristic defect due to damage to the passivation film caused by the filler and the underlying diffusion layer, and the solder heat resistance can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a LOC structure. FIG. 2 is a cross-sectional view showing a state where a passivation film is destroyed.
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Inner lead 3 ...
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27633898A JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9-270678 | 1997-10-03 | ||
| JP27067897 | 1997-10-03 | ||
| JP27633898A JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11166106A JPH11166106A (en) | 1999-06-22 |
| JP4062786B2 true JP4062786B2 (en) | 2008-03-19 |
Family
ID=26549310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27633898A Expired - Lifetime JP4062786B2 (en) | 1997-10-03 | 1998-09-30 | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4062786B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004079760A (en) | 2002-08-19 | 2004-03-11 | Nec Electronics Corp | Semiconductor device and its assembling method |
-
1998
- 1998-09-30 JP JP27633898A patent/JP4062786B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11166106A (en) | 1999-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH10292094A (en) | Epoxy resin composition, resin-sealed semiconductor device prepared by using the sane, epoxy resin molding material, and composite epoxy resin tablet | |
| JP3603483B2 (en) | Semiconductor element sealing material and semiconductor device using the same | |
| JP4062786B2 (en) | SEALING MATERIAL AND LOC STRUCTURE SEMICONDUCTOR DEVICE USING SAME | |
| JP3589694B2 (en) | Resin encapsulated semiconductor device and epoxy resin encapsulant used therefor | |
| US6211277B1 (en) | Encapsulating material and LOC structure semiconductor device using the same | |
| JPH0839549A (en) | Tablet for sealing semiconductor | |
| JP2000103938A (en) | Epoxy resin composition for sealing and semiconductor device | |
| JP4332972B2 (en) | Epoxy resin composition and semiconductor device | |
| JP3473640B2 (en) | Resin encapsulated semiconductor device and epoxy resin encapsulant used therefor | |
| JP4770024B2 (en) | Epoxy resin composition and semiconductor device | |
| JP4524832B2 (en) | Epoxy resin composition and semiconductor device | |
| JP3591377B2 (en) | Epoxy resin composition and semiconductor device | |
| JPH11147937A (en) | Epoxy resin composition and semiconductor device | |
| JP3449242B2 (en) | Epoxy resin composition and semiconductor device | |
| JP2002194058A (en) | Semiconductor device | |
| JPH0588904B2 (en) | ||
| JP2001233931A (en) | Epoxy resin composition for sealing and semiconductor device | |
| JP6562092B2 (en) | Epoxy resin composition for electronic component sealing and electronic component device using the same | |
| JP2004018798A (en) | Epoxy resin composition and semiconductor device | |
| JP4608736B2 (en) | Method for producing epoxy resin composition for semiconductor encapsulation | |
| JP2000186183A (en) | Epoxy resin composition for sealing and semiconductor device | |
| JP3093051B2 (en) | Epoxy resin composition | |
| JP3377911B2 (en) | Epoxy resin composition | |
| JP4379972B2 (en) | Epoxy resin composition and semiconductor device | |
| JPH06326220A (en) | Resin-sealed semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050926 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070820 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070919 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071116 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20071116 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071211 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20071224 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110111 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110111 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120111 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130111 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130111 Year of fee payment: 5 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140111 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |