JPH11163332A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a diffused layer in a shape such that an electric field can be relaxed at a gate end and an element-isolation region end. SOLUTION: In a semiconductor storage device 1, in which the diffused layers 23, 24 of an insulated gate type transistor are formed in the element forming region 13 of a semiconductor substrate 11 isolated by element-isolation regions 12, the diffused layers 23, 24 are formed to the semiconductor substrate 11 on both sides of a gate electrode 22, joint surfaces with the semiconductor substrate 11 are formed in an approximately projected curved surface shape having a radius of curvature rig larger than junction depth xj in shallow junctions on the gate electrode 22 sides on one sides of each diffused layer 23, 24, and joint surfaces with the semiconductor substrate 11 are formed in the approximately projecting curved surface shape, having a radius of curvature rji larger than junction depth xj under the state, in which the other sides of each diffusion layer 23, 24 are brought into contact with the side sections of the element-isolation regions 12, on the other sides of each diffused layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device characterized by a junction interface of a diffusion layer of a transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the data retention characteristics of a DRAM, it is important to suppress a leakage current such as a parasitic leak, a weak avalanche, a subthreshold leak, a gate oxide film leak, etc. It is most important to reduce leakage. These leak currents are caused by oxygen precipitation, residual defects due to ion implantation, minute defects such as stress, crystal defects of the silicon substrate at the LOCOS oxide film interface, and dislocations in the silicon substrate.

FIG. 5 shows a memory cell 201 of a DRAM. That is, the gate electrode 21 is formed on the element forming region 103 separated by the LOCOS oxide film 102 formed on the semiconductor substrate 101 via the gate insulating film 211.
2 is formed, and the diffusion layers 213 and 214 are formed on the semiconductor substrate 101 on both sides of the gate electrode 212. The diffusion layers 213 and 214 have a spherical (spherical) junction interface, and the diffusion layer portions 213G and 214 at the corners of the gate having a small radius of curvature.
G and diffusion layer portion 213 at the corner of LOCOS oxide film 102
The relaxation of the electric field at L and 214L is an important point for improving the data retention characteristics of the DRAM.

[0004]

The factors that determine the junction leakage in the past were diffusion current and generation and recombination current.
When the cell size is reduced and the junction depth Xj of the diffusion layers 213 and 214 becomes shallow as shown in FIG. 6, the junction surfaces 213L and 214L on the element isolation region 102 side are reduced.
Radius of curvature rj _l and the junction surface 213 on the gate electrode 212 side.
The radius of curvature rj _g of G, 214G decreases, and the electric field increases. Such an increase in the electric field increases the generation and recombination current [IEDM (Internatinal Electron Device).
s Meeting) (USA), 14.1 (1990) Steven H. Voldman, Jeff
rey B. Johnson, Thomas D. Linton, Stephen L. Titcomb, p.
349-352], and a local avalanche multiplication (avalanche multiplication) causes an increase in junction leak current and a decrease in DRAM data retention characteristics. Therefore, this is a major obstacle to increasing the integration of the DRAM.

[0005]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor memory device and a method of manufacturing the same which have been made to solve the above problems.

The semiconductor memory device is a semiconductor memory device in which a diffusion layer of an insulated gate transistor is formed in an element formation region provided in the semiconductor substrate and separated by an element isolation region formed in the semiconductor substrate. Diffusion layers are formed on the semiconductor substrate on both sides of the gate electrode of the insulated gate transistor. One side of each diffusion layer has a shallow junction on the gate electrode side, and the junction surface with the semiconductor substrate has a curvature larger than the junction depth. It is formed in a substantially convex curved surface shape having a radius, the other side of each diffusion layer is in a state of contacting the side portion of the element isolation region, and the bonding surface with the semiconductor substrate has a substantially convex radius of curvature larger than the bonding depth. It is characterized by being formed in a curved shape.

In the semiconductor memory device, one side of each diffusion layer is formed with a shallow junction on the gate electrode side, and a junction surface with the semiconductor substrate is formed in a substantially convex curved shape having a radius of curvature larger than the junction depth. The other side of each diffusion layer is formed so as to be in contact with the side of the element isolation region, and the bonding surface with the semiconductor substrate is formed in a substantially convex curved shape having a radius of curvature larger than the bonding depth. , The electric field in those portions is reduced. As a result, the junction leakage current is reduced.

In a first method of manufacturing a semiconductor memory device, a gate electrode is formed via a gate insulating film in an element formation region provided in a semiconductor substrate, which is separated by an element isolation region formed in the semiconductor substrate. . Next, an impurity for forming a diffusion layer is introduced into the element formation region by a first oblique ion implantation method using the gate electrode and the element isolation region as masks. Subsequently, after forming a sidewall insulating film on the side wall of the gate electrode, a diffusion layer is formed in the element forming region by a second oblique ion implantation method using the gate electrode, the sidewall insulating film, and the element isolation region as a mask. For introducing impurities.

In the first method of manufacturing a semiconductor memory device, an impurity for forming a diffusion layer in an element formation region is introduced by a first oblique ion implantation method using a gate electrode and an element isolation region as a mask. . Subsequently, after forming a sidewall insulating film on the side wall of the gate electrode, a diffusion layer is formed in the element forming region by a second oblique ion implantation method using the gate electrode, the sidewall insulating film, and the element isolation region as a mask. The diffusion layer is formed to have a shallow junction on the gate electrode side and a substantially convex curved surface having a radius of curvature larger than the junction depth, and a further isolation region. In the state of contact with the side portion, the bonding surface with the semiconductor substrate is formed in a substantially convex curved shape having a radius of curvature larger than the bonding depth.

In a second method of manufacturing a semiconductor memory device, a gate electrode is separated via a gate insulating film into an element formation region provided on the semiconductor substrate and separated by an element isolation region formed on the semiconductor substrate. Form. Next, an impurity for forming a diffusion layer is introduced into the element formation region by oblique ion implantation using the gate electrode and the element isolation region as a mask. Subsequently, a silicon oxide film is formed on the semiconductor substrate so as to cover the gate electrode and the element isolation region. Then, the gate electrode, the silicon oxide film formed on the side wall of the gate electrode and the ion using the element isolation region as a mask are formed. By the implantation method, an impurity for forming a diffusion layer in the element formation region is introduced in a state deeper than the introduction depth of the impurity introduced by the previously performed oblique ion implantation.
Then, after forming a sidewall on the side wall of the gate electrode, the gate electrode, the silicon oxide film formed on the side wall of the gate electrode, the sidewall, and the ion implantation method using the element isolation region as a mask are used to perform the ion implantation. An impurity for forming a diffusion layer in an element formation region is introduced in a state deeper than the introduced depth of the introduced impurity.

In the second method of manufacturing a semiconductor memory device, after a gate electrode is formed, a silicon oxide film formed on a side wall of the gate electrode is formed, and then a sidewall is formed, and then ion implantation is performed sequentially. As a result, since the impurity is introduced deeper than the introduction depth of the ion implantation performed earlier, the diffusion layer has a shallow junction on the gate electrode side, and the junction surface with the semiconductor substrate has a radius of curvature larger than the junction depth. The junction surface with the semiconductor substrate is formed in a substantially convex curved shape having a radius of curvature larger than the junction depth in a state of being formed in a substantially convex curved shape and further in contact with a side portion of the element isolation region.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described with reference to FIG. In FIG.
(1) shows a schematic sectional view, and (2) shows a layout diagram.

As shown in FIG. 1, a semiconductor memory device 1 comprising an insulated gate transistor is separated by an element isolation region 12 formed in a semiconductor substrate (for example, a silicon substrate) 11 and provided on the semiconductor substrate 11. Formed in the formed element forming region 13. A gate electrode 22 is formed on the element forming region 13 with a gate insulating film 21 interposed therebetween. The gate electrode 22 is made of, for example, doped polysilicon and may have an offset insulating film (not shown) formed thereon or a metal silicide layer formed thereon. Good.

Diffusion layers 23 and 24 are formed on the surface of the semiconductor substrate 11 on both sides of the gate electrode 22. On one side of each of the diffusion layers 23 and 24, is formed in a shallow junction to the gate electrode 22 side, the junction surface of the semiconductor substrate 11 is substantially convex curved shape having a large radius of curvature rj _g than the junction depth Xj ( For example, it is formed in a substantially spherical shape. The other side of each of the diffusion layers 23 and 24 is connected to the element isolation region 12.
The semiconductor substrate 11 is formed so as to be in contact with the side of
Has a radius of curvature rj _l greater than the junction depth Xj.
A substantially convex curved surface (for example, a substantially spherical shape) having
It is formed so as to include a crystal defect region generated in the semiconductor substrate 11 near the side of the element isolation region 12 during the OS oxidation.

Next, the relationship between the junction leak current and the radius of curvature rj of the diffusion layer will be described with reference to FIG. In the figure, the vertical axis indicates the junction leak current, and the horizontal axis indicates the radius of curvature of the diffusion layer. The temperature shown in the figure is the operating temperature of the diffusion layer.

As shown in FIG. 2, the junction depth of the diffusion layer is 0.65 μm. As the radius of curvature rj of the diffusion layer increases, the junction leakage current decreases at any operating temperature. It can be seen that the junction leakage current becomes smaller as the depth becomes larger than the depth Xj. Therefore, as described above, it is preferable that the curvature radii rj _g and rj _l of the diffusion layers 23 and 24 be larger than the junction depth Xj.

In the semiconductor memory device 1, each diffusion layer 2
One side of the 3,24 are formed by a shallow junction to the gate electrode 22 side, the junction surface of the semiconductor substrate 11 is formed in a substantially convex curved shape having a large radius of curvature rj _g than the junction depth Xj, each spreading The other side of the layers 23 and 24 is
It is formed in a state in contact with the side, since it is formed in a substantially convex curved shape having a large radius of curvature rj _l than the junction surface junction depth Xj of the semiconductor substrate 11, the electric field in those parts Is alleviated. As a result, the junction leakage current is reduced. Moreover, the diffusion layers 23 and 24 are LOCOS
During oxidation, the semiconductor substrate 1 near the side of the element isolation region 12
1 is formed so as to include a crystal defect region occurring in the first region. Therefore, the depletion layer does not extend to the crystal defect region. As described above, this transistor is replaced with the dynamic RA
When used as an M (hereinafter referred to as DRAM) memory transistor, data retention characteristics of the DRAM can be improved.

Next, a first example of the semiconductor memory device according to the present invention will be described.
An example of the manufacturing method will be described as a first embodiment with reference to a manufacturing process diagram in FIG. In FIG. 3, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, an element isolation region 12 is formed in a semiconductor substrate (for example, a silicon substrate) 11 by an ordinary element isolation formation technique (for example, a LOCOS method), and an element formation region 13 is provided. . Next, a gate electrode 22 is formed on the element formation region 13 with a gate insulating film 21 interposed therebetween by a normal gate formation technique. For example, deposition after forming the gate insulating film 21 on the surface of the element formation region 13, doped polycrystalline silicon film, a tungsten silicide (WSi _x) layer CVD (chemical vapor deposition) to a thickness of several hundred nm the method After that, these films are patterned by a lithography technique and an etching technique to form a gate electrode 22. Since FIG. 3 shows a memory cell of a DRAM, a word line 51 having an extended gate electrode is formed on the element isolation region 12.

Next, an impurity for forming a diffusion layer is introduced into the semiconductor substrate 11 in the element formation region 13 by a first oblique ion implantation method using the gate electrode 22 and the element isolation region 12 as a mask. The first oblique ion implantation is performed, for example, within a range of more than 45 ° and 75 ° or less, for example, 60 ° with respect to the normal direction of the semiconductor substrate surface 11A.
Ions are introduced at an angle of. At this time, the direction of the first oblique ion implantation is such that the gate length direction of the gate electrode 22 is 0 °, 25 ° to 65 °, 115 ° to 155 °, 205 ° to 245 °, and 295 ° ~ 33
4 orientations in the range of 5 °, for example 45 °, 135 °, 225
It is desirable to introduce ions from four directions of 315 ° and 315 °. As an example of the ion implantation conditions at this time, arsenic ions (As ⁺ ) are used as the implanted ions, and the dose is 1 × 10 ¹² / cm ² to 1 × 10 ¹⁴ / cm ^{2 at} a dose of several tens keV.
It is set to about.

Incidentally, the ion implantation angle becomes 45 ° or less.
And the radius of curvature rj of the diffusion layer at the gate end _gAre the diffusion layers 23 and 2
4 becomes smaller than the junction depth Xj, making it difficult to relax the electric field.
Become. When the ion implantation angle is larger than 75 °,
Diffusion on the element isolation region 12 side due to the shadow of the gate electrode 22
There is a high possibility that the layer portion will not be formed. Therefore,
The ON implantation angle is set in the above angle range.

Next, as shown in FIG. 3B, an insulating film covering the gate electrode 22 is formed on the semiconductor substrate 11 by, for example, a CVD method. This insulating film is formed by depositing, for example, silicon oxide having a thickness of several tens nm to one hundred and several tens nm. After that, the insulating film is etched back by anisotropic etching to form a sidewall insulating film 31 on the side wall of the gate electrode 22.

Next, the gate electrode 22 and the sidewall
Using the insulating film 31 and the isolation region 12 as masks
The element forming region 1 is formed by the second oblique ion implantation method.
3 for forming a diffusion layer in the semiconductor substrate 11.
Introduce. This second oblique ion implantation is performed on the semiconductor substrate surface.
The first oblique ion implantation method with respect to the normal direction of 11A
Angle smaller than the injection angle, for example larger than 45 °
Ions at an angle of less than 75 °, for example, at 45 °
Is introduced. At this time, the direction of the second oblique ion implantation is
When the gate length direction of the gate electrode 22 is 0 °, 25 ° to
65 ° range, 115 ° -155 ° range, 205 °-
4 in the range of 245 ° and 295 ° to 335 °
Orientation, for example 45 °, 135 °, 225 °, 315 °
It is desirable to introduce ions from four directions. At this time
As an example of the ion implantation conditions for arsenic,
ON (As⁺) At a dose of several tens keV to 1 × 1
0 ¹²Pieces / cm^Two~ 1 × 10¹⁴Pieces / cm^TwoSet to about
Do.

Thereafter, as shown in FIG. 3C, after an insulating film 41 covering the gate electrode 22 and the like is formed on the semiconductor substrate 11, flattening techniques such as etch-back and chemical mechanical polishing (CMP) are performed. After the surface of the insulating film 41 is planarized by the heat treatment of the bit line and capacitor forming process, the radius of curvature rj of the diffusion layer at the gate end (the end of the gate electrode 22) and the diffusion layer at the LOCOS end (the end of the element isolation region 12) is obtained. Are formed larger than the junction depth Xj.

In the above manufacturing method, each oblique ion implantation may be performed while rotating the semiconductor substrate 11 instead of performing ion implantation from four directions as described above.

In the first method for manufacturing a semiconductor memory device, diffusion layers 23 and 24 are formed in the element formation region 13 by a first oblique ion implantation method using the gate electrode 22 and the element isolation region 12 as a mask. To introduce impurities. Subsequently, after forming a side wall insulating film 31 on the side wall of the gate electrode 22, the gate electrode 22, the side wall insulating film 31 and the element isolation region 12 are used as masks to form an element formation region 13 by a second oblique ion implantation method. Since impurities for forming the diffusion layers 23 and 24 are introduced into the diffusion layers 23 and 24, the diffusion layers 23 and 24 have a shallow junction on the gate electrode 22 side and a radius of curvature larger than the junction depth at the junction surface with the semiconductor substrate 11. And a contact surface with the semiconductor substrate 11 in a state of being in contact with a side portion of the element isolation region 12 is formed in a substantially convex curved shape having a radius of curvature larger than the junction depth.

Next, the second embodiment of the semiconductor memory device according to the present invention will be described.
An example of the manufacturing method will be described as a second embodiment with reference to a manufacturing process diagram in FIG. In FIG. 4, FIG. 1 and FIG.
The same components as those described above are denoted by the same reference numerals.

As shown in FIG. 4A, an element isolation region 12 is formed in a semiconductor substrate (for example, a silicon substrate) 11 by an ordinary element isolation formation technique (for example, a LOCOS method), and an element formation region 13 is provided. . Next, a gate electrode 22 is formed on the element formation region 13 with a gate insulating film 21 interposed therebetween by a normal gate formation technique. For example, deposition after forming the gate insulating film 21 on the surface of the element formation region 13, doped polycrystalline silicon film, a tungsten silicide (WSi _x) layer CVD (chemical vapor deposition) to a thickness of several hundred nm the method After that, these films are patterned by a lithography technique and an etching technique to form a gate electrode 22.

Next, by the oblique ion implantation method using the gate electrode 22 and the element isolation region 12 as a mask,
An impurity for forming a diffusion layer is introduced into the semiconductor substrate 11 in the element formation region 13. In this oblique ion implantation, ions are introduced at an angle of, for example, 60 ° or more within a range of more than 45 ° and 75 ° or less with respect to the normal direction of the semiconductor substrate surface 11A. At this time, the direction of the first oblique ion implantation is 25 ° with the gate length direction of the gate electrode 22 being 0 °.
° -65 ° range, 115 ° -155 ° range, 205
4 orientations in the range of ° -245 ° and in the range of 295-335 °, for example 45 °, 135 °, 225 °, 315
It is desirable to introduce ions from four directions. As an example of the ion implantation conditions at this time, arsenic ions (As ⁺ ) are used as the implanted ions, and the dose is 1 at several tens keV.
The setting is performed at about × 10 ¹² / cm ² to 1 × 10 ¹⁴ / cm ² . Since FIG. 3 shows a memory cell of a DRAM, a word line 51 having an extended gate electrode is formed on the element isolation region 12.

Incidentally, the ion implantation angle becomes 45 ° or less.
And the radius of curvature rj of the diffusion layer at the gate end _gAre the diffusion layers 23 and 2
4 becomes smaller than the junction depth Xj, making it difficult to relax the electric field.
Become. When the ion implantation angle is larger than 75 °,
Diffusion on the element isolation region 12 side due to the shadow of the gate electrode 22
There is a high possibility that the layer portion will not be formed. Therefore,
The ON implantation angle is set in the above angle range.

Next, as shown in FIG.
By the method or the thermal oxidation method, on the semiconductor substrate 11,
A silicon oxide film 42 covering the gate electrode 22 and the element isolation region 12 is formed to a thickness of several tens nm. Thereafter, by the ion implantation method using the gate electrode 22, the silicon oxide film 42 formed on the side wall of the gate electrode 22 and the element isolation region 12 as a mask, the depth of the impurity introduced by the oblique ion implantation is reduced. An impurity for forming a diffusion layer is introduced into the semiconductor substrate 11 in the element forming region 13 in a deep state. As the impurity ions, for example, arsenic ions (As ⁺ ) are used, the dose is 1 × 10 ¹² / cm ² to 1 × 10 ¹⁴ / cm ² , and the projection range Rp is the projection range of the first oblique ion implantation. Ion implantation is performed with the energy set to be deeper than Rp.

Next, as shown in FIG. 4C, a polysilicon film covering the silicon oxide film 42 is formed by, for example, a CVD method. This polysilicon film is formed by depositing a thickness of, for example, several tens nm to one hundred and several tens nm. After that, the polysilicon film is etched back by anisotropic etching to form a sidewall 43 on the side wall of the gate electrode 22 with the silicon oxide film 42 interposed therebetween.

Subsequently, the gate electrode 22, the gate electrode 2
The silicon oxide film 42 formed on the side wall of the semiconductor device 2, the sidewall 43, and the element isolation region 12 are used as masks to keep the element deeper than the depth of the impurity introduced earlier by the ion implantation. An impurity for forming a diffusion layer is introduced into the semiconductor substrate 11 in the formation region 13. As an example of the ion implantation conditions, arsenic ions (As ⁺ ) are used as impurity ions, and the dose is 1
It is performed by setting the energy so that Rp becomes deeper than Rp of the previous ion implantation, from × 10 ¹² / cm ² to 1 × 10 ¹⁴ / cm ² .

Thereafter, as shown in FIG. 4D, an insulating film (not shown) covering the gate electrode 22 and the like is formed on the semiconductor substrate 1.
1, then etch-back, chemical mechanical polishing (C
After the surface of the insulating film is flattened by a flattening technique such as MP), heat treatment of a bit line and capacitor forming process is performed, and a gate end and a LOCOS end (element) are formed on the semiconductor substrate 11 on both sides of the gate electrode 22. Diffusion layers 23 and 24 are formed in which the radius of curvature rj of the diffusion layer at the end of the separation region is larger than the junction depth Xj.

In the above manufacturing method, each oblique ion implantation may be performed while rotating the semiconductor substrate 11 instead of performing ion implantation from four directions as described above.

In the second method of manufacturing the semiconductor memory device, after the gate electrode 22 is formed, the silicon oxide film 42 formed on the side wall of the gate electrode 22 is formed, and after the sidewall 43 is formed, By performing the ion implantation, the impurity is introduced deeper than the depth of the impurity introduced by the previous ion implantation.
Reference numeral 24 denotes a shallow junction on the gate electrode 22 side, and a junction surface with the semiconductor substrate 11 is formed in a substantially convex curved shape having radii of curvature rj _g and rj _l larger than the junction depth Xj. Is in contact with the side portion of the semiconductor substrate 11, the bonding surface with the semiconductor substrate 11 has a radius of curvature r larger than the bonding depth Xj.
It is formed in a substantially convex curved shape having j _g and rj _l .

In each embodiment of the present invention, arsenic (As) is used as the N-type impurity. Phosphorus (P) has a larger diffusion coefficient than arsenic (As) and cannot secure an effective gate length of the transistor. Moreover, since the diffusion profile cannot be controlled by the ion implantation depth, arsenic (As)
It is preferable to use

[0038]

As described above, according to the semiconductor memory device of the present invention, one side of each diffusion layer is formed with a shallow junction on the gate electrode side, and the junction surface with the semiconductor substrate is larger than the junction depth. It is formed in a substantially convex curved shape having a large radius of curvature,
The other side of each diffusion layer is formed so as to be in contact with the side of the element isolation region, and the bonding surface with the semiconductor substrate is formed in a substantially convex curved surface having a radius of curvature larger than the bonding depth. Electric fields on the gate electrode side and the element isolation region side of the layer are reduced. Therefore, the junction leak current caused by the electric field can be reduced. Further, since the diffusion layer can be formed so as to include the crystal defect region generated in the semiconductor substrate near the side portion of the element isolation region, the depletion layer does not extend to the crystal defect region. As described above, the data retention characteristics of the DRAM can be improved.

According to the first manufacturing method of the present invention, an impurity for forming a diffusion layer is introduced into an element formation region by a first oblique ion implantation method using a gate electrode as a mask. After forming the sidewall insulating film on the side wall, an impurity for forming the diffusion layer in the element formation region is introduced by the second oblique ion implantation method using the gate electrode and the sidewall insulating film as a mask. A shallow junction on the gate electrode side and a junction surface with the semiconductor substrate can be formed into a substantially convex curved surface having a radius of curvature larger than the junction depth, and further in contact with the side of the element isolation region and with the semiconductor substrate. The joining surface can be formed in a substantially convex curved shape having a radius of curvature larger than the joining depth. Therefore, it is possible to form the diffusion layer in a shape that can alleviate the electric field at the gate end and the element isolation region end.

According to the second manufacturing method of the present invention, after forming the gate electrode, forming the silicon oxide film formed on the side wall of the gate electrode, forming the side wall, ion implantation is performed sequentially. Since the impurity is introduced deeper than the impurity introduction depth by the ion implantation performed earlier,
The diffusion layer can be formed to have a shallow junction on the gate electrode side and a substantially convex curved surface having a radius of curvature larger than the junction depth at the junction surface with the semiconductor substrate. The bonding surface with the substrate can be formed into a substantially convex curved surface having a radius of curvature larger than the bonding depth. Therefore, it is possible to form the diffusion layer in a shape that can alleviate the electric field at the gate end and the element isolation region end.

[Brief description of the drawings]

FIG. 1 is a schematic configuration sectional view and a layout diagram of an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a relationship diagram between a junction leak current and a radius of curvature rj of a diffusion layer.

FIG. 3 is a manufacturing process diagram of an embodiment of a first manufacturing method according to the present invention.

FIG. 4 is a manufacturing process diagram of an embodiment of a second manufacturing method according to the present invention.

FIG. 5 is an explanatory diagram of a memory transistor of a DRAM according to a conventional technique.

FIG. 6 is an explanatory diagram of a problem.

[Explanation of symbols]

11 semiconductor substrate, 12 element isolation region, 13 element formation region, 22 gate electrode, 23, 24 diffusion layer, Xj
... junction depth, rj _g, rj _l ... curvature radius

Claims (9)

[Claims] 1. A semiconductor memory device in which a diffusion layer of an insulated gate transistor is formed in an element formation region provided in a semiconductor substrate and separated by an element isolation region formed in the semiconductor substrate. Are formed on the semiconductor substrate on both sides of the gate electrode of the insulated gate transistor, and one side of each of the diffusion layers has a shallow junction with the gate electrode and a junction surface with the semiconductor substrate has a junction depth smaller than the junction depth. Is formed in a substantially convex curved shape having a large radius of curvature, and the other side of each of the diffusion layers is in contact with a side portion of the element isolation region, and a bonding surface with the semiconductor substrate is larger than a bonding depth. A semiconductor memory device characterized by being formed in a substantially convex curved shape having a radius of curvature. 2. A step of forming a gate electrode via a gate insulating film in an element formation region provided on the semiconductor substrate and separated by an element isolation region formed on the semiconductor substrate; A step of introducing an impurity for forming a diffusion layer in the element formation region by a first oblique ion implantation method using the element isolation region as a mask, and a step of forming a sidewall insulating film on a side wall of the gate electrode And introducing an impurity for forming a diffusion layer in the element formation region by a second oblique ion implantation method using the gate electrode, the sidewall insulating film, and the element isolation region as a mask. A method of manufacturing a semiconductor memory device. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein said second oblique ion implantation is performed by using an implantation angle of said first oblique ion implantation method with respect to a normal direction of said semiconductor substrate surface. A method of manufacturing a semiconductor memory device, wherein ions are introduced at a small angle. 4. The method for manufacturing a semiconductor memory device according to claim 2, wherein the first and second oblique ion implantations are performed in a range of 25 ° to 65 ° with a gate length direction of the gate electrode being 0 °. 1
15 ° to 155 ° range, 205 ° to 245 ° range,
And introducing ions from four directions in the range of 295 ° to 335 °. 5. The method of manufacturing a semiconductor memory device according to claim 3, wherein the first and second oblique ion implantations are performed in a range of 25 ° to 65 ° with a gate length direction of the gate electrode being 0 °. 1
15 ° to 155 ° range, 205 ° to 245 ° range,
And introducing ions from four directions in the range of 295 ° to 335 °. 6. A step of forming a gate electrode via a gate insulating film in an element formation region provided on the semiconductor substrate and separated by an element isolation region formed on the semiconductor substrate; Introducing an impurity for forming a diffusion layer into the element formation region by oblique ion implantation using the element isolation region as a mask; and silicon oxide covering the gate electrode and the element isolation region on the semiconductor substrate. A step of forming a film, and a depth of introduction of impurities introduced by the oblique ion implantation by an ion implantation method using the gate electrode, the silicon oxide film formed on the side wall of the gate electrode, and the element isolation region as a mask. A step of introducing an impurity for forming a diffusion layer in the element formation region in a state deeper than the gate electrode; Forming a sidewall on the gate electrode, the silicon oxide film formed on the side wall of the gate electrode, the side wall and the element isolation region by a mask using the ion implantation method. A step of introducing an impurity for forming a diffusion layer in the element forming region in a state deeper than the introduced depth of the impurity. 7. The method for manufacturing a semiconductor memory device according to claim 6, wherein said oblique ion implantation introduces ions within a range of more than 45 ° and 60 ° or less with respect to a normal direction of said semiconductor substrate surface. A method for manufacturing a semiconductor memory device. 8. The method for manufacturing a semiconductor memory device according to claim 6, wherein the oblique ion implantation is performed in a range of 25 ° to 65 °, and in a range of 115 ° to 15 °, with a gate length direction of the gate electrode being 0 °.
5 ° range, 205 ° -245 ° range, and 295
A method for manufacturing a semiconductor memory device, characterized in that ions are introduced from four directions in the range of degrees to 335 degrees. 9. The method for manufacturing a semiconductor memory device according to claim 7, wherein the oblique ion implantation is performed in a range of 25 ° to 65 °, and 115 ° to 15 °, with a gate length direction of the gate electrode being 0 °.
5 ° range, 205 ° -245 ° range, and 295
A method for manufacturing a semiconductor memory device, comprising irradiating ions from four directions within a range of from °° to 335 °.