JPH11163268A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce wiring delay between functional blocks without changing circuits in the functional blocks, by providing wiring relay circuits for dividing and relaying clock signals of long wiring in the functional blocks. SOLUTION: Functional blocks 301-307 are circuits such as CPU, DSP or ASSP for performing desired functions and are further provided with a wiring relay circuit 5. The wiring relay circuit 5 is provided with two buffer circuits 501 and 502 in the functional block 306. The wiring is once taken out of the functional blocks and is put again in the functional blocks. In other words, adjustment of delay can be performed easily and with efficiency by connecting buffer circuits when necessary in wiring between functional blocks, without going back to layout and wiring in the functional block 306 by putting input and output out of the functional block 306.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a means for controlling a wiring delay between functional blocks.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration example of a conventional semiconductor integrated circuit. 5, the semiconductor integrated circuit 131 includes functional blocks 331 to 337, a clock generation circuit 4, and an input / output circuit 2.

The clock generation circuit 4 individually delays some or all of the function blocks based on a signal supplied from the external input terminal 6 through the input / output circuit 2 or from an arbitrary function block. Make adjustments and supply clock signals. FIG. 5 shows an example in which clock signals 731, 732, and 733 are supplied to three functional blocks 331, 332, and 337 based on a signal supplied from the external input terminal 6 through the input / output circuit 2.

FIG. 2 is a diagram for explaining the clock generation circuit 4. In FIG. 2, reference numeral 402 denotes a clock generation circuit;
03 is a delay adjustment circuit, and 401 is a clock input terminal. First, a clock signal is generated by a clock generation circuit 402 using a signal input from a clock input terminal 401.
After that, the delay adjustment circuit 403 adds a desired delay time to each functional block and outputs a clock signal.
The clock generation circuit 402 is specifically a PLL, a frequency divider, a buffer circuit, or the like.

[0005] The function blocks 331 to 337 are circuits for implementing arbitrary functions, and include a CPU, a DSP, an ASSP, and the like. The input / output circuit 2 includes a semiconductor integrated circuit 131
Is an interface circuit for connecting the inside and the outside of the device.

The function blocks 331 to 337, the clock generation circuit 4, and the input / output circuit 2 have signal lines connecting the respective circuits in addition to the clock signal in order to realize desired functions. Since it is not directly related to the essence of the description, it is omitted in FIG.

Next, in the semiconductor integrated circuit 131 configured as described above, three functional blocks 331, 33
The clock delay time between the external input terminal 6 for supplying to the clock generation circuit 4 through the input / output circuit 2 and the clock terminal of the flip-flop in each of the functional blocks 331, 332, 337 is made the same between 2 and 337. The method will be described. Here, in the functional block, the clock delay time from the clock input terminal of the functional block to the clock terminal of the flip-flop is assumed to be the same in advance by clock tree synthesis or the like.

For each functional block, a clock delay time from the external input terminal 6 to the clock terminal of the flip-flop in each functional block, excluding the delay time of the delay adjustment circuit 403, is obtained. Based on the obtained maximum value of the delay value, for example, a minimum delay time is added by the delay adjustment circuit 403 in the clock generation circuit 4 for a functional block corresponding to the maximum value, and for a functional block not corresponding to the maximum value, , Delay adjustment circuit 403
The delay value of the difference from the maximum value including the delay time is added to the delay time by the delay adjustment circuit 403 in the clock generation circuit 4 so that the three functional blocks 331, 332, 3
The clock delay time between 37 can be the same.

[0009]

As described above, the conventional semiconductor integrated circuit 131 adjusts the delay by the delay adjustment circuit 403 for each functional block so that the clock delay time between the functional blocks is the same. I was Generally, the delay adjustment circuit 403 is realized by changing the number of stages of the buffer and the driving capability. Since this buffer is composed of a transistor, the delay is adjusted by the delay of the transistor.

The clock signal lines 731, 732, 7 of FIG.
As shown in FIG.
If the wiring lengths up to 31, 332, and 337 greatly differ among the functional blocks, this difference is also adjusted by the delay adjusting circuit 403. However, since the transistor delay and the wiring delay have different characteristics with respect to changes in temperature and power supply voltage, the difference between the wiring delays cannot be completely adjusted by the transistor delay. This tendency is prominent in deep submicron semiconductor integrated circuits after the 0.35 μm process, in which the ratio of the wiring delay to the delay time between terminals becomes dominant compared to the delay of the transistor. In some cases, the manufactured semiconductor integrated circuit does not operate.

In order to avoid this problem, there is a method of increasing the width of the longer wiring or increasing the length of the shorter wiring to make the wiring delay as long as possible. In this case, reducing the wiring efficiency increases the chip size, and the number of work steps required for this is also required separately from normal wiring work, which may cause a reduction in development efficiency.

Accordingly, the present invention has been made in view of the above problems, and an object thereof is to reduce a wiring delay between functional blocks only by changing a wiring connection between the functional blocks without changing a circuit in the functional blocks. It is to provide a semiconductor integrated circuit.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, a semiconductor integrated circuit according to a first feature of the present invention is for dividing and relaying a clock signal having a long wiring length in a functional block. Wiring relay circuit.

According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, the wiring relay circuit includes at least one buffer circuit, and the input and output of each buffer circuit are functional. Make a configuration that connects directly to the input and output of the block.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit according to the first or second aspect, wherein the clock generation circuit is mounted on an arbitrary functional block.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit having a wiring relay circuit for relaying a signal line other than a clock in the semiconductor integrated circuit of the first to third aspects.

In the semiconductor integrated circuit according to the first, second and third aspects of the present invention, the long wiring is cut off by temporarily relaying the long clock signal in a wiring relay circuit, for example, in a buffer circuit. , Can be divided into short wires. Generally, the wiring delay increases in proportion to the square of the wiring length. Therefore, even when the total wiring length between terminals is the same, the wiring delay is temporarily reduced by relaying a buffer circuit or the like midway. Since the delay of the transistor in the delay adjustment circuit is adjusted as in the above-described conventional example, the characteristics of the delay of the transistor and the delay of the wiring with respect to changes in temperature and power supply voltage are different. The clock delay time between the functional blocks can be made the same within a range in which the variation is allowable.

Further, in the semiconductor integrated circuit according to the fourth aspect of the present invention, when it is desired to reduce a wiring delay of a signal other than a clock due to a critical path or the like, the signal is transferred to a buffer in a wiring relay circuit, for example, a buffer. It can be realized by relaying once with a circuit.

[0019]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. 1, a semiconductor integrated circuit 101 includes functional blocks 301 to 307, a clock generation circuit 4, and an input / output circuit 2.

The configuration and function of the clock generation circuit 4 are the same as those of the above-described conventional example. In FIG. 1, based on a signal supplied from the external input terminal 6 through the input / output circuit 2,
An example in which clock signals 701, 702, and 703 are supplied to three functional blocks 301, 302, and 307 will be described.

Each of the functional blocks 301 to 307 is a circuit for realizing an arbitrary function such as a CPU, a DSP or an ASSP, and further includes a wiring relay circuit 5 which is a feature of the present invention. The wiring relay circuit 5 includes, as shown in FIG.
06, two buffer circuits 501 and 502 are provided.
The wiring is once drawn out of the functional block, and is returned again in the functional block. There are the following two reasons for this. That is, 1) For each buffer circuit, by putting the input and the output out of the functional block, it is possible to adjust the delay without re-arranging and wiring in the functional block.
If necessary, the connection can be realized by connecting a buffer circuit at the time of wiring between functional blocks, so that delay adjustment can be easily and efficiently realized. 2) If wiring is performed between the buffer circuits in the functional block, it is difficult to control the wiring length.

In this example, there are two buffer circuits, but there may be one or three or more buffer circuits. Also, a wiring relay circuit may be provided in a functional block other than the functional block 306 in some cases. In addition, the wiring relay circuit 5 can be inserted into a functional block by: 1) a method in which all the functional blocks are inserted in advance and only those required for delay adjustment are used; and 2) a floor plan of a chip is known. In this case, there are two types of methods in which only the functional blocks necessary for delay adjustment are stored.

Here, the reason why the wiring relay circuit 5 is included in the functional block 306 is as follows. That is, the wiring relay circuit 5 is taken out of the functional block, and
If only the functional blocks are arranged, in the wiring between the functional blocks, that part is taken away from the wiring area, and further necessary wiring is blocked in this part, so that the wiring area between the functional blocks becomes large. In the end, the chip area is increased and the cost is increased.
Therefore, the wiring relay circuit 5 is included in the functional block. Since the wiring relay circuit 5 is very small, it does not increase the area of the functional block even if it is placed in a functional block, so that there is an advantage that the chip area is not adversely affected.

The configuration and function of the input / output circuit 2 are the same as those of the above-described conventional example. The function blocks 301 to 307, the clock generation circuit 4, and the input / output circuit 2 have signal lines connecting the respective circuits in addition to the clock signal in order to realize desired functions. 1 is omitted in FIG.

Next, in the semiconductor integrated circuit 101 configured as described above, three functional blocks 301 and 30 are provided.
The clock delay time from the external input terminal 6 for supplying to the clock generation circuit 4 through the input / output circuit 2 to the clock terminal of the flip-flop in each of the functional blocks 301, 302, and 307 is made the same between 2 and 307. The method will be described. Here, in the functional block, the clock delay time from the clock input terminal of the functional block to the clock terminal of the flip-flop is assumed to be the same in advance by clock tree synthesis or the like.

First, the clock signals 701, 702, 70
Among the three, the clock signal 703 that is clearly longer than the other clock signals is divided into three using the buffers 501 and 502 of the wiring relay circuit 5 included in the functional block 306. In this example, if the clock signal line 703 is equally divided into three, the wiring delay increases in proportion to the square of the wiring length as described above. It can be reduced as shown.

[0028]

(Equation 1)

Next, for each functional block, a clock delay time from the external input terminal 6 to the clock terminal of the flip-flop in each functional block, excluding the delay time of the delay adjustment circuit 403, is obtained. Also,
Regarding the function block 307, the delay of the buffer circuits 501 and 502 in the wiring relay circuit 5 and the function block 3
The clock delay time is obtained by adding the wiring delay in 06.
Based on the obtained maximum value of the delay value, for example, a minimum delay time is added by the delay adjustment circuit 403 in the clock generation circuit 4 for a functional block corresponding to the maximum value, and for a functional block not corresponding to the maximum value, The delay value of the difference from the maximum value including the delay time of the delay adjustment circuit 403 is added to the delay time by the delay adjustment circuit 403 in the clock generation circuit 4 so that the three functional blocks 30 are added.
The clock delay time between 1, 302, and 307 can be the same.

FIG. 3 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. 3, a semiconductor integrated circuit 111 includes functional blocks 311 to 317, a clock generation circuit 4, and an input / output circuit 2.

The configuration and function of the clock generation circuit 4 are the same as those of the above-described conventional example. However, in this example, the clock generation circuit 4 is provided in the function block 314. FIG.
, Three functional blocks 311, 3 based on a signal supplied from the external input terminal 6 through the input / output circuit 2.
An example in which clock signals 711, 712, and 713 are supplied to 12 and 317 will be described.

Each of the functional blocks 311 to 317 is a circuit for realizing an arbitrary function such as a CPU, a DSP or an ASSP, and further includes a wiring relay circuit 5 which is a feature of the present invention. The wiring relay circuit 5 includes, as shown in FIG.
16 has two buffer circuits 501 and 502.
In this example, there are two buffer circuits, but there may be one or three or more buffer circuits. Also, the function block 31
In some cases, a wiring relay circuit may be provided in a functional block other than the sixth functional block.

The configuration and function of the input / output circuit 2 are the same as those of the above-described conventional example. The function blocks 311 to 317, the clock generation circuit 4, and the input / output circuit 2 have signal lines connecting the respective circuits in addition to the clock signal in order to realize desired functions. Are omitted in FIG.

Next, in the semiconductor integrated circuit 111 configured as described above, the three functional blocks 311 and 31
The clock delay time between the external input terminal 6 for supplying the clock generation circuit 4 through the input / output circuit 2 to the clock terminal of the flip-flop in each of the functional blocks 311, 312, and 317 is made the same between 2 and 317. The method will be described. Here, in the functional block, the clock delay time from the clock input terminal of the functional block to the clock terminal of the flip-flop is assumed to be the same in advance by clock tree synthesis or the like.

First, the clock signals 711, 712, 71
3, the clock signal 713 which is clearly longer than the other clock signals is divided into three using the buffers 501 and 502 of the wiring relay circuit 5 included in the function block 316. In this example, if the clock signal line 713 is equally divided into three, the wiring delay increases in proportion to the square of the wiring length as described above. It can be reduced as shown.

Next, for each functional block, a clock delay time from the external input terminal 6 to the clock terminal of the flip-flop in each functional block, excluding the delay time of the delay adjusting circuit 403, is obtained. Also,
Regarding the function block 317, the delay of the buffer circuits 501 and 502 in the wiring relay circuit 5 and the function block 3
The clock delay time is obtained by adding the wiring delay in 16.
Based on the obtained maximum value of the delay value, for example, a minimum delay time is added by the delay adjustment circuit 403 in the clock generation circuit 4 for a functional block corresponding to the maximum value, and for a functional block not corresponding to the maximum value, The delay value of the difference from the maximum value including the delay time of the delay adjustment circuit 403 is added to the delay time by the delay adjustment circuit 403 in the clock generation circuit 4 so that the three functional blocks 31 are added.
The clock delay time between 1, 3, 12 and 317 can be the same.

FIG. 4 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. In FIG. 4, the semiconductor integrated circuit 121 includes functional blocks 301, 306, 3
22 to 325 and 327, a clock generation circuit 4, and an input / output circuit 2.

The configuration and function of clock generation circuit 4 are the same as those in FIG. Note that the configuration and function of the clock generation circuit 4 may be the same as those in FIG. 2 or FIG.

Function blocks 301, 306, 322-3
Reference numerals 25 and 327 denote circuits for realizing arbitrary functions such as a CPU, a DSP and an ASSP, and further include wiring relay circuits 51 and 52 which are features of the present invention. Wiring relay circuit 51,
52 includes buffer circuits 503 and 504 in functional blocks 324 and 325, respectively, as shown in FIG. In this example, there is one buffer circuit, but there may be two or more buffer circuits. In some cases, a functional block other than the functional blocks 324 and 325 is also provided with a wiring relay circuit.

The configuration and function of the input / output circuit 2 are the same as those of the above-described conventional example. The function blocks 321 to 327, the clock generation circuit 4, and the input / output circuit 2 are used to realize desired functions in addition to the critical path signal 724.
Although there are signal lines connecting the respective circuits, they are omitted in FIG. 4 because they have no direct relation to the essence of the description.

Next, a method of reducing the wiring delay of the critical path signal 724 in the semiconductor integrated circuit 121 configured as described above will be described. However, the critical path signal 724 is originally the function block 322
Is a signal directly connected to the function block 327.

The critical path signal 724 is divided into three using the buffer circuits 503 and 504 of the wiring relay circuits 51 and 52 included in the function blocks 324 and 325 as shown in FIG.

In this example, the clock signal line 72
If 4 is equally divided into three, as described above, the wiring delay increases in proportion to the square of the wiring length, so that the clock wiring delay can be reduced as shown in (Equation 1).

[0044]

As described above, according to the present invention, when a signal having a long wiring length between functional blocks is a problem, the circuit between the functional blocks is not changed particularly without changing the circuit in the functional block. Since the wiring delay value can be suppressed to a small value only by changing the connection, skew adjustment between specific signals such as clock signals between functional blocks and improvement of a critical path can be easily and efficiently realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a clock generation circuit.

FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 2 input / output circuit 301 to 307 functional block 4 clock generation circuit 5 wiring relay circuit 501, 502 buffer circuit 6 external input terminal 701 to 703 clock signal

Claims (4)

[Claims] 1. A clock comprising: a functional block including a wiring relay circuit for relaying a clock signal; and a means for supplying the clock signal to the functional block and adjusting a clock delay between the functional blocks. A semiconductor integrated circuit comprising a generation circuit. 2. The wiring relay circuit according to claim 1, wherein the wiring relay circuit includes at least one buffer circuit, and an input and an output of each of the buffer circuits are directly connected to an input and an output of the functional block. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein said clock generation circuit is provided in any of said functional blocks. 4. A wiring relay circuit for relaying a signal line other than a clock signal.
A semiconductor integrated circuit as described in the above.