JPH10199985A - Semiconductor integrated circuit and layout design method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein useless power consumption is reduced and clock skew is restrained. SOLUTION: This semiconductor integrated circuit has a clock supply path 20, which has a tree structure and distributes clocks CK to a plurality of flip- flops 11-13. A clock control cell CC, which supplies clocks to the respective branch points according to a control signal, is interposed in one or two or more branch points in the clock supply path 20 of the tree structure. To each of the flip-flops 11-13, a control circuit 30 supplies control signals S1, S2S to the clock control cell CC such that the clock CK is supplied to the flip-flop, only when the flip-flop needs the clock CK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit and a layout design method thereof.

[0002]

2. Description of the Related Art Some ICs (semiconductor integrated circuits) include a synchronous circuit composed of a large number of flip-flops driven by a common clock. When designing the layout of an IC including such a synchronous circuit, in order to ensure the stability of the operation of the synchronous circuit, the clock skew, that is, the deviation of the clock supply timing to each flip-flop is minimized. Care must be taken. From such considerations, a method is adopted in which the layout of the clock wiring for supplying the clock is prioritized over other parts, and the flip-flops receiving the clock supply are arranged along the clock wiring. There is.

FIGS. 5A to 5D show an example of an IC chip in which chip layout is performed with priority given to clock wiring. First, FIG. 5A shows a chip layout in which a fishbone type clock wiring 2 is connected between output terminals of clock drivers 1 and 1 for outputting a clock. FIG. 5B shows a chip layout in which the mesh type clock wiring 3 is connected between the output terminals of the clock drivers 1 and 1. FIG. 5 (c)
Shows a chip layout using the H-tree structure wiring 4 as a clock wiring. In each of the techniques shown in these figures, a wiring pattern of a predetermined shape is formed on a chip, and a large number of flip-flops (not shown) receiving a clock are arranged along the wiring pattern. .

On the other hand, FIG. 5D shows an example of a chip layout obtained by so-called clock tree synthesis. Clock tree synthesis is one of automatic layout techniques suitable for a circuit including a large number of flip-flops supplied with a common clock. In this clock tree synthesis, when laying out a large number of flip-flops supplied with such a clock on a chip,
As a clock supply path connecting a clock supply source and each flip-flop, a clock supply path 5 having a tree structure including a plurality of clock drivers as illustrated in FIG. 5D is automatically generated. When the clock supply path 5 is automatically generated, the clock wiring length and the driving capability of each clock driver are optimized so that a clock is supplied to each flip-flop with a predetermined target delay amount.

[0005]

By the way, the above-mentioned layout method using the fishbone type clock wiring, the mesh type clock wiring, and the clock wiring having the H-tree structure can keep the total length of the clock wiring itself relatively short. However, since a clock wiring pattern having a predetermined shape is formed on a chip, there is a problem that the degree of freedom of wiring other signals is reduced and the degree of integration of the chip is reduced.
Further, the layout method using the mesh type clock wiring has a problem that the total length of the wiring is relatively long and the load on the clock driver is large, so that it is difficult to operate the synchronous circuit at high speed and power consumption is increased. was there.

On the other hand, a layout based on clock tree synthesis optimizes a clock supply path so that a clock is supplied to each flip-flop at an appropriate timing, and is thus effective in suppressing clock skew. However, even if this clock tree synthesis is used, no consideration is given to reducing power consumption of a clock driver or the like of a synchronous circuit. In other words, even if a synchronous circuit is laid out by clock tree synthesis, a clock driver that supplies a clock to a non-operating flip-flop in the synchronous circuit and a clock buffer in the flip-flop are unnecessarily activated. Can occur in general, and this unnecessary activation causes an increase in power consumption.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and a semiconductor integrated circuit and a semiconductor integrated circuit in which the clock skew is reduced by utilizing the advantages of the clock tree and the power consumption is reduced. It is an object of the present invention to provide a circuit layout design method.

[0008]

The invention according to claim 1 is
A clock supply path having a tree structure for branching a clock and supplying the divided circuit to a plurality of sequential circuits, and one or more branch points in the clock supply path having the tree structure interposed therebetween;
A clock control cell that supplies a clock to each branch destination according to a control signal; and a clock control cell that supplies a clock to the sequential circuit only when each of the plurality of sequential circuits requires a clock. A gist of the present invention is a semiconductor integrated circuit including a control unit for supplying the control signal.

According to a second aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit having a plurality of sequential circuits to which a common clock is supplied. Divide the clock,
A clock control cell that supplies a clock to each branch destination according to a control signal is interposed between the common clock supply source and at least a part of the plurality of sequential circuits, and the control signal is supplied to the clock. Adding control means for supplying control cells; b. Setting a target delay amount for each signal path from the common clock supply source to the plurality of sequential circuits; c. Automatically generating layout information of a circuit inserted through a clock supply path having a tree structure optimized to satisfy the target delay amount from the clock control cell to each of the sequential circuits by a clock tree synthesis method The gist of the present invention is a layout design method for a semiconductor integrated circuit, comprising:

According to a third aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit having a plurality of sequential circuits to which a common clock is supplied. Setting a target delay amount for each signal path from the common clock supply source to the plurality of sequential circuits; b. According to the clock tree synthesis method, layout information of a circuit inserted through a clock supply path having a tree structure optimized so as to satisfy the target delay amount from the common clock supply source to the plurality of sequential circuits is obtained. Automatically generating; c. A clock control cell for branching a clock and supplying a clock to each branch destination in accordance with control information is inserted into one or more branch points in a clock supply path of the tree structure, and the control signal is controlled by the clock control. Modifying the layout information to add control means for supplying the cells; d. A step of further correcting the corrected layout information so that a delay amount from the common clock supply source to the plurality of sequential circuits satisfies the target delay amount. The gist is the layout design method.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments will be described to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

A. Embodiment of Semiconductor Integrated Circuit According to the Present Invention The semiconductor integrated circuit according to the present embodiment basically uses a clock supply path having a tree structure automatically generated by clock tree synthesis. A means for suppressing power is added. Hereinafter, referring to FIGS. 1A and 1B, in comparison with a circuit generated by general clock tree synthesis,
An embodiment of a semiconductor integrated circuit according to the present invention will be described.

First, FIG. 1A shows an example of a circuit generated by general clock tree synthesis. In the figure, 11 to 13 are flip-flops to which a common clock CK is supplied. Reference numeral 20 denotes a clock supply path having a tree structure automatically generated by clock tree synthesis, and includes a plurality of clock drivers 21 to 24 and a wiring pattern.

On the other hand, the semiconductor integrated circuit according to the present embodiment has a configuration shown in FIG. That is, in the semiconductor integrated circuit according to the present embodiment, each of one or two or more branch points (the branch points circled by broken lines in FIG. 1A in this example) in the clock supply path 20 having the tree structure. A clock control cell CC for controlling the supply of a clock to the branch destination is inserted, and a control circuit 30 for supplying a control signal to the clock control cell CC is provided.

FIG. 2 shows the function of the clock control cell CC. The clock control cell CC branches the clock input to the input terminal I and outputs it from the output terminals O1 and O2. As shown in FIG.
Whether or not to output a clock can be freely controlled for each output terminal by the values of 1 and S2.

In the example shown in FIG.
K is supplied to each of the flip-flops 11 to 13 via the clock control cell CC. However, the control circuit 30 supplies the clock CK to the flip-flops 11 to 13 only when each of the flip-flops needs the clock CK. Control signal S to the clock control cell CC as
1 and S2.

That is, in FIG. 1B, for example, when each of the flip-flops 11 to 13 is forcibly reset or when these output signals are not used by other circuits at all, 11 to 13 do not require the clock CK. Therefore, in such a case, the control circuit 30 outputs L as control signals S1 and S2 to the clock control cell CC. When only the flip-flop 11 needs the clock CK, it outputs H and L as the control signals S1 and S2, respectively. The same applies to other cases, and the control circuit 30 outputs control signals S1 and S2 according to FIG. 2 depending on whether each flip-flop requires the clock CK. FIG.
In FIG. 2B, only one clock control cell CC is shown to prevent the drawing from being complicated, but the control circuit 30 supplies the same control signal to other clock control cells not shown. I do.

As described above, according to the present embodiment, a clock is supplied to each flip-flop via a clock supply path having a tree structure obtained by clock tree synthesis. Since the used clock supply is controlled, the difference in clock supply timing to each flip-flop is suppressed low, and unnecessary power consumption of the clock driver and the flip-flop is suppressed.

B. Embodiment of Layout Design Method for Semiconductor Integrated Circuit According to the Present Invention Next, an embodiment of a layout design method for a semiconductor integrated circuit according to the present invention will be described.

(1) First Embodiment FIGS. 3A to 3C show a layout design method according to a first embodiment. In these figures, A
To F indicate flip-flops, respectively.

In this embodiment, first, a designer divides flip-flops supplied with a clock into a plurality of groups. This division is performed so that those requiring clock supply at the same timing (for example, flip-flops reset by the same signal) are always included in the same group.

FIG. 3A shows an example of a circuit in which this division is performed. In this example, the flip-flop is divided at a node circled by a broken line,
Flip-flops A to receive clock CK directly
D is divided into a group consisting only of flip-flops A and a group consisting of flip-flops BD. Further, flip-flops E and F using the output signal of flip-flop B as a clock are divided into separate groups.

Next, a clock control cell for supplying a clock to each of the divided groups is inserted on a clock supply path. FIG. 3B shows the result of interposing a clock control cell in the circuit shown in FIG. 3A, and CC1 and CC2 are each a clock control cell. At the same time,
A control circuit for supplying a control signal to each clock control cell is also added.

Next, a target delay amount from the clock control cell to each flip-flop is set for each group, and automatic layout is performed by synthesizing a clock tree. FIG.
In the example shown in (c), since the clock CK needs to reach the flip-flops A to D at the same timing, the target delay amount from the clock control cell CC1 to the flip-flop A and the target delay amount from the clock control cell CC1 to the flip-flops B to Each of the target delay amounts up to D is set to the same delay amount tpd. As a result of the automatic layout, for a circuit in the range shown in FIG. 3C, for example, one clock supply path having a delay amount tpd is automatically generated between the clock control cell CC1 and the flip-flop A. You. The clock control cell C
Between C1 and the flip-flops B to D, the clock C with the delay amount tpd is applied to any of the flip-flops.
A tree-structured clock supply path for sending K is automatically generated. In the automatic generation of these clock supply paths,
If necessary, a clock driver is inserted for adjusting the amount of delay, or the driving capability (output transistor size) of the clock control cell CC1 is automatically adjusted. The same applies to the clock supply path between the other clock control cells and the flip-flop.

Thus, the layout information of the semiconductor integrated circuit in which the clock skew is suppressed and the wasteful power consumption is prevented can be obtained.

(2) Second Embodiment FIGS. 4A to 4C show a layout design method according to a second embodiment. Similar to the first embodiment, each of A to F indicates a flip-flop.

In this embodiment, as in the first embodiment, first, the flip-flops A to F are divided into a plurality of groups (see FIG. 4A).

Next, a target delay amount is set for each flip-flop that receives a common clock supply, and an automatic layout is performed by clock tree synthesis. In the example shown in FIG. 4B, clock tree synthesis is performed using the target delay amount from the clock CK supply source to the flip-flops A to D as tpd. Then, after the completion of the automatic layout, the locations of the respective groups obtained by the first division on the chip are checked, and the nodes serving as boundaries between the groups (the nodes circled by broken lines in FIG. 4B) ).

Next, the clock control cells CC1 and CC2 are inserted into the nodes searched in this way, and the layout information is corrected so that the supply to each group is performed via these cells (FIG. 4C). reference). Also, a control circuit for sending a control signal to each clock control cell and layout information of wiring are added.

Next, layout information for delay adjustment is corrected. That is, as described above, the clock control cell C
As a result of the insertion of C1 and CC2, for example, the delay amount from the clock CK supply source to the flip-flop A is t
pd1, flip-flop B from clock CK supply
In some cases, the delay amount from the target delay amount tpd to the delay amount tpd is tpd2. Therefore, in such a case, the layout information is corrected to eliminate the deviation. The adjustment of the delay is performed by, for example, adjusting the transistor size of the clock driver automatically generated by the clock tree synthesis. In this embodiment, the same effects as those of the first embodiment can be obtained.

[0031]

As described above, according to the semiconductor integrated circuit and the layout design method thereof according to the present invention,
There is an effect that increase in power consumption can be suppressed as much as possible and clock skew can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of a semiconductor integrated circuit according to the present invention in comparison with a conventional one.

FIG. 2 is a diagram showing functions of a clock control cell in the embodiment.

FIG. 3 is a diagram showing a first embodiment of a semiconductor integrated layout design method according to the present invention;

FIG. 4 is a diagram showing a first embodiment of a semiconductor integrated layout design method according to the present invention;

FIG. 5 is a diagram showing a chip layout of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 11 to 13 flip-flops, 20 clock supply paths in a tree structure, CC clock control cells, 30 control circuits.

Claims (3)

[Claims] 1. A tree-structured clock supply path for branching a clock and supplying it to a plurality of sequential circuits, and 1 or 2 in the tree-structured clock supply path.
A clock control cell interposed at the branch point to supply a clock to each branch destination according to a control signal; and a clock is supplied to the sequential circuit only when each of the plurality of sequential circuits needs a clock. A control unit for supplying the control signal to the clock control cell. 2. A layout design method for a semiconductor integrated circuit having a plurality of sequential circuits to which a common clock is supplied, comprising: a. A clock control cell that branches a clock and supplies a clock to each branch destination according to a control signal is inserted between the common clock supply source and at least a part of the plurality of sequential circuits, and Adding control means for supplying a control signal to the clock control cell; b. Setting a target delay amount of each signal path from the common clock supply source to the plurality of sequential circuits; c. Automatically generating layout information of a circuit inserted through a clock supply path having a tree structure optimized to satisfy the target delay amount from the clock control cell to each of the sequential circuits by a clock tree synthesis method And a layout design method for a semiconductor integrated circuit. 3. A layout design method for a semiconductor integrated circuit having a plurality of sequential circuits to which a common clock is supplied, comprising: a. Setting a target delay amount for each signal path from the common clock supply source to the plurality of sequential circuits; b. According to the clock tree synthesis method, layout information of a circuit inserted through a clock supply path having a tree structure optimized so as to satisfy the target delay amount from the common clock supply source to the plurality of sequential circuits is obtained. Automatically generating; c. A clock control cell for branching a clock and supplying a clock to each branch destination in accordance with control information is inserted into one or more branch points in a clock supply path of the tree structure, and the control signal is controlled by the clock control. Modifying the layout information to add control means for supplying the cells; d. A step of further correcting the corrected layout information so that a delay amount from the common clock supply source to the plurality of sequential circuits satisfies the target delay amount. Layout design method.