JPH11163018A - Manufacture of semiconductor device and multi-layer wiring substrate and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device having high density and high connection reliability, and a multi-layer wiring substrate having high density and high reliability at low cost. SOLUTION: At the time patterning a base electrode layer constituted of a gold film 6, nickel film 5, and titanium film 4 of a semiconductor element, and at the time of providing an anchor between the insulating resin layer and wiring layer of a multi-layer wiring substrate, a particle ejecting means by compressed air is used. That is, abrasive particles are injected on the base electrode layer using a particle injection means by compressed air, and the base electrode layer is ground and removed by using a bump 9 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is bonded on a wiring board by using a flip-chip mounting technique and a multilayer wiring board used for the same.

[0002]

2. Description of the Related Art In recent years, with the development and spread of information processing technology, electronic devices have been reduced in size, thickness, and performance, and semiconductor chips have also been reduced in size and integrated. .

[0003] In particular, the L of a microprocessor unit or the like that operates at a frequency of several hundred MHz and performs arithmetic processing.
In order to cope with multi-input / output, high processing speed, and miniaturization of the SI chip, a method of mounting the SI chip on a module substrate by flip-chip connection technology is being adopted.

In the flip-chip connection technique, the mounting area of the semiconductor element on the substrate can be made the same as the size of the semiconductor device, and the connection wiring length can be shortened as compared with the wire bonding method, the TAB method or the like. This mounting technology is suitable for high-speed mounting. Flip chip mounting is a general term for a method in which a semiconductor element and a circuit board are opposed to each other and connected by bump electrodes. Depending on the connection method, for example, solder bump connection, microbump connection, anisotropic conductive film connection, conductive The connection is classified into a paste connection and a pressure connection.

[0005] Above all, the method using solder bumps has a wide allowable range for mounting position deviation due to the self-alignment effect at the time of reflow connection, and also causes the solder bumps to undergo plastic deformation, thereby reducing the stress generated at the connection portion.
Because of its advantages such as high reliability, it has become the mainstream of flip chip mounting.

However, in the connection method using solder bumps, a barrier metal is required between the semiconductor element electrode and the solder because the wettability between aluminum and solder, which are generally used as semiconductor element electrodes, is low.

The barrier metal is selected from, for example, a metal having good adhesion to the aluminum electrode, a metal which relatively slows the diffusion of tin in solder, a metal having good wettability with solder, and an antioxidant metal. Be composed. Generally, in order to reduce the cost and the number of processes, a metal having the above-mentioned effects is used, and is composed of two or three layers.

As a barrier metal for solder, a laminated film of titanium / copper / gold, a laminated film of chromium / copper / gold, etc. are used. And a structure in which gold, platinum or the like is deposited as an antioxidant layer.

In particular, when a tin-lead eutectic solder having a high tin content is used, the reaction between nickel and tin is slower than the reaction between copper and tin. Has a higher reliability than other barrier metal configurations (S. Honma, et.al., “Effectiveness
of thin film barrier metals for eutectic solder b
umps ", Proceedings of ISHM '96, PP. 87-92, 199
6).

In general, solder bumps are formed by electroplating, in which bumps can be formed in a wafer and collectively at a high film forming speed in order to obtain high productivity. As a conventional element technique for forming a bump by electroplating, a technique of forming a bump after previously patterning a barrier metal portion (Japanese Patent Laid-Open No. 61-1411).
59) After bump electrodes are formed, barrier metal is removed by etching using the bumps as a mask (Japanese Patent Laid-Open No.
223436) has been proposed.

However, in the latter technique, it is difficult to perform selective etching of tin in the solder and nickel which is one layer of the barrier metal, and tin in the solder dissolves when the barrier metal is patterned. Therefore,
There have been problems such as a change in the composition ratio of tin and lead in the solder and an uneven height of the solder bumps, leading to a reduction in yield after reflow connection and a reduction in connection reliability.

Further, if the etching protection resist is formed on the solder bumps in advance and the nickel is etched, the above problem can be avoided. However, it is necessary to form a resist pattern that completely covers the bumps. However, the bump pitch could not be reduced due to the increase in the pitch. In this case, there is also a problem that the manufacturing process is complicated.

In recent years, when a bump electrode is formed on a semiconductor chip made of a compound semiconductor such as gallium arsenide used as a high-speed device or a high-frequency device, the solubility of the compound semiconductor in nickel etchant is extremely high. A protective resist has to be formed even on a portion where no passivation film is formed, which further complicates the process.

On the other hand, after the former forming technique, that is, etching is first performed only for nickel which is one layer of the barrier metal,
When a method of forming a solder bump by electroplating is applied, a change in the composition of the solder can be prevented, and it is not necessary to form a protective resist for the solder or a protective resist when using a compound semiconductor.

FIGS. 22 to 31 show one of the barrier metals.
An example of a manufacturing process of a semiconductor device with a bump in a case where only a nickel layer is etched first will be described.

First, a semiconductor device as shown in FIG. 22 is prepared. An aluminum connection electrode 2 is provided on the active element surface of the semiconductor element 1, and the surface other than the connection electrode 2 is covered with a passivation film 13. The size, the number of electrodes, and the electrode pitch of the semiconductor element 1 can be arbitrarily set and can be appropriately selected.

Next, as shown in FIG.
A titanium film 4, a nickel film 5, and an antioxidant film 6 are sequentially sputtered thereon as barrier metal 50.

As shown in FIG. 24, on the oxidation preventing film 6, an etching resist 7 for etching the nickel film 5 / oxidation preventing film 6 is formed.

Thereafter, as shown in FIG. 25, an etching solution is applied, and the nickel 5 / oxidation preventing film 6 is etched using the etching resist 7 as a mask.

After completion of the etching, as shown in FIG.
The etching resist 7 is peeled off.

Next, as shown in FIG. 27, a solder plating resist 8 is formed around the barrier metal 50 and on the passivation film 13, and as shown in FIG. 28, solder plating is performed to form a solder layer 9. . As the solder plating resist 8, a resist capable of forming a thick film is used.

Further, as shown in FIG. 29, the solder plating resist 8 is peeled off, and as shown in FIG. 30, the titanium film 4 is etched using the barrier metal 50 and the solder layer 9 as a mask.

Finally, as shown in FIG. 31, the solder layer 9 is reflowed to obtain solder bumps 59 on the semiconductor element 1.

As described above, in the method shown in FIGS. 22 to 31, it is not possible to perform selective etching of tin in the solder and nickel as a barrier metal. The etched state, that is, nickel 5 /
This is performed in a state where the antioxidant film 6 exists in an island shape. In this case, for example, as shown in FIG. 26, the area of the titanium film 4 single layer portion on the semiconductor element is much larger than the area of the island-shaped electrode portion. As a result, the electrical resistance of the titanium film increases.

FIG. 32 is a schematic diagram showing an example of a plating apparatus for performing such electroplating. The cathode electrode 31, which is a current supply source, is provided at the periphery of the wafer 32 for the purpose of expanding the effective area of the wafer 32. Therefore, when plating is performed in a state where the resistance of the underlying electrode is large, current concentrates in the peripheral portion of the cathode electrode 31, the current density is extremely reduced in the central portion of the wafer, and the plating film thickness distribution in the wafer is significantly deteriorated. . Actually, when plating was performed in this state, a film thickness distribution of ± 70% occurred in the wafer surface, and it was not possible to form bumps having a uniform height.

Therefore, when a semiconductor element with a solder bump using a barrier metal having a laminated structure of titanium / nickel / oxidation preventing film obtained by the method shown in FIGS. Due to the difference, there is a problem that a connection failure occurs and the yield of the semiconductor device is low. Furthermore, even if they are connected, there is a problem that the reliability of connection between the semiconductor element and the circuit board is deteriorated due to the difference in the amount of solder.

In addition, as electronic devices become smaller, thinner and more sophisticated, the wiring inside a circuit board on which semiconductor elements are mounted is also becoming denser.

In particular, an LSI such as a microprocessor unit operating at a frequency of several hundred MHz and performing arithmetic processing
In a module board on which a chip is mounted as a bare chip, a high-density multilayer wiring board in which wiring layers having a wiring accommodation capacity per layer of 50 lines / cm or more are multilayered is required.

In order to meet such a demand, instead of a printed wiring board formed by laminating prepregs and a ceramic substrate formed by laminating green sheets, which has been widely used, a vapor deposition is performed on a ceramic or laminated substrate. Method, a wiring layer formed by a sputtering method, a plating method, and the like,
A fine multilayer wiring board (build-up wiring board) in which insulating resin layers formed by applying a varnish-like resin are alternately laminated to form a thin-film wiring layer is being used.

A method of manufacturing a wiring in a conventional general build-up wiring board will be described with reference to FIGS. As shown in FIG. 33, a general copper foil-clad printed wiring board 81 such as CCL-E170 or CCL-H802 formed by laminating prepregs is prepared, and a normal subtractive method is applied on the printed wiring board 81. Thereby, a first wiring layer 82 is formed.

A varnish of an insulating resin selected from, for example, epoxy, polyimide, benzocyclobutene, and Teflon is formed on the substrate 81 and the wiring layer 82 by a coating method such as spin coating or curtain coating. After that, cure and completely polymerize and cure the resin,
An interlayer insulating resin layer 63 as shown in FIG. 34 is formed.

Next, by irradiating a carbon dioxide laser and ablating the resin, as shown in FIG. 35, a via hole 64 for interlayer connection between the wiring layer on the printed wiring board and the upper wiring layer is formed. Formed on the layer 63.

Further, as shown in FIG.
With the aim of increasing the adhesiveness with the wiring layer formed on it,
The resin surface is roughened.

Thereafter, for example, electroless plating, vapor deposition,
Alternatively, a metal film 66 is formed on the resin layer 63 and the wiring layer 82 by a sputtering method or the like, as shown in FIG.

Next, as shown in FIG.
39, a resist pattern 67 is formed, and as shown in FIG. 39, processed by a normal subtractive method to form a second wiring layer 68. By repeating these series of steps as many times as necessary, a multilayer wiring can be formed.

According to this method, a wiring having a width of 50 μm or less and a via hole having a diameter of 50 μm or less can be formed.

In such a conventional manufacturing process, a mechanical roughening method, a chemical roughening method and a chemical roughening method are used as a resin surface roughening method for improving the adhesion between the interlayer insulating resin layer 63 and the wiring layer 68 formed thereon. The roughening method or a combination of both is widely used. The resin surface roughened by such a method increases the contact area between the resin and the metal formed on the resin surface, and further causes an anchoring effect in which the metal enters the concave portion of the resin, thereby increasing the adhesion between the resin and the metal. To increase the reliability of the multilayer wiring board.

As the mechanical roughening method, a buff polishing method or the like is used in which a buff wheel on which abrasive grains such as aluminum oxide and silicon carbide are fixed is rotated and brought into contact with the resin surface to grind the resin surface. FIG. 40 is a view for explaining the insulating resin layer roughened by the buff polishing method. The shape of the surface of the insulating resin layer 53 obtained by this method is streaky irregularities having a low density as shown in FIG. 40. Therefore, even if the surface area increases, a sufficient anchoring effect cannot be obtained. In addition, since the polishing cloth cannot enter the inside of the minute concave pattern such as the via hole, the side wall of the via hole cannot be roughened, and the adhesion between the wiring layer 58 and the insulating resin layer 53 in the via portion is improved. It is difficult to do. For example, when a bismaleimide triazine resin surface is treated by this method and a metal film is formed by electroless copper plating, only a peel strength of 0.04 kg / cm is obtained (Nakakugi et al., "Roughening of BT resin" Improvement of Conductor Adhesion ", Proceedings of the 9th Academic Conference on Circuit Packaging, pp.3
5-36, 1995).

On the other hand, the chemical roughening method comprises swelling, etching and neutralization steps. For example, when the resin is mainly composed of epoxy, sulfuric acid, chromic acid, potassium permanganate or the like is used as an etchant. Used. In FIG.
The figure for demonstrating the insulating resin layer 63 roughened by the chemical roughening method is shown. The shape of the surface of the insulating resin layer 63 obtained by this method is a random unevenness formed at a fine and high density with steps of several μm as shown in FIG. At the interface with 68,
High anchoring effect can be expected. This method also has the effect of simultaneously removing the resin residue remaining at the bottom of the via hole after the formation of the via hole and reducing the via connection resistance. When the surface of the bismaleimide triazine resin is treated by this method and a metal film is formed by electroless copper plating, about 0.6 kg / cm
(Nakakugi et al., “Improvement of conductor adhesion by roughening BT resin”, Proc. Of the 9th Annual Conference of the Japan Society for Circuit Packaging, pp. 35-36, 1995).

However, the wiring of the uppermost layer of the multi-layer substrate on which components are mounted by using solder is required for securing reliability.
A peel strength of at least kg / cm is required. Therefore, the form of the resin surface as shown in FIG. 41 is still insufficient. In addition, the etchant used in this method differs depending on the insulating resin to be treated, and there may be no effective etchant depending on the type of the insulating resin. For example, for polyimide, benzocyclobutene, and Teflon, which have small dielectric constant and dielectric loss and excellent properties, etchants that can form random irregularities of several μm that cause an anchoring effect in close contact with metal are currently available. Is not known.

On the other hand, as one of the chemical roughening methods, a soluble filler is dispersed in a resin used for an insulating resin layer,
There is a method to selectively etch only the filler exposed on the surface after polymerization curing ("Takahashi," Build-up Printed Wiring Board Using Full Additive Method ", Lecture at the 10th Circuit Packaging Academic Lecture Meeting) Proceedings, p
p. 63-64, 1996). FIG. 42 is a view for explaining the interlayer insulating resin layer 73 roughened by another chemical roughening method. The shape of the surface of the insulating resin layer 73 obtained by this method is sufficient to obtain an anchoring effect, and as shown in FIG. In comparison, a higher anchoring effect is exhibited at the interface between the insulating resin layer 73 and the wiring layer 78. The resulting peel strength reaches 1.2 kg / cm or more. In addition, according to this method, the resin surface can be processed similarly for polyimide, benzocyclobutene, and Teflon, which are materials that are difficult to chemically roughen.

However, in the surface structure of the insulating resin obtained by this method, the dispersed filler may impair the inherent properties of the resin. In particular, benzocyclobutene and Teflon have excellent properties such as low dielectric constant, low dielectric loss, and low water absorption, but when these resins are mixed with, for example, an epoxy resin as a filler, they are mixed according to the mixing amount. There is a problem that characteristics are deteriorated.

Further, in order to increase the adhesion between the resin and the metal, a plasma treatment method can be used in addition to the above-described surface roughening method of the insulating resin. In this method, the surface of the insulating resin is exposed to a plasma such as oxygen or nitrogen gas to form irregularities on the surface and to form a polar group such as a carboxyl group on the surface of the insulating resin to increase affinity with a metal. This is a method of increasing the adhesion. According to this method, a polar group can be formed on the surface even for a material such as benzocyclobutene or Teflon, which is difficult to chemically roughen, and it is possible to form a polar group with a metal without mixing a filler that deteriorates resin characteristics. Can be improved.

However, since the apparatus used in this method must generate low-pressure plasma, a high-frequency high-frequency power supply and vacuum equipment are required. This is a very expensive facility compared to the facilities used for Although the adhesion to the wiring metal is improved, the degree is smaller than that of the above-mentioned chemical polishing method. For example, when a bismaleimide triazine resin is processed by a mechanical polishing method and a chemical polishing method and then a copper film is formed, the peel strength of the copper film reaches about 0.6 kg / cm. However, when benzocyclobutene is subjected to a nitrogen plasma treatment to form a copper film, a peel strength of only about 0.2 kg / cm is obtained at the maximum (T-miyagi et. Al., "MCM-D / L using co
pper / photosensitive-BCB multilayer for upper mi
crowave band system ”, Proceedings of 46th Electr
onic Components & Technology Conference, pp.149
-153, 1996). This is because the shape of the surface of the insulating resin layer is not drastically changed by the plasma treatment, and the irregularities formed are as small as 0.1 μm or less, and the anchoring effect cannot be expected. With this peel strength, peeling occurs between the insulating resin and the wiring layer when a thermal cycle test is performed, making it difficult to obtain a highly reliable multilayer wiring.

As described above, when forming a high-density build-up wiring board by using any of the methods, the adhesion between the insulating resin layer and the metal is reduced regardless of the type of the insulating resin layer. It has been difficult to achieve an increasing interface structure. Therefore, it has been difficult to obtain a multilayer wiring board having excellent characteristics and high reliability.

[0046]

As described above, a titanium / nickel / barrier metal structure of an antioxidant layer is suitable for a solder bump used in a semiconductor device.
In the method of etching nickel using a solder bump as a mask, tin is dissolved at the time of patterning of a barrier metal, which causes a reduction in yield after reflow connection and a reduction in connection reliability. In addition, forming an etching protection resist on a bump has a problem that it is difficult to form an uneven pitch and the process is complicated. Furthermore, when a compound semiconductor wafer is used, it is necessary to form a protective resist for nickel etchant, and there is a problem that the process is further complicated.

In a method in which the nickel / oxidation preventing layer of the barrier metal is pre-etched and then the bump is formed by solder plating using only titanium as the cathode metal, the electrical resistance of the underlying electrode increases, and the thickness of the plating film increases. Since the distribution is deteriorated, the yield of the semiconductor device after chip mounting is low, and the connection reliability of the chip is also deteriorated.

Further, when forming a high-density and high-reliability multilayer wiring board, it is necessary to increase the adhesion between the insulating resin and the wiring layer which greatly contributes to the reliability. Polyimide with excellent properties as
When benzocyclobutene or Teflon was used, there was no effective etchant, and when fillers were mixed, the properties deteriorated, so it was difficult to roughen the resin surface by the chemical roughening method. . Even if directional irregularities are formed at the interface between the insulating resin layer and the wiring layer by using a mechanical roughening method by buffing, the adhesion between the insulating resin layer and the wiring layer is reduced. I couldn't make it bigger.

Further, a polar group is formed on the surface of the insulating resin layer by using the plasma processing method, and the interface between the insulating resin layer and the wiring layer, which has increased the chemical bonding force with the metal, has a chemically roughened surface. The adhesion between the resin and the wiring metal is lower than the interface having an anchoring effect using the chemical method, and the processing equipment is also expensive, and it is not possible to manufacture a highly reliable multilayer wiring substrate at low cost. Was.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device having high density and high connection reliability at low cost.

Another object of the present invention is to provide a multilayer wiring board having high density and high reliability.

Still another object of the present invention is to provide a method for manufacturing a multilayer wiring board having high density and high reliability at low cost.

[0053]

According to the present invention, first, a step of forming a base electrode layer on a surface of a semiconductor element, plating a metal layer on the base electrode layer, and patterning the metal layer are performed. Step of forming a bump electrode, and using a granular material injection means by compressed air, using the bump electrode as a mask,
A method of manufacturing a semiconductor device, comprising a step of performing grinding removal by spraying abrasive grains on the base electrode layer.

According to a second aspect of the present invention, in a multilayer wiring board in which insulating resin layers and wiring layers are alternately laminated, the insulating resin layer and the wiring layer are interposed between the insulating resin layers and the wiring layers. To provide a multilayer wiring board, wherein an anchor for connecting the wiring board is embedded.

According to the present invention, thirdly, a step of forming an insulating resin layer on a substrate, and a step of spraying anchor particles on the insulating resin layer by spraying anchor particles by means of compressed-particle injection. And a step of forming a wiring layer on the surface of the insulating resin layer to which the anchor particles are anchored.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION The present inventors have conducted intensive studies in order to manufacture a semiconductor device having a high density and high connection reliability at low cost, and as a result, a barrier metal formed between a solder bump and a semiconductor element has been obtained. By improving the patterning method,
It has been found that excellent effects can be obtained.

Further, the present inventors have improved the interface between the insulating resin layer and the wiring layer in a multilayer wiring board which can be suitably used for a semiconductor device, thereby improving the adhesion between the insulating resin layer and the wiring layer. Have been found to provide a multilayer wiring board having high density and high reliability, and have accomplished the present invention.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a base electrode layer on a surface of a semiconductor element and a step of forming a bump electrode by plating a metal layer on the base electrode layer and patterning the metal layer And a step of performing grinding removal by injecting abrasive grains onto the base electrode layer using the bump electrode as a mask by using a particle ejecting means using compressed air.

According to the method of the present invention, in the patterning of the base electrode, abrasive grains are jetted onto the base electrode layer by using a particle jetting means using compressed air, and the base electrode layer is ground and removed using the bump electrode as a mask. Because it is done by
There is no need for chemical operations such as formation of a resist and use of an environmentally problematic etching solution. Furthermore, this allows elution of the bump electrode component by the etching solution,
In addition, the process is not complicated due to the formation of the protective resist. Further, at the time of electroplating, since the base electrode has a suitable resistance value, there is no large difference in the distribution of bump height.

Therefore, according to the present invention, a semiconductor device having high reliability at low cost and capable of high density can be obtained.

The abrasive grains are preferably made of at least one material selected from the group consisting of aluminum oxide, silicon carbide, diamond, cerium oxide, silicon oxide, chromium oxide, and iron oxide.

The average grain size of the abrasive grains is preferably 0.1 μm
It is more preferably 0.1 μm or more and の or less of the minimum bump interval. When the thickness is 0.1 μm or more, the grinding speed can be increased and the process time can be reduced. Further, when the distance is equal to or less than 1/2 of the minimum bump interval,
It becomes easy to grind the metal layer between bumps having a chirality pitch.

The multilayer wiring board of the present invention has a structure in which insulating resin layers and wiring layers are alternately laminated, and has an insulating resin layer and a wiring layer between the insulating resin layer and the wiring layer. Anchors for connecting the layers are embedded.

The anchor is buried by forming a wiring layer on the surface of the insulating resin layer on which the anchor particles are anchored, for example, by means of spraying compressed air.

Further, the method for manufacturing a multilayer wiring board according to the present invention provides an example of the above-described method for manufacturing a multilayer wiring board. The method includes the steps of forming an insulating resin layer on a substrate, and spraying particles by compressed air. The method includes a step of spraying anchor particles on the insulating resin layer by using means, and a step of forming a wiring layer on the surface of the insulating resin layer on which the anchor particles are anchored.

According to the multilayer wiring board of the present invention, the anchored particles effectively act to increase the adhesion between the surface of the insulating resin layer and the surface of the wiring layer, and high reliability is obtained. Higher densities are possible.

In the method of the present invention, no chemical roughening is performed during the surface treatment of the insulating resin layer. For this reason, it is not necessary to use an etchant which is environmentally problematic, and further, it can be applied to a wide range of insulating resin materials, particularly materials which are weak to etchants such as polyimide, benzocyclobutene, and Teflon. In addition, the method of the present invention does not require an expensive device such as plasma, so that a low-cost, high-density, high-reliability multilayer wiring board can be manufactured.

The anchor is preferably made of at least one material selected from the group consisting of silicon carbide, aluminum oxide, diamond, cerium oxide, silicon oxide, chromium oxide, and iron oxide.

The insulating resin layer is preferably made of at least one material selected from the group consisting of benzocyclobutene, polyimide and Teflon.

The average particle size of the anchor particles is preferably 0.1 μm.
m, and more preferably 0.1 μm or more and 1/2 or less of the minimum bump interval or 1/10 of the thickness of the interlayer insulating resin layer, whichever is smaller. 0.1μ
When it is at least m, a better anchoring effect can be obtained. If the dimension is smaller than 1/2 of the minimum bump interval or 1/10 of the thickness of the interlayer insulating resin layer,
It is possible to sufficiently suppress an increase in wiring resistance and deterioration in characteristics of the insulating resin layer.

For the purpose of obtaining a sufficient anchoring effect and suppressing the deterioration of the characteristics of the interlayer insulating resin, the region where the anchor exists is the interface between the insulating resin layer and the wiring metal. Is preferably within a range not exceeding the average particle size of the anchor.

Further, in the present invention, in order to suppress the generation of dust at the time of production, a certain amount of an anchor material is mixed with a liquid,
It can be blown with compressed gas and anchored on the resin surface.

[0073]

EXAMPLES The present invention will be specifically described below with reference to examples.

An example of a method for manufacturing a semiconductor device according to the present invention will be described below. The present invention is not limited to the following examples, but can be variously modified and used.

FIGS. 1 to 7 are views for explaining an example of a method of manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 1, a connection electrode 2 made of, for example, aluminum was provided on the active element surface, and a semiconductor wafer 1 having a semiconductor element covered with a passivation film 3 except for the connection electrode 2 was prepared. The semiconductor element wafer is not limited to silicon, but may be a compound semiconductor such as gallium arsenide or indium phosphide. Further, the size, the number of electrodes, and the electrode pitch of the semiconductor element can be arbitrarily set and can be appropriately selected.

Next, as shown in FIG.
A titanium film 4, a nickel film 5, and a gold film 6 serving as barrier metals were continuously laminated thereon by, for example, a sputtering method, an evaporation method, or the like.

Here, the uppermost gold film 6 functions as an antioxidant film of a nickel film, and is formed to a thickness of, for example, about 0.05 μm. With this thickness, even if the gold is diffused into the solder by reflowing the solder bumps, the characteristics of the solder are not affected. The nickel film 5 can function as a barrier for preventing diffusion of tin in the solder bump. The film thickness is, for example, about 0.2 μm in consideration of the diffusion speed of tin. Further, the titanium film 4 can function as an adhesive layer for improving the adhesion between the nickel film 5 and the connection electrode 2 and the passivation film 3. Therefore, the thickness of the titanium film 4 may be small, for example, about 0.05 μm. Although the adhesion between nickel and a film such as silicon oxide used as the passivation film 3 is low, peeling of the nickel film 5 can be prevented by forming the titanium film 4 as an adhesive layer. Further, these laminated films simultaneously act as base electrodes for electroplating described later. When an oxide film intervenes at the film interface, these films significantly lower the adhesion. Therefore, it is preferable to continuously form these films without breaking the vacuum for the purpose of preventing the natural oxide film from intervening.

Thereafter, as shown in FIG. 3, a solder plating resist 8 was formed on the gold / nickel / titanium laminated film.

As the solder plating resist 8, a high-viscosity positive resist capable of forming a thick film was used. The resist pattern was formed by first applying a resist by spin coating, pre-baking, and exposing and developing.

Next, the semiconductor wafer 1 on which the solder plating resist 8 was formed was subjected to solder plating. Solder plating can be formed by an electroplating method in which the film formation speed is higher than that of electroless plating and the plating solution can be easily managed. As the electroplating apparatus, a jet plating apparatus as shown in FIG. 32 was used so that the concentration of the plating solution was uniform on the wafer surface. Further, a sulfonic acid-based plating solution was used as the solder plating solution 33. The amounts of tin ions and lead ions were adjusted so that the composition ratio of tin and lead in the film after plating was, for example, 6: 4.

As shown in FIG. 4, a cathode electrode 31 serving as a current supply source is brought into contact with a laminated film composed of a gold film 6, a nickel film 5, and a titanium film 4 and energized in a plating solution 33, whereby plating is performed. A solder film 9 was formed in the opening of the resist 8. The cathode electrode 31 was provided around the wafer 32 for the purpose of expanding the effective area of the wafer. The laminated film including the gold film 6, the nickel film 5, and the titanium film 4 was used as a base electrode in plating. In this base electrode, nickel, which has a lower resistivity than titanium, is formed over the entire surface of the wafer with a thickness of 0.2 μm, so that the sheet resistance of the base electrode is low, and current concentration around the cathode electrode is reduced. As a result, within the wafer, a plating film thickness distribution within ± 10% (for a 5-inch diameter wafer) was obtained.

Subsequently, as shown in FIG. 5, the solder plating resist 8 was dissolved and peeled off with acetone.

Further, the laminated film consisting of the gold film 6, the nickel film 5, and the titanium film 4 other than under the bumps was removed. In the method of the present invention, as the removing method, a method of injecting abrasive grains at a high pressure to grind by using a granule ejecting means by compressed air is used.

This grinding could be performed, for example, by using a granule injection device using compressed air as shown in FIG. As shown in the figure, the particle ejecting apparatus 60 mainly includes a mechanism for ejecting the high-pressure air 41 together with the solution 39, and a stage 37 for mounting the wafer 38 and moving the wafer 38 in a predetermined direction at a predetermined speed. Was. As the solution 39, for example, a solution in which aluminum oxide abrasive grains having an average particle diameter of 1 μm were mixed with water at a rate of 100 g / L was used. Solution 39 contains 5 kg /
The high-pressure air 41 of cm ² is sucked and mixed by the negative pressure generated when the high-pressure air 41 is injected from the nozzle 40, and is injected together with the air from the nozzle 40. Stage 3 on which wafer 38 is mounted
7 can be moved at a constant speed in the XY directions by a controlled stepping motor.

The distance between the wafer 38 and the nozzle 40 is 20 m
m, the moving speed of the stage 37 in the X direction is 10 mm /
And the step distance in the Y direction is 10 mm, the wafer 1
By spraying the solution on the laminated film exposed on the surface, as shown in FIG. 6, the laminated film composed of gold 6, nickel / 5, and titanium 4 can all be ground and removed. After the removal of the laminated film, the passivation film 3 is exposed. The passivation film 3 is not completely removed because the passivation film 3 has a higher hardness than the metal film and is thicker than the laminated film. However, traces due to grinding remain on the surface of the passivation film 3, and random irregularities having a step of about 0.5 μm may be formed. A similar trace may be left on the surface of the solder bump 9, but it has no effect on the composition ratio of tin and lead in the solder. Since the amount of solder grinding is small and uniform grinding is performed, there is no change in the film thickness distribution.

Thereafter, in order to remove abrasive grains remaining on the surface, the wafer surface was washed with high-pressure water using pure water for the solution with the same apparatus as the apparatus shown in FIG.

The semiconductor wafer with bumps thus obtained was passed through a reflow furnace to reflow the solder bumps 9 to obtain a semiconductor element having bump electrodes formed thereon as shown in FIG. At the time of reflow, a flux was applied for the purpose of removing a natural oxide film formed on the solder surface. The reflow temperature is, for example, 24
It was set to 0 ° C. By this step, the solder bump 9 becomes spherical, and the surface irregularities formed on the bump surface during the grinding of the laminated film can be completely eliminated.

Next, a comparison was made between the semiconductor device using the solder bumps thus obtained and a semiconductor device using the conventional solder bump.

Composition distribution Sample a was formed by etching a barrier metal using a solder bump as a mask, sample b was formed by patterning a nickel film of a barrier metal and then forming a solder bump, and sample c was formed as a sample c. Each of those formed using the method of the present invention was prepared.

The samples a, b and c were measured for the solder composition by the ICP method, and the distribution in the diameter direction within the 5-inch wafer was evaluated.

As a result, FIG. 9 is a graph showing the relationship between the distance from the center in the 5-inch wafer and the composition of the obtained bump. In the figure, a graph 901 indicates a sample a
3 is a graph showing a composition distribution of the present invention. Graph 902 is a graph showing the composition distribution of sample b. Graph 903 is a graph showing the composition distribution of sample c.

Bump Height The distribution of the above samples a, b, and c in the diameter direction in a 5-inch wafer was measured.

FIG. 10 is a graph showing the relationship between the distance from the center of the 5-inch wafer and the height of the obtained bump.

In the figure, the graph 101 is the sample a, the graph 10
2 shows the bump height distribution of sample b, and graph 103 shows the bump height distribution of sample c.

As shown in FIG. 9 and FIG.
It is difficult to say that both the composition distribution and the height distribution are good, and the height distribution of the sample b is extremely poor. On the other hand, with respect to the sample c formed according to the present invention, both the composition distribution and the height distribution were the most stable among the three samples.

Connection reliability test The above-mentioned samples a, b and c were diced into chips,
Flip chip mounting was performed on the surface of a build-up wiring board in which an insulating layer and a wiring layer were laminated on a glass epoxy board.
In this test, the chip and the substrate were sealed with a resin in order to reduce the stress generated at the connection part due to the difference in the coefficient of thermal expansion between the chip and the substrate. As the sealing resin, an epoxy resin containing a bisphenol-based epoxy, an imidazole curing catalyst, an acid anhydride curing agent, and a spherical quartz filler was used.

A connection reliability test was performed on the obtained connection structure as follows. 10mm as semiconductor element
A chip having a size of × 10 mm was prepared, and a chain (the number of bumps: 256) in which the wiring on the chip and the wiring on the substrate were connected by a bump having a diameter of 80 μm was prepared and subjected to a temperature cycle.
The test conditions are -55 ° C (30 minutes)-25 ° C (5 minutes)-12
The test is performed at 5 ° C. (30 minutes) to 25 ° C. (5 minutes), and the resistance of the circuit end is measured every 200 cycles. Examined.

As a result, FIG. 11 is a graph showing the relationship between the number of cycles and the cumulative failure rate. In the figure, graph 111 is sample a, graph 112 is sample b, and graph 1
13 shows the result of sample c.

As shown in FIG. 11, the sample a
In the 00 cycle, the defective rate became 50%, and the sample b was about 22%.
The defective rate reached 50% in 00 cycles. These defects are caused by the stress due to thermal expansion due to the distribution of the composition and height of the bumps, which concentrates on the portions where the composition is not uniform or on the bumps with a small amount of solder. On the other hand, Sample c showed no defect until around 3000 cycles and showed the highest connection reliability. In addition, as a result of observing the cross section of the sample after the test, in samples a and b, peeling occurred partially between the sealing resin and the passivation film on the chip, but in sample c, irregularities were observed on the surface of the passivation film. Since it was formed and the adhesion to the resin was high, no peeling occurred.

Furthermore, when comparing the number of steps in the bump manufacturing process, the sample a had 7 steps, the sample b had 10 steps, and the sample c had
Then, there are seven steps. However, sample a requires a wafer protection resist forming step in addition to the barrier metal patterning for the compound semiconductor wafer. Therefore, the step of the sample c is substantially the smallest step. That is, the present invention can reduce the number of bump forming steps to 70% of the conventional one at the maximum, and can greatly contribute to improvement in manufacturing yield and reduction in manufacturing cost.

The present invention is not limited to the above-described embodiment, but can be implemented with modifications without departing from the scope of the invention. For example, in the step of injecting abrasive grains to grind and remove the metal film, the abrasive may be injected in a powder state without being mixed with a liquid.

The wafer, the barrier metal, the solder bump, and the resist can be used with various changes in the material, composition, dimensions, and the like, and the conditions for spraying the abrasive grains are not limited to the above examples.

Next, an example of the multilayer wiring board of the present invention will be described.

FIG. 12 is a schematic sectional view showing an example of the multilayer wiring board according to the present invention. As shown in FIG. 12, the multilayer wiring board includes a base 81, a first wiring layer 82 formed on the base 81, and an insulating resin layer 83 formed on the first wiring layer 82. And a second wiring layer 88 formed on the insulating resin layer 83. In particular, the interface between the interlayer insulating resin layer 83 and the wiring layer 88 has random irregularities with fine and high density. Anchors 8 to increase and increase adhesion
5 are provided.

Such a multilayer wiring board can be manufactured, for example, by the following method.

FIGS. 13 to 19 are views for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

The base material 81 on which the multilayer wiring is formed is made of a semiconductor substrate such as silicon or gallium arsenide, a laminated substrate mainly composed of epoxy, bismaleimide triazine (BT), or the like; And the like can be used. Here, a copper clad laminate (CCL) in which a 18 μm thick copper foil was formed on both sides of the BT laminate was used as a base material.

The first wiring layer 82 was formed by a usual subtractive method. First, a liquid positive type resist was spin-coated on a copper foil on the surface of a base material 81 for forming a multilayer wiring to form a resist film having a thickness of about 5 μm. Thereafter, baking was performed at 90 ° C. for 30 minutes, exposure and phenomenon were performed, and a wiring pattern was formed with a resist film. Subsequently, the copper foil other than the wiring pattern was removed by etching with a mixed solution comprising ammonium persulfate, sulfuric acid, and ethanol. further,
By dissolving and removing the resist film with acetone, as shown in FIG.
2 was formed.

Subsequently, as shown in FIG. 14, an insulating resin layer 83 to be an interlayer insulating layer is formed. As the insulating resin, photosensitive benzocyclobutene or the like was used. A varnish of this resin was applied on a substrate by spin coating or curtain coating to form a coating film having a thickness of about 15 μm.
After that, baking was performed at 80 ° C. for 20 minutes and dried.

Further, as shown in FIG. 15, exposure and development are performed to form a via hole 84 for connecting the first wiring and the second wiring in the insulating resin layer 83. After curing at 250 ° C. for 30 minutes, the resin was cured. For example, when a non-photosensitive resin is used as an interlayer resin layer, curing is performed after varnish application, and then a carbon dioxide laser is irradiated to ablate the resin to form via holes in the resin.

Next, the resin layer 8 formed as described above
The three surfaces were treated to increase the adhesion between the second wiring and the resin. This processing was performed using an apparatus similar to the apparatus shown in FIG. Here, a solution 39 in which silicon carbide having an average particle diameter of 1 μm was mixed with water at a rate of 100 g / L was used. 5 kg / cm ²
The high-pressure air was sucked and mixed by the negative pressure generated when the high-pressure air was injected from the nozzle 40, and was injected together with the air from the nozzle. The stage 37 on which the substrate 81 is mounted was moved at a constant speed in the X and Y directions by a controlled stepping motor.

The distance between the substrate 81 and the nozzle 40 is 20 mm
And the moving speed of the substrate 81 in the X direction is 20 mm / min.
By setting the step distance in the direction to 10 mm and injecting the solution onto the resin layer 83 on the substrate surface, as shown in FIG.
Anchor particles 85 made of silicon carbide were uniformly anchored on the entire surface of the substrate.

The anchor particles 85 anchored on the resin surface accounted for a few percent of the whole particles sprayed on the surface of the resin layer 3 and most of the particles were dropped off. Traces were left on the surface of the resin 83 other than the anchor particles 85 anchored, and random irregularities having a step of about 0.5 μm were formed.

In some cases, a thin film of benzocyclobutene having a thickness of about 1 μm was left at the bottom of the via hole 84. However, in this anchoring step, particles were scraped off by the collision of particles and could be sufficiently removed. At the same time, the surface of the first wiring 82 exposed at the bottom of the via hole 84 was roughened by collision of particles.

First wiring 82 exposed at the bottom of via hole 84
Copper has a hardness of about 100 Hv, which is three times or more the hardness of the resin. Therefore, the probability that the anchor particles 5 are anchored is low, but the surface of the wiring exposed with a mixed solution of sulfuric acid and hydrogen peroxide is used. It is preferable to perform light etching to completely remove the particles 5.

Subsequently, as shown in FIG. 17, a laminated film 86 of a titanium film and a copper film is formed on the insulating resin layer 3 on which anchor particles are anchored and random irregularities are formed, for example, by a sputtering method. Formed. Note that this laminated film 86
Was made to have a total thickness of about 2 μm, for example.
Here, the copper film acted as a plating cathode, and the titanium film acted as an adhesive layer for increasing the adhesion between the copper film and the resin surface. Therefore, the thickness of the titanium film may be thin, for example, about 0.1 μm. In this case, the titanium surface is easily oxidized, without breaking the vacuum,
It is preferable to continuously form an upper copper film. By forming the titanium film and the copper film in this way,
Intervention of a natural oxide film can be prevented, and a wiring having high adhesion and low resistance can be obtained.

Next, a resist was applied on the laminated film 86 by spin coating and baked to form a resist layer 87 having a thickness of about 5 μm. Thereafter, as shown in FIG. 18, the resist layer 87 was processed into a wiring pattern by exposure and development.

Thereafter, a copper film other than the wiring pattern is formed by using ammonium persulfate, sulfuric acid,
Etching was performed with a mixed solution of ethanol. Further, the titanium film was removed by etching with a mixed solution comprising EDTA, ammonia, and hydrogen peroxide solution. Resist film 87
Was dissolved and removed with acetone to form a second wiring layer 88 as shown in FIG.

The steps shown in FIG. 13 to FIG.
By repeating the necessary number of wiring layers, a multilayer wiring of three or more layers can be formed.

In the multilayer wiring board 90 formed by the above steps, the anchor particles 85 made of silicon carbide having an average particle diameter of 1 μm are interposed at the interface between the interlayer insulating resin layer 83 and the wiring layer 88. The anchor particles are composed of the insulating resin layer 83 and the wiring layer 8.
8 is anchored at both, and as a result,
The adhesion between the insulating resin layer 83 and the wiring metal 88 increases.

Next, the following comparison was made between a multilayer wiring board obtained in the same manner as described above and a conventional multilayer wiring board.

Adhesion Strength First, samples 1 to 4 were prepared as conventional multilayer wiring boards. Sample 1 was a benzocyclobutene surface as formed, Sample 2 was a surface roughened mechanically by a # 800 buff wheel, Sample 3 was a surface treated with carbon tetrafluoride and nitrogen plasma, and Sample 4 was an epoxy-based Is a multilayer wiring board in which 5 wt% of the filler is mixed and the filler exposed on the surface is etched and roughened with a potassium permanganate solution to form a wiring on the roughened surface. Sample 5
The multilayer wiring board according to the present invention was used.

For samples 1 to 5, the wiring layer was 90 °
The film was peeled off by a peel test, and the adhesion strength was measured.

FIG. 20 is a graph showing the result of comparing the adhesion strength between the insulating resin layer and the wiring layer between the conventional multilayer wiring board and the multilayer wiring board of the present invention. As shown in FIG. 20, in samples 1 to 3, the peel strength did not reach 0.3 kg / cm. However, in Samples 4 and 5, sufficient adhesion strength was obtained.

Various Characteristics of Multilayer Wiring Board Next, for samples 1 to 5, relative permittivity, dielectric loss,
The volume resistivity, water absorption, and 50 μm ² via resistance were measured. In addition, each measurement was performed as follows.

Relative permittivity The relative permittivity is determined by forming circular electrodes having a diameter of 5 mm and a diameter of 3.8 mm so as to face the first and second wiring layers, respectively, and connecting an impedance analyzer between the two electrodes. The capacity at 1 MHz was measured, and further obtained by converting the measured capacity.

Dielectric Loss Dielectric loss is measured at 1 MHz by forming circular electrodes having a diameter of 5 mm and a diameter of 3.8 mm so as to face the first and second wiring layers, respectively, and connecting an impedance analyzer between both electrodes. It was measured.

Volume resistivity A circular electrode having a diameter of 5 mm and a diameter of 3.8 mm is formed so as to face the first and second wiring layers, respectively. An insulation resistance meter is connected between both electrodes, and a DC voltage of 50 V is applied. After one minute, the resistance was measured. The volume resistivity was determined by converting from the resistance value at that time.

Water Absorption The water absorption was measured by a method shown in JIS C 6481, 5.14 using a multilayer wiring board formed using a silicon wafer as a substrate and using the same portion of each sample.

50 μm ² Via Resistance For the formed 50 μm ² via, a four-terminal method was used.
Via resistance was measured. 100 mA was applied as a direct current.

The results obtained by the above measurement are shown in Table 1 below.

[0133]

[Table 1]

As shown in Table 1, the properties of the interlayer insulating resin except for the via resistance were exactly the same with respect to the samples 1 to 3, but the sample 4 containing the filler was the same as the sample 4.
It was found that all of the dielectric constant, dielectric loss tangent, insulation resistance, and water absorption were deteriorated. On the other hand, as is apparent from Sample 5, in the multilayer wiring board of the present invention, since the anchoring particles exist only at the resin-metal interface, good properties are obtained without adversely affecting the properties of the resin. Was done.

The via resistance was approximately the same for Sample 3 and Sample 5, and about 100 times higher for the other samples. When the cross sections of the samples were observed,
In Samples 2 and 4, the resin residue remained at the bottom of the via hole, whereas in Samples 3 and 5, the residue was completely removed. This indicates that the use of the method of the present invention can effectively remove the resin residue at the bottom of the via hole as in the case of the plasma treatment.

Reliability Next, a reliability test was performed on Samples 4 and 5.
In this test, a via chain (the number of vias: 1000) was formed through a via hole having a diameter of 40 μm with two-layer wiring and subjected to thermal shock. The test method used was a severe test of JIS C-5012, immersion in 260 ° C silicone oil for 10 seconds per transfer 15 seconds -20 ° C trichlorethylene immersion for 20 seconds per transfer 1
With 5 seconds as one cycle, the resistance at the circuit end was measured every 20 cycles, and the rate of change in resistance was determined.

FIG. 21 is a graph showing the results of such a reliability test.

In the figure, the graph 211 is the sample 4, the graph 21
2 shows the results of Sample 5, respectively.

As shown in FIG. 21, in the sample 4 which is a conventional multilayer wiring board, the resistance change rate is increased from about 100 cycles to about 150 cycles, but in the sample 5 which is a multilayer wiring board of the present invention, 200 cycles or more. Withstands the thermal shock of
It was found that the reliability was improved. This result is due to the fact that the adhesion between the interlayer insulating resin of the substrate and the wiring layer according to the present invention has increased, and that the characteristics of the interlayer insulating resin do not deteriorate.

The present invention is not limited to the above-described embodiment, but can be implemented with modifications without departing from the scope of the invention. For example, as the first wiring formation method, an evaporation method, a sputtering method, an electroplating method, an electroless plating method, or the like may be used. Similarly, for the second wiring forming method, a vapor deposition method, an electroplating method, an electroless plating method, or the like can be used.

The base material, wiring, insulating resin, resist, and etching solution can be used with various changes in the material, dimensions, and the like. Further, the conditions for anchoring particles are not limited to those described above. That is a must.

[0142]

According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having high density and high connection reliability can be manufactured at low cost.

According to the multilayer wiring board of the present invention, a highly reliable wiring can be obtained, and a high density wiring can be realized.

Further, according to the method for manufacturing a multilayer wiring board of the present invention, a multilayer wiring board having high density wiring and high reliability can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a schematic view showing an example of a particle ejecting apparatus that can be used in the present invention.

FIG. 9 is a graph showing the relationship between the distance from the center of the wafer and the composition of the obtained bump.

FIG. 10 is a graph showing the relationship between the distance from the center of the wafer and the height of the obtained bump.

FIG. 11 is a graph showing a result of a connection reliability test of the semiconductor device;

FIG. 12 is a schematic cross-sectional view illustrating an example of a multilayer wiring board according to the present invention.

FIG. 13 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 14 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 15 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 16 is a diagram illustrating each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 17 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention;

FIG. 18 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 19 is a view for explaining each step of an example of the method for manufacturing a multilayer wiring board according to the present invention.

FIG. 20 is a graph showing the adhesion strength between an insulating resin layer and a wiring layer.

FIG. 21 is a graph showing the results of a reliability test of a multilayer wiring board;

FIG. 22 is a view for explaining an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 23 is a view illustrating an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 24 is a view for explaining an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 25 is a view for explaining an example of a conventional manufacturing process of a bump connection electrode of a semiconductor element.

FIG. 26 is a view for explaining an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 27 is a view for explaining an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 28 is a view for explaining an example of a conventional manufacturing process of a bump connection electrode of a semiconductor element.

FIG. 29 is a view illustrating an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 30 is a view for explaining an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 31 is a view illustrating an example of a manufacturing process of a conventional bump connection electrode of a semiconductor element.

FIG. 32 is a schematic view illustrating an example of a plating apparatus.

FIG. 33 is a view for explaining an example of a conventional manufacturing process of a multilayer wiring board;

FIG. 34 is a view illustrating an example of a conventional manufacturing process of a multilayer wiring board.

FIG. 35 is a view for explaining an example of a conventional multi-layer wiring board manufacturing process.

FIG. 36 is a view for explaining an example of a conventional manufacturing process of a multilayer wiring board;

FIG. 37 is a view for explaining an example of a conventional manufacturing process of a multilayer wiring board;

FIG. 38 is a view for explaining an example of a conventional manufacturing process of a multilayer wiring board.

FIG. 39 is a view for explaining an example of a conventional manufacturing process of a multilayer wiring board;

FIG. 40 is a diagram illustrating an insulating resin layer roughened by a buff polishing method.

FIG. 41 is a view illustrating an insulating resin layer roughened by a chemical roughening method.

FIG. 42 is a view illustrating an insulating resin layer roughened by another chemical roughening method.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Yukio Kizaki 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Production Technology Research Institute (72) Inventor Hiroshi Yamada 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Address Co., Ltd., Toshiba Production Technology Laboratory

Claims (7)

[Claims] 1. A step of forming a base electrode layer on a surface of a semiconductor element, a step of plating a metal layer on the base electrode layer, and forming a bump electrode by patterning the metal layer; A method for manufacturing a semiconductor device, comprising a step of performing grinding removal by injecting abrasive grains onto the base electrode layer using the bump electrode as a mask by using body injection means. 2. The abrasive grain is at least one selected from the group consisting of aluminum oxide, silicon carbide, diamond, cerium oxide, silicon oxide, chromium oxide, and iron oxide.
2. The method according to claim 1, wherein the semiconductor device is made of two materials. 3. In a multilayer wiring board in which insulating resin layers and wiring layers are alternately laminated, an anchor for connecting the insulating resin layer and the wiring layer is provided between the insulating resin layer and the wiring layer. A multilayer wiring board characterized by having embedded therein. 4. The anchor according to claim 3, wherein the anchor is embedded by forming a wiring layer on the surface of the insulating resin layer on which the anchor particles have been anchored, using a means of spraying compressed air. Multilayer wiring board. 5. The anchor according to claim 3, wherein the anchor is made of at least one material selected from the group consisting of silicon carbide, aluminum oxide, diamond, cerium oxide, silicon oxide, chromium oxide, and iron oxide. The multilayer wiring board as described in the above. 6. The multilayer wiring board according to claim 3, wherein the insulating resin layer is made of at least one material selected from the group consisting of benzocyclobutene, polyimide, and Teflon. 7. A step of forming an insulating resin layer on the substrate, a step of spraying anchor particles using compressed particle air jetting means, and anchoring the insulating resin layer. A method of manufacturing a multilayer wiring board, comprising a step of forming a wiring layer on the surface of the anchored insulating resin layer.