JP2006156910A - Semiconductor device - Google Patents

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JP2006156910A
JP2006156910A JP2004349043A JP2004349043A JP2006156910A JP 2006156910 A JP2006156910 A JP 2006156910A JP 2004349043 A JP2004349043 A JP 2004349043A JP 2004349043 A JP2004349043 A JP 2004349043A JP 2006156910 A JP2006156910 A JP 2006156910A
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layer
solder
semiconductor substrate
semiconductor device
free solder
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Kimiji Kayukawa
君治 粥川
Shoji Miura
昭二 三浦
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Denso Corp
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Denso Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of assuring a sufficient bonding lifetime when a semiconductor substrate is soldered to a header or the like by using Sn-based Pb free solder. <P>SOLUTION: Inverse sputtering is executed to a forming face S of the semiconductor substrate 1 in order to remove a natural oxide film (not illustrated in Figure) formed on the forming face S of the semiconductor substrate 1. Next, an Al layer 2, a Ti layer 3, and an Ni layer 4 are formed on the forming face S of the semiconductor substrate 1 by sputtering. A protection film, for example, made of unillustrated Au or the like with a thickness of about 30-50 nm is formed on the Ni layer 4 by the sputtering. After that, a Ti-Ni layer 5 as a solder barrier layer is formed to the interface between the Ti layer 3 and the Ni layer 4 by executing heat treatment with a quartz tube type heat treatment furnace of a nitrogen atmosphere. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、複数の金属層からなる電極を有する半導体装置に関するものである。   The present invention relates to a semiconductor device having an electrode composed of a plurality of metal layers.

従来より、例えば特許文献１に示すように、シリコン基板の裏面に複数の金属層からなる裏面電極１０５を備えた半導体ペレット１００を半田１０６によってヘッダ１０７に半田接合する半導体装置がある。図７は特許文献１の半導体装置の構造を示す要部断面図である。   Conventionally, as shown in Patent Document 1, for example, there is a semiconductor device in which a semiconductor pellet 100 having a back electrode 105 made of a plurality of metal layers on the back surface of a silicon substrate is solder-bonded to a header 107 by solder 106. FIG. 7 is a cross-sectional view of the main part showing the structure of the semiconductor device of Patent Document 1.

この従来の半導体装置は、ゲート電極などを有する半導体ペレット１００と裏面電極１０５を備える。この裏面電極１０５は、シリコンとの接合性が良いＡｌ層１０１、シリコンの半田側への拡散防止のためのＴｉ層１０２、半田１０６のシリコン基板側への拡散防止のためのＮｉ層１０３、Ｎｉ層１０３の酸化防止のためのＡｕ層１０４を備える。そして、シリコンとＡｌ層１０１との間にシリコン−Ａｌ合金層を形成することによって剥離を低減すると共に、各金属層間に合金層を形成することによって各金属層間での接触抵抗を低減するものである。
特許第３３３９５５２号公報 This conventional semiconductor device includes a semiconductor pellet 100 having a gate electrode and the like and a back electrode 105. The back electrode 105 includes an Al layer 101 having good bonding property to silicon, a Ti layer 102 for preventing diffusion of silicon to the solder side, a Ni layer 103 for preventing diffusion of solder 106 to the silicon substrate side, Ni An Au layer 104 for preventing oxidation of the layer 103 is provided. Then, the silicon-Al alloy layer is formed between the silicon and the Al layer 101 to reduce peeling, and the alloy layer is formed between the metal layers to reduce the contact resistance between the metal layers. is there.
Japanese Patent No. 3339552

しかしながら、近年、環境汚染などの問題から、Ｓｎ−Ｐｂ系半田に代わってＰｂを使用しないＰｂフリー半田（Ｓｎ系Ｐｂフリー半田など）の使用が進められている。このＰｂフリー半田（Ｓｎ系Ｐｂフリー半田など）を用いて半導体電極を下地基板に半田接合する場合には、接合寿命が短くなるという問題があった。   However, in recent years, use of Pb-free solder (such as Sn-based Pb-free solder) that does not use Pb instead of Sn-Pb-based solder has been promoted due to problems such as environmental pollution. When the semiconductor electrode is solder-bonded to the base substrate using this Pb-free solder (Sn-based Pb-free solder or the like), there is a problem that the bonding life is shortened.

本発明は、上記問題点に鑑みなされたものであり、半導体基板を下地基板などにＳｎ系Ｐｂフリー半田を用いて半田接合する場合に、充分な接合寿命を保証できる半導体装置の提供を目的とするものである。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can guarantee a sufficient bonding life when a semiconductor substrate is solder-bonded to a base substrate or the like using Sn-based Pb-free solder. To do.

上記目的を達成するために請求項１に記載の半導体装置では、Ａｌ膜が形成された半導体基板に、Ａｌ膜上に接着層として形成された第１の金属層と、第１の金属層とＮｉもしくはＣｕとの混合層からなる半田バリア層とを備える半導体電極であって、半導体電極をＳｎ系Ｐｂフリー半田により下地基板に半田接合することを特徴とするものである。   In order to achieve the above object, in the semiconductor device according to claim 1, a first metal layer formed as an adhesive layer on the Al film on the semiconductor substrate on which the Al film is formed, a first metal layer, A semiconductor electrode including a solder barrier layer made of a mixed layer of Ni or Cu, wherein the semiconductor electrode is solder-bonded to a base substrate with Sn-based Pb-free solder.

このように、半導体基板と第１の金属層との間に半導体基板及び第１の金属層との接触抵抗の小さいＡｌ膜を形成することによって、半導体基板とＡｌ膜との間、及びＡｌ膜と第１の金属層との間での接触抵抗を小さくすることができる。したがって、半導体基板と第１の金属層との間をオーミック接続の状態とすることができる。   Thus, by forming an Al film having a low contact resistance between the semiconductor substrate and the first metal layer between the semiconductor substrate and the first metal layer, the Al film is formed between the semiconductor substrate and the Al film. The contact resistance between the first metal layer and the first metal layer can be reduced. Therefore, an ohmic connection can be established between the semiconductor substrate and the first metal layer.

また、半田バリア層として、第１の金属層とＮｉもしくはＣｕを含む混合層（合金層）を用いることによって第１の金属層へのＳｎの到達時間を長くできることを本発明者は実験により見出した。よって、Ａｌ膜が形成された半導体基板とベース基板とをＳｎ系Ｐｂフリー半田を用いて接合する場合でも充分な接合寿命を保証できる。   Further, the inventors have found through experiments that the arrival time of Sn to the first metal layer can be increased by using the first metal layer and a mixed layer (alloy layer) containing Ni or Cu as the solder barrier layer. It was. Therefore, even when the semiconductor substrate on which the Al film is formed and the base substrate are bonded using Sn-based Pb-free solder, a sufficient bonding life can be guaranteed.

また、請求項２に示すように、第１の金属層をＴｉとすることによって、ＮｉもしくはＣｕとの接合性を良好にすることができる。   In addition, as shown in claim 2, when the first metal layer is made of Ti, the bondability with Ni or Cu can be improved.

また、請求項３に記載の半導体装置では、半田バリア層とＳｎ系Ｐｂフリー半田との間にＮｉもしくはＣｕを備えることを特徴とするものである。これによれば、半田バリア層とＳｎ系Ｐｂフリー半田との間にＮｉ層もしくはＣｕ層がある分第１の金属層へのＳｎの到達時間を長くすることができる。   The semiconductor device according to claim 3 is characterized in that Ni or Cu is provided between the solder barrier layer and the Sn-based Pb-free solder. According to this, the arrival time of Sn to the first metal layer can be increased by the presence of the Ni layer or the Cu layer between the solder barrier layer and the Sn-based Pb-free solder.

また、請求項４に記載の半導体装置では、半田バリア層とＳｎ系Ｐｂフリー半田との間に第１の金属層とＮｉもしくはＣｕとＳｎとからなる３元混合層を備えることを特徴とするものである。これによれば、第１の金属層とＮｉ／ＣｕとＳｎとからなる３元混合層及び半田バリア層へＳｎが拡散した場合でも、第１の金属層の界面には、上記３元混合層が形成されることになる。従って、各層の元素で構成された３元混合層が界面に存在するので各層間で結合しやすく接合強度が向上する。   According to a fourth aspect of the present invention, the semiconductor device includes a ternary mixed layer made of Ni or Cu and Sn between the solder barrier layer and the Sn-based Pb-free solder. Is. According to this, even when Sn diffuses to the first metal layer, the ternary mixed layer composed of Ni / Cu and Sn, and the solder barrier layer, the ternary mixed layer is present at the interface of the first metal layer. Will be formed. Accordingly, since a ternary mixed layer composed of the elements of each layer exists at the interface, bonding between the layers is facilitated and bonding strength is improved.

また、請求項５に記載の半導体装置では、半田バリア層の厚さは１９ｎｍ以上であることを特徴とするものである。これによれば、半田バリア層の厚さは、最低１９ｎｍあれば充分な接合寿命を得ることができる。   In the semiconductor device according to claim 5, the thickness of the solder barrier layer is 19 nm or more. According to this, a sufficient bonding life can be obtained if the thickness of the solder barrier layer is at least 19 nm.

以下、本発明の実施の形態における半導体装置に関して、図面に基づいて説明する。図１は本発明の実施の形態に係わる、半導体装置の構造を示す要部断面図である。図１において、１は半導体基板、２はＡｌ層、３はＴｉ層、４ａはＮｉ部、５はＴｉ−Ｎｉ層、６はＳｎ系Ｐｂフリー半田、７はリードフレームである。 Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a principal part showing the structure of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is an Al layer, 3 is a Ti layer, 4a is a Ni portion, 5 is a Ti-Ni layer, 6 is a Sn-based Pb-free solder, and 7 is a lead frame.

半導体基板１は、Ｓｉ基板上にゲート、ソース領域などが形成されたパワーＭＯＳトランジスタなどである。なお、半導体基板１は、パワーＭＯＳトランジスタに限定されるものではなく、縦型ＩＧＢＴやダイオードなどであってもよい。   The semiconductor substrate 1 is a power MOS transistor in which a gate, a source region, and the like are formed on a Si substrate. The semiconductor substrate 1 is not limited to a power MOS transistor, and may be a vertical IGBT or a diode.

Ａｌ層２は、半導体基板１とＴｉ層３との間がオーミック接続となるようにするためである。半導体基板１としてＮ型半導体基板を用いる場合、半導体基板１とＴｉ層３との間でオーミック接続が可能である。しかし、半導体基板１としてＰ型半導体基板を用いる場合、半導体基板１とＴｉ層３との間でショットキー接続となる可能性があった。そこで、Ｐ型半導体基板と接触抵抗の小さいＡｌ層２を半導体基板１とＴｉ層３との間に設ける。当然のことながら、Ａｌ層２とＴｉ層３とは金属でありオーミック接続となるので、半導体基板１とＴｉ層３との間をオーミック接続の状態とすることができる。   The Al layer 2 is for making an ohmic connection between the semiconductor substrate 1 and the Ti layer 3. When an N-type semiconductor substrate is used as the semiconductor substrate 1, an ohmic connection can be made between the semiconductor substrate 1 and the Ti layer 3. However, when a P-type semiconductor substrate is used as the semiconductor substrate 1, there is a possibility that Schottky connection is made between the semiconductor substrate 1 and the Ti layer 3. Therefore, an Al layer 2 having a low contact resistance with the P-type semiconductor substrate is provided between the semiconductor substrate 1 and the Ti layer 3. As a matter of course, the Al layer 2 and the Ti layer 3 are metal and are in ohmic connection, so that the semiconductor substrate 1 and the Ti layer 3 can be in an ohmic connection state.

Ｔｉ層３は、本発明における第１金属層に相当するものである。このＴｉ層３は、Ｔｉ−Ｎｉ層５とＡｌ層２が形成された半導体基板１との接着層として機能する。なお、Ｔｉ層３は、他にもＭｏ、Ｗ、Ｃｏ、Ｖ、Ｃｒ、ＴｉＷなどであっても、接着層としては充分であるが、Ｎｉ層４もしくはＣｕとの接合性が良好なＴｉを用いるのが好ましい。   The Ti layer 3 corresponds to the first metal layer in the present invention. The Ti layer 3 functions as an adhesive layer between the Ti—Ni layer 5 and the semiconductor substrate 1 on which the Al layer 2 is formed. The Ti layer 3 may be Mo, W, Co, V, Cr, TiW, or the like, but it is sufficient as an adhesive layer, but Ti having good bondability with the Ni layer 4 or Cu is used. It is preferable to use it.

Ｎｉ部４ａは、後ほど説明するＴｉ−Ｎｉ層５を形成するために形成されたＮｉ層４のうち、Ｔｉ層３と合金化されずに残ったものである。なお、Ｎｉ部４ａ（Ｎｉ層４）は、これに限定されるものではなくＣｕであってもよい。   The Ni portion 4a is the one that remains without being alloyed with the Ti layer 3 in the Ni layer 4 formed to form the Ti—Ni layer 5 described later. The Ni portion 4a (Ni layer 4) is not limited to this and may be Cu.

Ｔｉ−Ｎｉ層５は、本発明における半田バリア層に相当するものであり、Ｓｎ系Ｐｂフリー半田のＳｎがＴｉ層３に到達するのを防止するものである。なお、Ｎｉ層４の代わりにＣｕを用いた場合は、この半田バリア層はＴｉ−Ｃｕ層となる。   The Ti—Ni layer 5 corresponds to the solder barrier layer in the present invention, and prevents Sn of the Sn-based Pb-free solder from reaching the Ti layer 3. In addition, when Cu is used instead of the Ni layer 4, this solder barrier layer becomes a Ti—Cu layer.

ここで、本発明の実施の形態における半導体装置の製造方法に関して、図面に基づいて説明する。図２は本発明の実施の形態に係わる、半導体装置の製造工程を順に示す模式的である。   Here, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a schematic diagram sequentially showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

図２（ａ）において、半導体基板１のＴｉ層３などの形成面Ｓには図示しない自然酸化膜が形成されているので、まず、この自然酸化膜を除去するために、半導体基板１の形成面Ｓの逆スパッタリングを行う。逆スパッタリングを行うために、半導体基板１をスパッタリング装置のチャンバ内にセットした後、到達真空度として１０−７ｔｏｒｒ程度までチャンバ内の真空排気を行う。そして、このチャンバ内にアルゴンガスをマスフローコントローラによって３〜２５×１０−３ｔｏｒｒになるように導入する。この雰囲気下で半導体基板１に高周波バイアス４００〜６００Ｖを印加し、印加電力を１〜２ｋＷ／ｍ２の密度で、半導体基板１を例えば４ｎｍの厚さ、逆スパッタリングを行う。この逆スパッタリング終了後、速やかにチャンバ内へのアルゴンガス導入を停止する。この逆スパッタリングによって、半導体基板１の形成面Ｓに形成されていた自然酸化膜が除去される。 In FIG. 2A, since a natural oxide film (not shown) is formed on the formation surface S such as the Ti layer 3 of the semiconductor substrate 1, first, in order to remove the natural oxide film, the formation of the semiconductor substrate 1 is performed. Reverse sputtering of surface S is performed. In order to perform reverse sputtering, after setting the semiconductor substrate 1 in the chamber of the sputtering apparatus, the chamber is evacuated to a vacuum degree of about 10 −7 torr. And argon gas is introduce | transduced in this chamber so that it may become 3-25 * 10 < -3 > torr by a massflow controller. Under this atmosphere, a high frequency bias of 400 to 600 V is applied to the semiconductor substrate 1, and the semiconductor substrate 1 is reverse-sputtered to a thickness of 4 nm, for example, at a density of 1 to 2 kW / m 2 . After the reverse sputtering is completed, the introduction of argon gas into the chamber is stopped immediately. By this reverse sputtering, the natural oxide film formed on the formation surface S of the semiconductor substrate 1 is removed.

次に、図２（ｂ）に示すように、Ａｌ層２を形成する工程に移る。アルミターゲットを備えたチャンバ、すなわちＡｌ層２を形成することができるチャンバへウエハを搬送し、その後、アルゴンガスをマスフローコントローラによって、３〜２５×１０−３ｔｏｒｒになるようにチャンバ内に導入し、この雰囲気下でチタンターゲット側に高周波バイアス４００〜６００Ｖを印加する。この状態において、アルゴンイオンはアルミターゲットに衝突し、スパッタリングを引き起こし、アルミ原子またはアルミクラスターがアルミターゲット表面から放出される。放出されたアルミ原子またはアルミクラスターは逆スパッタリングされた半導体基板１に飛来し堆積する。このようにして、例えば厚さ２００ｎｍ〜３００ｎｍ程度のＡｌ層２を形成する。なお、Ａｌ層２の厚さは、半導体基板１とアルミターゲットとの間にはシャッタが設置されており、このシャッタの開閉によって適宜制御される。 Next, as shown in FIG. 2B, the process proceeds to the step of forming the Al layer 2. The wafer is transferred to a chamber equipped with an aluminum target, that is, a chamber in which the Al layer 2 can be formed, and then argon gas is introduced into the chamber at 3 to 25 × 10 −3 torr by a mass flow controller. In this atmosphere, a high frequency bias of 400 to 600 V is applied to the titanium target side. In this state, argon ions collide with the aluminum target, causing sputtering, and aluminum atoms or aluminum clusters are released from the surface of the aluminum target. The released aluminum atoms or aluminum clusters fly and deposit on the reverse-sputtered semiconductor substrate 1. In this way, for example, the Al layer 2 having a thickness of about 200 nm to 300 nm is formed. The thickness of the Al layer 2 is appropriately controlled by opening and closing the shutter, which is provided between the semiconductor substrate 1 and the aluminum target.

次に、図２（ｃ）に示すように、Ｔｉ層３を形成する工程に移る。Ｔｉ層３の形成は、Ａｌ層２を形成する工程と同じく、チタンターゲットを備えたチャンバ、すなわちＴｉ層３を形成することができるチャンバへウエハを搬送し、チャンバ内にアルゴンガスをマスフローコントローラによって３〜２５×１０−３ｔｏｒｒになるようにチャンバ内に導入する。そして、この雰囲気下でチタンターゲット側に高周波バイアス４００〜６００Ｖを印加し、チタンターゲットのスパッタリングを行う。このようにして、例えば厚さ２００ｎｍ〜３００ｎｍ程度のＴｉ層３を形成する。なお、Ｔｉ層３の厚さに関しても、Ａｌ層２が形成された半導体基板１とチタンターゲットとの間にはシャッタが設置されており、このシャッタの開閉によって適宜制御される。 Next, as shown in FIG. 2C, the process proceeds to the step of forming the Ti layer 3. The Ti layer 3 is formed in the same manner as in the formation of the Al layer 2 by transferring the wafer to a chamber equipped with a titanium target, that is, a chamber capable of forming the Ti layer 3, and supplying argon gas into the chamber by a mass flow controller. It introduce | transduces in a chamber so that it may become 3-25 * 10 < -3 > torr. In this atmosphere, a high frequency bias of 400 to 600 V is applied to the titanium target side to perform sputtering of the titanium target. In this way, for example, the Ti layer 3 having a thickness of about 200 nm to 300 nm is formed. The thickness of the Ti layer 3 is also appropriately controlled by opening and closing the shutter between the semiconductor substrate 1 on which the Al layer 2 is formed and the titanium target.

次に、図２（ｄ）に示すように、Ｎｉ層４を形成する工程に移る。Ｎｉ層４の形成は、Ａｌ層２、Ｔｉ層３を形成する工程と同じく、ニッケルターゲットを備えたチャンバ、すなわちＮｉ層４を形成することができるチャンバへウエハを搬送し、チャンバ内にアルゴンガスをマスフローコントローラによって３〜２５×１０−３ｔｏｒｒになるようにチャンバ内に導入する。そして、この雰囲気下でニッケルターゲット側に高周波バイアス４００〜６００Ｖを印加し、ニッケルターゲットのスパッタリングを行う。このようにして、例えば厚さ５００ｎｍ〜６００ｎｍ程度のＮｉ層４を形成する。また、Ｎｉ層４の厚さに関しても、Ａｌ層２及びＴｉ層３が形成された半導体基板１とニッケルターゲットとの間にシャッタが設置されており、このシャッタの開閉によって適宜制御される。 Next, as shown in FIG. 2D, the process proceeds to the step of forming the Ni layer 4. The formation of the Ni layer 4 is similar to the step of forming the Al layer 2 and the Ti layer 3. The wafer is transferred to a chamber equipped with a nickel target, that is, a chamber in which the Ni layer 4 can be formed, and argon gas is introduced into the chamber. Is introduced into the chamber at 3-25 × 10 −3 torr by a mass flow controller. In this atmosphere, a high frequency bias of 400 to 600 V is applied to the nickel target side to perform sputtering of the nickel target. In this way, for example, the Ni layer 4 having a thickness of about 500 nm to 600 nm is formed. Further, the thickness of the Ni layer 4 is also appropriately controlled by opening and closing the shutter, which is provided between the semiconductor substrate 1 on which the Al layer 2 and the Ti layer 3 are formed and the nickel target.

さらに、Ｎｉ層４上に図示しないＡｕなどからなる保護膜を形成する。保護膜の形成は、Ａｌ層２、Ｔｉ層３、Ｎｉ層４を形成する工程と同じく、金ターゲットを備えたチャンバ、すなわちＡｕ層を形成することができるチャンバへウエハを搬送し、チャンバ内にアルゴンガスをマスフローコントローラによって３〜２５×１０−３ｔｏｒｒになるようにチャンバ内に導入する。そして、この雰囲気下で金ターゲット側に高周波バイアス４００〜６００Ｖを印加し、金ターゲットのスパッタリングを行う。このようにして、例えば厚さ３０ｎｍ〜５０ｎｍ程度の保護膜を形成する。また、Ａｕの厚さに関してもＡｌ層２及びＴｉ層３などが形成された半導体基板１と金ターゲットとの間にシャッタが設置されており、このシャッタ開閉によって適宜制御される。 Further, a protective film made of Au or the like (not shown) is formed on the Ni layer 4. The protective film is formed in the same manner as the steps of forming the Al layer 2, the Ti layer 3 and the Ni layer 4, by transferring the wafer to a chamber equipped with a gold target, that is, a chamber capable of forming an Au layer, and into the chamber. Argon gas is introduced into the chamber by a mass flow controller so as to be 3 to 25 × 10 −3 torr. In this atmosphere, a high frequency bias of 400 to 600 V is applied to the gold target side to perform sputtering of the gold target. In this way, a protective film having a thickness of, for example, about 30 nm to 50 nm is formed. In addition, the thickness of Au is also appropriately controlled by opening and closing the shutter between the gold substrate and the semiconductor substrate 1 on which the Al layer 2 and the Ti layer 3 are formed.

次に、図２（ｅ）に示されるように、Ｔｉ−Ｎｉ層５を形成する工程に移る。このＴｉ−Ｎｉ層５を形成する工程は、上述のようにしてＡｌ層２、Ｔｉ層３、Ｎｉ層４、保護層が形成された半導体基板１を窒素雰囲気の石英管熱処理炉にセットする。そして、この石英管熱処理炉において、例えば、３５０℃で３分間の熱処理を行うことによってＴｉ層３とＮｉ層４との界面にＴｉ−Ｎｉ層５を形成する。   Next, as shown in FIG. 2E, the process proceeds to the step of forming the Ti—Ni layer 5. In the step of forming the Ti—Ni layer 5, the semiconductor substrate 1 on which the Al layer 2, Ti layer 3, Ni layer 4 and protective layer are formed as described above is set in a quartz tube heat treatment furnace in a nitrogen atmosphere. In this quartz tube heat treatment furnace, for example, a Ti—Ni layer 5 is formed at the interface between the Ti layer 3 and the Ni layer 4 by performing a heat treatment at 350 ° C. for 3 minutes.

その後、半導体基板１の形成面Ｓ上に形成されたＡｌ層２、Ｔｉ層３、Ｎｉ部４ａ、Ｔｉ−Ｎｉ層５からなる電極をＳｎ系Ｐｂフリー半田６によってリードフレーム７に半田接合する。   Thereafter, an electrode made of the Al layer 2, the Ti layer 3, the Ni portion 4 a, and the Ti—Ni layer 5 formed on the formation surface S of the semiconductor substrate 1 is soldered to the lead frame 7 with Sn-based Pb-free solder 6.

なお、Ｔｉ−Ｎｉ層５の膜厚は、熱処理温度と熱処理時間とによって適宜制御される。例えば、４００℃で３分間の熱処理を行った後に３６０℃で３分間の熱処理を行うことによって膜厚１９ｎｍ〜２６ｎｍのＴｉ−Ｎｉ層５を得ることができる。また、一回の熱処理でも、３５０℃で３０分間では膜厚４０ｎｍ〜６０ｎｍ、４００℃で３０分間では膜厚６０ｎｍ〜７０ｎｍ、４５０℃で３０分間では膜厚１００ｎｍ〜１２０ｎｍのようなＴｉ−Ｎｉ層５を得ることができる。   The film thickness of the Ti—Ni layer 5 is appropriately controlled by the heat treatment temperature and the heat treatment time. For example, the Ti—Ni layer 5 having a film thickness of 19 nm to 26 nm can be obtained by performing a heat treatment at 400 ° C. for 3 minutes and then performing a heat treatment at 360 ° C. for 3 minutes. Further, even in one heat treatment, a Ti—Ni layer having a film thickness of 40 nm to 60 nm at 350 ° C. for 30 minutes, a film thickness of 60 nm to 70 nm at 400 ° C. for 30 minutes, and a film thickness of 100 nm to 120 nm at 450 ° C. for 30 minutes. 5 can be obtained.

また、このＴｉ−Ｎｉ層５が、どの程度の膜厚で充分な接合寿命を保証できるかを検証した。図３（ａ）はＳｎ系Ｐｂフリー半田６としてＳｎ−Ｃｕ半田を用いた場合の高温放置試験時のＴｉ層３界面付近の断面図であり、（ｂ）はＳｎ系Ｐｂフリー半田６としてＳｎ−Ａｇ半田を用いた場合の高温放置試験時のＴｉ層３界面付近の断面図である。この高温放置試験は、Ｔｉ−Ｎｉ層５の膜厚が１９ｎｍである電極をＳｎ−Ｃｕ半田・Ｓｎ−Ａｇ半田それぞれでリードフレーム７に半田接合した半導体装置を１５０℃の温度環境に放置して行った。この結果、１５０℃の温度環境において５０００ｈ経過した時点で、図３（ａ）、（ｂ）に示すようにＴｉ層３界面に各半田材は到達しておらず、Ｔｉ−Ｎｉ層５は膜厚が１９ｎｍ以上であれば充分な接合寿命を保証できるといえる。   Moreover, it was verified by what film thickness this Ti—Ni layer 5 can guarantee a sufficient bonding life. FIG. 3A is a cross-sectional view of the vicinity of the interface of the Ti layer 3 during a high temperature standing test when Sn—Cu solder is used as the Sn-based Pb free solder 6, and FIG. 3B is Sn as the Sn-based Pb free solder 6. It is sectional drawing of Ti layer 3 interface vicinity at the time of the high temperature leaving test at the time of using -Ag solder. In this high temperature standing test, a semiconductor device in which an electrode having a Ti—Ni layer 5 having a film thickness of 19 nm is soldered to the lead frame 7 with Sn—Cu solder and Sn—Ag solder is left in a temperature environment of 150 ° C. went. As a result, when 5000 hours have passed in a temperature environment of 150 ° C., as shown in FIGS. 3A and 3B, each solder material does not reach the interface of the Ti layer 3, and the Ti—Ni layer 5 is a film. If the thickness is 19 nm or more, it can be said that a sufficient bonding life can be guaranteed.

ここで、Ｓｎ系Ｐｂフリー半田を用いて半導体電極を下地基板に半田接合する場合に接合寿命が短くなる理由について説明する。図４はＳｎ組成比の異なる半田材におけるＮｉ中へのＳｎ拡散係数の関係を示す図であり、この図からわかるようにＳｎ系Ｐｂフリー半田は、Ｓｎ−Ｐｂ系半田に比べてＮｉ中へのＳｎ拡散係数が約１０倍である。Ｎｉ中へのＳｎ拡散係数が約１０倍であるということは、ＳｎがＮｉ中へ拡散しＮｉが消滅する（半田材がＴｉへ到達する）時間が約１／１０になるということである。半田材がＴｉへ到達すると、半田材とＴｉとの接合性が良くないためＴｉと半田材との界面において剥離が起こりやすくなる。   Here, the reason why the bonding life is shortened when the semiconductor electrode is solder-bonded to the base substrate using Sn-based Pb-free solder will be described. FIG. 4 is a diagram showing the relationship of Sn diffusion coefficient into Ni in solder materials having different Sn composition ratios. As can be seen from this figure, Sn-based Pb-free solder is more into Ni than Sn—Pb-based solder. The Sn diffusion coefficient is about 10 times. The fact that the Sn diffusion coefficient into Ni is about 10 times means that the time when Sn diffuses into Ni and Ni disappears (solder material reaches Ti) is about 1/10. When the solder material reaches Ti, since the bonding property between the solder material and Ti is not good, peeling is likely to occur at the interface between Ti and the solder material.

次に、このようなＳｎ系Ｐｂフリー半田６を用いて半導体基板１をリードフレーム７に半田接合する際に、Ｔｉ−Ｎｉ層５によって、ＳｎがＮｉ中へ拡散しＮｉが消滅する時間を長くすることができる理由について説明する。   Next, when the semiconductor substrate 1 is soldered to the lead frame 7 using such Sn-based Pb-free solder 6, the Ti—Ni layer 5 causes Sn to diffuse into Ni and increase the time during which Ni disappears. Explain why you can.

検証のため、半導体装置をＳｎ−Ｐｂ系半田を用いてリードフレーム７へ半田接続して、１５０℃の温度環境に放置する高温放置試験を行った。その結果、半田バリア層として膜厚６００ｎｍのＮｉ層を用いた場合、約５００時間でＮｉ層全てが拡散（消滅）し、Ｔｉ層の界面にはＮｉ−Ｓｎ層が形成される。   For verification, a high temperature storage test was performed in which the semiconductor device was soldered to the lead frame 7 using Sn—Pb solder and left in a temperature environment of 150 ° C. As a result, when a 600 nm thick Ni layer is used as the solder barrier layer, the entire Ni layer diffuses (disappears) in about 500 hours, and a Ni—Sn layer is formed at the interface of the Ti layer.

また、半田バリア層として膜厚２５ｎｍのＴｉ−Ｎｉ層５を用いた場合、約５００時間でＴｉ−Ｎｉ層５にＳｎの拡散が始まり、約４０００時間でＴｉ層３の界面にＳｎが現れた。この結果から明らかなように、半田バリア層としてＴｉ−Ｎｉ層５を用いることによって、ＳｎがＴｉへ到達する時間を長くすることが出来る。従って、半導体基板１とリードフレーム７とをＳｎ系Ｐｂフリー半田６を用いて半田接合する場合に充分な接合寿命が保証できる。   When the Ti—Ni layer 5 having a film thickness of 25 nm was used as the solder barrier layer, Sn began to diffuse into the Ti—Ni layer 5 in about 500 hours, and Sn appeared at the interface of the Ti layer 3 in about 4000 hours. . As is apparent from this result, the time for Sn to reach Ti can be lengthened by using the Ti—Ni layer 5 as the solder barrier layer. Accordingly, when the semiconductor substrate 1 and the lead frame 7 are soldered together using the Sn-based Pb-free solder 6, a sufficient bonding life can be guaranteed.

（変形例１）
また、変形例１として、Ｔｉ−Ｎｉ層５とＳｎ系Ｐｂフリー半田６との間に本発明における第２半田バリア層に相当するＮｉ層４を形成するようにしてもよい。図５は、本発明の実施の形態の変形例１に係わる、半導体装置の構造を示す要部断面図である。なお、上述の実施の形態との共通部分についての詳しい説明は省略する。 (Modification 1)
As a first modification, the Ni layer 4 corresponding to the second solder barrier layer in the present invention may be formed between the Ti—Ni layer 5 and the Sn-based Pb free solder 6. FIG. 5 is a cross-sectional view of the main part showing the structure of the semiconductor device according to Modification 1 of the embodiment of the present invention. Note that a detailed description of parts common to the above-described embodiment is omitted.

図５において、１は半導体基板、２はＡｌ層、３はＴｉ層、４はＮｉ層、５はＴｉ−Ｎｉ層、６はＳｎ系Ｐｂフリー半田、７はリードフレームである。製造方法に関しては、上述と同様に逆スパッタリング、スパッタリング、熱処理を行い、Ａｌ２層、ＴＩ層３、Ｎｉ層４、Ｔｉ−Ｎｉ層５を形成する。この際に、Ｎｉ層４の膜厚を厚めに（例えば、６００ｎｍ）形成することによって、Ｔｉ−Ｎｉ層５とＳｎ系Ｐｂフリー半田６との間にＮｉ層４を形成する。このように、半田バリア層としてのＴｉ−Ｎｉ層５とＳｎ系Ｐｂフリー半田６との間にＮｉ層４を形成することによって、Ｎｉ層４がある分ＳｎがＴｉ層３へ到達する時間を長くすることが出来る。なお、Ｎｉ層４は、これに限定されるものではなくＣｕであってもよい。   In FIG. 5, 1 is a semiconductor substrate, 2 is an Al layer, 3 is a Ti layer, 4 is a Ni layer, 5 is a Ti-Ni layer, 6 is a Sn-based Pb-free solder, and 7 is a lead frame. Regarding the manufacturing method, reverse sputtering, sputtering, and heat treatment are performed in the same manner as described above to form the Al 2 layer, the TI layer 3, the Ni layer 4, and the Ti—Ni layer 5. At this time, the Ni layer 4 is formed between the Ti—Ni layer 5 and the Sn-based Pb-free solder 6 by forming the Ni layer 4 thick (for example, 600 nm). In this way, by forming the Ni layer 4 between the Ti—Ni layer 5 as the solder barrier layer and the Sn-based Pb-free solder 6, the time required for Sn to reach the Ti layer 3 is increased by the Ni layer 4. Can be long. The Ni layer 4 is not limited to this and may be Cu.

（変形例２）
また、変形例２として、Ｔｉ−Ｎｉ層５とＳｎ系Ｐｂフリー半田６との間に本発明における３元混合層に相当するＴｉ−Ｎｉ−Ｓｎ層８を形成するようにしてもよい。図６は、本発明の実施の形態の変形例２に係わる、半導体装置の構造を示す要部断面図である。なお、上述の実施の形態との共通部分についての詳しい説明は省略する。 (Modification 2)
As a second modification, a Ti—Ni—Sn layer 8 corresponding to the ternary mixed layer in the present invention may be formed between the Ti—Ni layer 5 and the Sn-based Pb free solder 6. FIG. 6 is a cross-sectional view of the principal part showing the structure of the semiconductor device according to Modification 2 of the embodiment of the present invention. Note that a detailed description of parts common to the above-described embodiment is omitted.

図６において、１は半導体基板、２はＡｌ層、３はＴｉ層、５はＴｉ−Ｎｉ層、６はＳｎ系Ｐｂフリー半田、７はリードフレーム、８はＴｉ−Ｎｉ−Ｓｎ層である。製造方法に関しては、上述と同様に逆スパッタリング、スパッタリング、熱処理を行い、Ａｌ層２、ＴＩ層３、Ｎｉ層４、Ｔｉ−Ｎｉ層５を形成する。その後、形成面Ｓ側にＡｌ沿層２、Ｔｉ層３、Ｔｉ−Ｎｉ層５などが形成された半導体基板１をＳｎ系Ｐｂフリー半田６によってリードフレーム７に半田接合する。さらに、半導体基板１がＳｎ系Ｐｂフリー半田６によってリードフレーム７に半田接続された状態で、上述のような窒素雰囲気の石英管熱処理炉にて熱処理を行うことによって、Ｔｉ−Ｎｉ−Ｓｎ層８を形成する。この際に、半田接続後の熱処理の時間及び温度によってＴｉ−Ｎｉ−Ｓｎ層８の膜厚（例えば、１９ｎｍ）を適宜制御する。   In FIG. 6, 1 is a semiconductor substrate, 2 is an Al layer, 3 is a Ti layer, 5 is a Ti—Ni layer, 6 is a Sn-based Pb-free solder, 7 is a lead frame, and 8 is a Ti—Ni—Sn layer. Regarding the manufacturing method, reverse sputtering, sputtering, and heat treatment are performed in the same manner as described above to form the Al layer 2, the TI layer 3, the Ni layer 4, and the Ti—Ni layer 5. Thereafter, the semiconductor substrate 1 on which the Al creeping layer 2, the Ti layer 3, the Ti—Ni layer 5 and the like are formed on the formation surface S side is soldered to the lead frame 7 with Sn-based Pb-free solder 6. Further, the Ti—Ni—Sn layer 8 is formed by performing a heat treatment in a quartz tube heat treatment furnace in a nitrogen atmosphere as described above in a state where the semiconductor substrate 1 is solder-connected to the lead frame 7 by the Sn-based Pb-free solder 6. Form. At this time, the film thickness (for example, 19 nm) of the Ti—Ni—Sn layer 8 is appropriately controlled according to the time and temperature of the heat treatment after the solder connection.

Ｔｉ−Ｎｉ層５とＳｎ系Ｐｂフリー半田６との間にＴｉ−Ｎｉ−Ｓｎ層８を設けると、もし、Ｔｉ−Ｎｉ−Ｓｎ層８及びＴｉ−Ｎｉ層５へＳｎが拡散した場合でも、Ｔｉ層３の界面には、Ｔｉ−Ｎｉ−Ｓｎ層８が形成されることになる。従って、Ｔｉ界面に各層の元素で構成されたＴｉ−Ｎｉ−Ｓｎ層８が存在することによって各層間で結合しやすく接合強度が向上する。なお、Ｎｉ層４は、これに限定されるものではなくＣｕであってもよい。   If the Ti—Ni—Sn layer 8 is provided between the Ti—Ni layer 5 and the Sn-based Pb-free solder 6, even if Sn diffuses into the Ti—Ni—Sn layer 8 and the Ti—Ni layer 5, A Ti—Ni—Sn layer 8 is formed at the interface of the Ti layer 3. Therefore, the presence of the Ti—Ni—Sn layer 8 composed of the elements of each layer at the Ti interface facilitates bonding between the layers and improves the bonding strength. The Ni layer 4 is not limited to this and may be Cu.

なお、上述の実施の形態においては、Ａｌ層２、Ｔｉ層３、Ｎｉ層４をスパッタリングを用いて形成する例を用いて説明したが、本発明はこれに限定されるものではなく、蒸着などで形成してもよい。   In the above-described embodiment, the example in which the Al layer 2, the Ti layer 3, and the Ni layer 4 are formed by sputtering has been described. However, the present invention is not limited to this, such as vapor deposition. May be formed.

本発明の実施の形態に係わる、半導体装置の構造を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. 本発明の実施の形態に係わる、半導体装置の製造工程を順に示す模式図である。It is a schematic diagram which shows the manufacturing process of the semiconductor device concerning embodiment of this invention in order. （ａ）は本発明の実施の形態に係わる、半導体装置のＳｎ−Ｃｕ半田を用いた場合の高温放置試験のＴｉ層３界面付近の断面図であり、（ｂ）はＳｎ−Ａｇ半田を用いた場合の高温放置試験のＴｉ層３界面付近の断面図である。(A) is sectional drawing of Ti layer 3 interface vicinity of the high temperature standing test at the time of using the Sn-Cu solder of the semiconductor device concerning embodiment of this invention, (b) uses Sn-Ag solder. It is sectional drawing of Ti layer 3 interface vicinity of the high temperature storage test in case of having. Ｓｎ組成比の異なる半田材におけるＮｉ中へのＳｎ拡散係数の関係を示す図である。It is a figure which shows the relationship of the Sn diffusion coefficient in Ni in the solder material from which Sn composition ratio differs. 本発明の実施の形態の変形例１に係わる、半導体装置の構造を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning the modification 1 of embodiment of this invention. 本発明の実施の形態の変形例２に係わる、半導体装置の構造を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning the modification 2 of embodiment of this invention. 従来技術に係わる、半導体装置の構造を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device concerning a prior art.

符号の説明Explanation of symbols

１ 半導体基板、２ Ａｌ層、３ Ｔｉ層、４ Ｎｉ層、４ａ Ｎｉ部、５ Ｔｉ−Ｎｉ層、６ Ｓｎ系Ｐｂフリー半田、７ リードフレーム、８ Ｔｉ−Ｎｉ−Ｓｎ層   DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Al layer, 3 Ti layer, 4 Ni layer, 4a Ni part, 5 Ti-Ni layer, 6 Sn type Pb free solder, 7 Lead frame, 8 Ti-Ni-Sn layer

Claims (5)

Ａｌ膜が形成された半導体基板に、Ａｌ膜上に接着層として形成された第１の金属層と、
前記第１の金属層とＮｉもしくはＣｕとの混合層からなる半田バリア層とを備える半導体電極であって、
前記半導体電極をＳｎ系Ｐｂフリー半田により下地基板に半田接合することを特徴とする半導体装置。 A first metal layer formed as an adhesive layer on the Al film on the semiconductor substrate on which the Al film is formed;
A semiconductor electrode comprising the first metal layer and a solder barrier layer made of a mixed layer of Ni or Cu,
A semiconductor device, wherein the semiconductor electrode is solder-bonded to a base substrate with Sn-based Pb-free solder. 前記第１の金属層がＴｉであることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first metal layer is Ti. 前記半田バリア層と前記Ｓｎ系Ｐｂフリー半田との間にＮｉもしくはＣｕを備えることを特徴とする請求項１又は請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein Ni or Cu is provided between the solder barrier layer and the Sn-based Pb-free solder. 前記半田バリア層と前記Ｓｎ系Ｐｂフリー半田との間に前記第１の金属層とＮｉもしくはＣｕとＳｎとからなる３元混合層を備えることを特徴とする請求項１又は請求項２に記載の半導体装置。   The ternary mixed layer comprising the first metal layer and Ni or Cu and Sn is provided between the solder barrier layer and the Sn-based Pb-free solder. Semiconductor device. 前記半田バリア層の厚さは１９ｎｍ以上であることを特徴とする請求項１乃至請求項４に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thickness of the solder barrier layer is 19 nm or more.
JP2004349043A 2004-12-01 2004-12-01 Semiconductor device Pending JP2006156910A (en)

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