JPH11160389A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor testing apparatus in which a relay is controlled so as to be turned on and off without using a relay drive circuit when a device to be tested is tested without a load and when the device to be tested is tested with a load by a method wherein a plurality of power supplies for a load circuit are provided and a plurality of relays which are driven by the plurality of power supplies are provided. SOLUTION: Normally, in the load circuit of a DUT 3, the value of a threshold level and that of a load are decided in such a way that a pull-up load resistance 5 which is connected to a power supply is connected to a pull-down load resistance 6 which is connected to a GND. In addition, the terminal, on one side, of the driving coil of a relay 4 is connected to the GND, and the terminal on the other side is connected to a power supply 7 for the load circuit. When the DUT 3 is tested without a load, a voltage is not supplied from the power supply 7 so as to be set at a GND level. A current is not made to flow to the driving coil of the relay 4, and the load circuit is not connected to the DUT 3. When the DUT 3 is tested with a load, the relay 4 is turned on by the voltage value level of the power supply 7, and the load circuit is connected to a measuring circuit by the resistance 5 and by the resistance 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor test apparatus,
In particular, it relates to a load circuit connection method for a semiconductor test apparatus.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration diagram of a portion for connecting and disconnecting a load to an output terminal of a device to be measured in a conventional semiconductor test apparatus. In this figure, reference numeral 1 denotes a driver for generating an input signal, 2 a comparator for determining the level of an output signal, 3 a device to be measured, 4 a relay, 5 a load resistor for pull-up, 6 a load resistor for pull-down, 7 Denotes a power supply for a load circuit, and 8 denotes a drive circuit for driving the relay 4, and each component is connected as shown in the figure.

When a device under test is tested by the semiconductor test apparatus having such a configuration, the device under test 3 is usually tested under no load conditions. At this time, a signal is supplied from the driver 1 to the input pin of the device under test 3 with the relay 4 turned off, and a test is performed by the comparator 2 to determine the level.

When a load test is performed, a relay 4
Is turned on, and the same test is performed in a state where the load resistance 5 for pull-up and the load resistance 6 for pull-down are connected to the device 3 to be measured.

[0005]

However, in the above-described method, the ON / OFF control of the relay 4 is performed by the relay drive circuit 8. However, the measuring pins of the device under test 3 are often tens of pins. The whole semiconductor test apparatus has several hundred pins to several thousand pins, and the number of relay drive circuits is required. Therefore, the circuit scale becomes enormous.

The present invention has been made in view of such a background, and a circuit for driving a relay can be prepared between a case where a device under test is tested with no load and a case where a load test is performed without preparing a circuit for driving a relay. It is another object of the present invention to provide a semiconductor test apparatus capable of ON / OFF controlling a relay and simplifying a circuit.

[0007]

In order to achieve this object, the invention according to claim 1 is provided for each of a plurality of input terminals of a device under test, and applies a measurement signal to each of the plurality of input terminals. A plurality of drivers that are provided for each of a plurality of output terminals of the device under test, a plurality of comparators that determine a signal level output from the plurality of output terminals, and a plurality of comparators that are provided for each of the plurality of output terminals. A plurality of load circuits respectively connected to or disconnected from the plurality of output terminals, and a plurality of load circuits provided for each of the plurality of load circuits, for applying a voltage to be applied to the plurality of load circuits when connected to the plurality of output terminals, respectively. A plurality of load circuit power supplies that can be turned on / off for each of the load circuits by a program; and a plurality of load circuit power supplies provided for each of the plurality of load circuits. Thus to provide a semiconductor test apparatus comprising and a plurality of relays to be driven.

According to a second aspect of the present invention, when the relay is driven by the voltage of the power supply for the load circuit, the load circuit is connected to the output terminal. And a semiconductor test apparatus according to (1).

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a portion related to load connection control of a semiconductor test apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a driver for generating a signal to be applied to the input terminal of the device under test 3, reference numeral 2 denotes a comparator for detecting the signal level of the output terminal of the device under test 3, and reference numeral 3 denotes a device to be measured. Device (hereinafter D
4 is a relay, 5 is a pull-up load resistor, 6 is a pull-down load resistor, 7 is a load circuit power supply, and each component is connected as shown.

Although only one set of each of the components denoted by reference numerals 1, 2 and 4 to 7 is shown, actually, the same number as the sum of the number of input pins and the number of output pins of the device under test 3 is prepared. It is assumed that

In the semiconductor test apparatus having such a configuration, the relay 4 is normally used when the DUT 3 is tested under no load.
When the test is performed with the DUT 3 loaded, the relay 4 is turned on and the DU is
The test is performed with the pull-up load resistor 5 and the pull-down load resistor 6 connected to T3.

At this time, in controlling the driving of the relay 4, the voltage of the load circuit power supply 7 is applied by the program control because the coil of the relay 4 is connected to the load circuit power supply 7. As a result, the relay 4 is driven by applying a voltage.

Next, the operation of this circuit will be specifically described. Normally, the load circuit of the DUT 3 is configured such that the pull-up load resistor 5 connected to the power supply and the pull-down load resistor 6 connected to GND are connected as shown in FIG. I can decide.

One terminal of the drive coil of the relay 4 is connected to GND, and the other terminal is connected to the load circuit power supply 7. For a no-load test of DUT3,
Since the voltage is not supplied from the load circuit power source 7 and is kept at the GND level, no current flows through the drive coil of the relay 4, so that the relay 4 is not turned on and the load circuit is not connected to the DUT.

Next, during a load test of the DUT 3, the level of the load circuit power supply 7 is raised to a preset voltage value. At this time, at the same time when the threshold level of the load circuit is determined, a current also flows through the drive coil of the relay 4 and the relay 4 is turned on, and the load circuit formed by the pull-up resistor 5 and the pull-down resistor 6 4 are connected to the measuring circuit via the contacts.

The operation of one embodiment of the present invention has been described above in detail with reference to the drawings. However, the present invention is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention.

[0018]

As described above, according to the present invention, in the semiconductor test apparatus, the relay connected to the load circuit is turned ON / OFF when the DUT is tested with no load and when the load test is performed. Since the relay is driven by the load circuit power supply as a method for turning off the load circuit, an effect is obtained that the load circuit can be turned on / off without preparing a circuit for driving the relay.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor test apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional semiconductor test apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Driver 2 Comparator 3 Device under test (DUT) 4 Relay 5 Pull-up load resistor 6 Pull-down load resistor 7 Load circuit power supply 8 Relay drive circuit

Claims (2)

[Claims] 1. A plurality of drivers are provided for each of a plurality of input terminals of a device under test, and are provided for each of a plurality of output terminals of the device under test; A plurality of comparators for determining signal levels output from the plurality of output terminals; a plurality of load circuits provided for each of the plurality of output terminals, respectively connected to or disconnected from the plurality of output terminals; A plurality of load circuits provided for each load circuit and capable of being turned on / off for each of the load circuits by a program for applying a voltage to be applied to the plurality of load circuits when connected to the plurality of output terminals, respectively; And a plurality of relays provided for each of the plurality of load circuits and driven by the plurality of load circuit power supplies. 2. The semiconductor test apparatus according to claim 1, wherein the load circuit is connected to the output terminal when the relay is driven by a voltage of the load circuit power supply.