JPH11154851A - Integrated circuit element having adaptive output port - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform connection without adding an element such as a buffer, even if there is difference in other integrated circuit elements which are connected and power supply voltage by selecting a power supply voltage, that is individually designated among plural power input terminals and supplying it to plural output ports respectively. SOLUTION: Power supply voltages which are inputted from input terminals 4 to 6 of power sources of this integrated circuit element 7 are respectively supplied to each contact of parallel connected switches 9 and 11 which are provided inside the element 7. A signal that is outputted from an internal circuit 8 is sent to output buffers 10 and 12 respectively. The power source of a first output buffer 10 is selected to a voltage B, that is the power supply voltage of an integrated circuit element 19 which is its output destination by switching the switch 9 through a control signal from the circuit 8. Similarly, the power source of the second output buffer 12 is selected to a voltage C, that is the power supply voltage of an integrated circuit element which is its output destination by switching the switch 11 through a control signal from the circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit device (also referred to as an integrated circuit device or an integrated circuit component) having an adaptive output port.

[0002]

2. Description of the Related Art A conventional integrated circuit device has only one kind of power supply voltage at an output port, and a rising speed of an output signal is constant.

[0003]

Therefore, the above-mentioned prior art has the following drawbacks.

1) In recent years, the power supply voltage of an integrated circuit tends to decrease with the progress of the manufacturing process. However,
The power supply voltages of all the integrated circuit elements used in one electronic device do not decrease at the same time, so that the integrated circuit elements operate at different power supply voltages. Therefore, in that case, a buffer for adjusting the power supply voltage between the signals is required.

2) Conventionally, a clock or data output port of an integrated circuit has a pulse rising speed higher than necessary in order to operate regardless of the circuit layout of a device. However, it is clear that a pulse faster than necessary adversely affects unnecessary radiation and power consumption.

The present invention has been made in view of the above points, and a first object of the present invention is to add an element such as a buffer even if there is a difference in power supply voltage from another integrated circuit element to be connected. It is possible to make a connection without the need.

A second object of the present invention is to prevent the output port from being driven at an unnecessarily high speed by making the rising speed of the signal variable according to the arrangement of other integrated circuit elements to be connected. To make it possible.

[0008]

In order to achieve the first object, according to the present invention, a plurality of power supply input terminals having different power supply voltages, a plurality of output ports, and a plurality of output ports are provided. Power supply switching means for selecting a power supply voltage having a voltage value individually specified from each of the plurality of power supply input terminals and supplying the selected power supply voltage to the output port.

Here, the power supply switching means may comprise a plurality of changeover switches individually provided for each of the plurality of output ports.

[0010] The information processing apparatus may further include a selection signal generation circuit that supplies a selection signal corresponding to a voltage value of a power supply voltage supplied to each of the plurality of output ports to each of the plurality of changeover switches.

Further, the voltage value of the power supply voltage selectively supplied to each of the plurality of output ports is a voltage value of the power supply voltage required by each integrated circuit element connected to the output port. it can.

[0012] In order to achieve the second object, the present invention is directed to claim 5.
The invention comprises a plurality of output ports, and a selection control means for selecting and providing a plurality of rising speeds or a rising speed specified from among drive currents or a drive current to each of the plurality of output ports. It is characterized by having done.

Here, the selection control means includes: a selection means for preparing a plurality of rising speeds or drive currents selectable for each of the plurality of output ports;
A selection signal generation circuit for generating a selection signal corresponding to a rising speed or a drive current to be given to each of the plurality of output ports, and the selected signal corresponding to the selection signal supplied from the selection signal generation circuit. Means for selecting a rising speed or a drive current corresponding to the selection signal from the means and supplying the selected drive speed to the output port.

Further, the rising speed or drive current selectively supplied to each of the plurality of output ports is determined according to the arrangement state of each integrated circuit element connected to the plurality of output ports. Can be.

Further, the difference in the arrangement state of each integrated circuit element connected to the plurality of output ports is determined by whether each of the integrated circuit elements shares the substrate of the plurality of output ports. It can be.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows a circuit configuration of an integrated circuit element according to the embodiment. In FIG. 1, 1, 2, and 3 are power supplies having different voltage values, and 4, 5, and 6 are input terminals of the respective power supplies. 7 is a first integrated circuit element according to the present invention, 8 is an internal circuit of the integrated circuit element 7, 9 and 11 are power supply switches for output buffers, 10 and 12 are output buffers thereof, and 13 and 14 are integrated circuit elements. 7 is an output terminal. Reference numeral 19 denotes a second integrated circuit element connected to the integrated circuit element 7, and 17 denotes a power supply terminal of the integrated circuit element 19. Reference numeral 20 denotes a third integrated circuit element connected to the integrated circuit element 7, reference numeral 18 denotes a power supply terminal of the integrated circuit element 20, and reference numerals 15 and 16 denote signal input terminals of the integrated circuit elements 19 and 20, respectively.

Next, the operation of this embodiment will be described with reference to FIG.

In the configuration of FIG. 1, assuming that the power supply voltage of the integrated circuit element 7 is A, the power supply voltage of the integrated circuit element 19 is B, and the power supply voltage of the integrated circuit element 20 is C, The voltage A is input to the terminal 4, the voltage B is input to the power supply terminal 5, and the voltage C is input to the power supply terminal 6.

Here, the power supply voltage of the integrated circuit element 19 is B
Therefore, the voltage B is input to the power supply terminal 17. Since the power supply voltage of the integrated circuit element 20 is C, the voltage C is input to the power supply terminal 18 thereof.

The power supply input terminals 4, 5,.
The power supply voltage input from the integrated circuit device 7 is
Are supplied to the respective contacts of the parallel-connected switches 9 and 11 provided inside the switch.

The signals output from the internal circuit 8 are sent to output buffers 10 and 12, respectively. The power source of the first output buffer 10 is the integrated circuit element 1 to which the output
9 is selected by switching the switch 9 by a control signal from the internal circuit 8. Similarly, the power supply of the second output buffer 12 is the voltage C which is the power supply voltage of the integrated circuit element 20 to which the output buffer 12 is output.
Is selected by switching the switch 11 according to a control signal from the internal circuit 8.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
1 shows a circuit configuration of an integrated circuit element according to the embodiment. In FIG. 2, reference numeral 21 denotes a first substrate on which the integrated circuit element according to the present invention is mounted, 22 denotes a first integrated circuit element that best represents the features of the present invention, and 23 denotes an internal circuit of the integrated circuit element 22. . Reference numerals 24 and 25 denote output ports A and B for driving output signals from the internal circuit 23.
The relationship between the rising speeds of the respective pulses is such that port B> port A. Similarly, 30,
Reference numeral 31 denotes an output port C and an output port D for driving an output signal from the internal circuit 23. The relationship between the rising speeds of the respective pulses is such that port D> port C.

Reference numeral 26 denotes a switch for selecting the port A or port B, and reference numeral 27 denotes a control signal for switching the switch 26. Similarly, 29 is a switch for selecting port C and port D, and 28 is a control signal for switching the switch 29. These control signals 27 and 28 are output from the internal circuit 23.

Reference numeral 33 denotes an output terminal for outputting the signal selected by the first switch 26 to the outside, and reference numeral 34 denotes an output terminal for outputting the signal selected by the second switch 29 to the outside. 36 is a second integrated circuit element mounted on the same substrate 21 as the integrated circuit element 22, and 35 is an input terminal thereof.

Reference numeral 38 denotes a substrate different from the substrate 21, and the substrate 21 and the substrate 38 are connected by 37 wires. Reference numeral 40 denotes a third integrated circuit element mounted on the substrate 38, and reference numeral 39 denotes a signal input terminal thereof.

Next, the operation of this embodiment will be described with reference to FIG.

In the configuration shown in FIG. 2, signals output from the internal circuit 23 of the first integrated circuit element 22 are sent to ports A and B of 24 and 25. Since the output destination of this signal is connected to the second integrated circuit element 36 on the same substrate 21, the switch 26 selects the port A whose rising speed is slow by the control signal 27 from the internal circuit 23, and the port B Enter save mode. The signal passing through the switch 26 is output from the output terminal 33 and is input to the input terminal 35 of the integrated circuit device 36.

Next, the signal output from the internal circuit 23 of the first integrated circuit element 22 is sent to ports C and D of 30 and 31. Since the output destination of this signal is connected to the third integrated circuit element 40 on the separate substrate 38, the switch 29 selects the port D having a fast rising speed by the control signal 28 from the internal circuit 23, and the port C is the power Enter save mode. The signal that has passed through the switch 29 is output from the output terminal 34, and is input to the input terminal 39 of the third integrated circuit element 40 through the wire 37 for connecting the substrates.

FIG. 3 shows an example of an output waveform and an input waveform in the embodiment of FIG.

Here, the waveform 41 represents the output waveform of the port A of 24, and the waveform 42 is inputted to the input terminal 35 of the second integrated circuit element 36 disposed on the same substrate 21 as the output side. This shows the input waveform. The waveform of 43 represents the output waveform of port D of 31, and the waveform of 44 represents the input waveform input to the input terminal 39 of the third integrated circuit element 40 disposed on the substrate 38 separate from the output side. I have.

Since the 24 port A and the input terminal 35 are arranged on the same substrate 21, the load at the connection is light, and the rise of the output port corresponds to the output waveform 4 of the port A.
Use of a slow port such as 1 does not hinder operation.

However, since the output destination of the port D of 31 is the input terminal 39 on the separate board 38, using a slower port causes a heavy load, which hinders the operation. Therefore, if the port D having a fast rising like the output waveform 43 of the port D is used, the operation is not hindered like the input waveform 44 input to the input terminal 39.

[0034]

As described above, according to the first aspect of the present invention, when transferring signals between integrated circuits having different power supply voltages, an additional circuit such as a buffer is not added.
Processing can be performed at high speed.

According to the second aspect of the present invention, even if the rise time required for the output signal is different due to the relationship of the arrangement of the integrated circuit or the like, an output suitable for the rise time can be output. At the same time, the level of unnecessary radiation can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a waveform diagram showing an example of an output waveform and an input waveform according to a second embodiment of the present invention.

[Explanation of symbols]

 1, 2, 3 Power supply input terminals 4, 5, 6, 17, 18 Power supply input terminals 7, 19, 20, 22, 36, 40 Integrated circuit element 8, 23 Internal circuit of integrated circuit 9, 11, 26, 29 switch 10,12 output buffer 24,25,30,31 output port 13,14,33,34 output terminal 15,16,35,39 input terminal 21,38 board 27,28 control signal 37 wire 41 port A output Waveform 42 Input waveform at input terminal 35 43 Output waveform at port D 44 Input waveform at input terminal 39

Claims (8)

[Claims] 1. A plurality of power supply input terminals having different power supply voltages, a plurality of output ports, and a power supply voltage having a voltage value individually designated for each of the plurality of output ports is transmitted from the plurality of power supply input terminals. An integrated circuit device comprising: a power supply switching means for selecting and supplying power to the output port. 2. The power supply switching means comprises a plurality of changeover switches individually provided for each of the plurality of output ports.
3. The integrated circuit device according to claim 1. 3. A selection signal generation circuit for supplying a selection signal corresponding to a voltage value of a power supply voltage supplied to each of the plurality of output ports to each of the plurality of changeover switches. Item 3. An integrated circuit device according to item 2. 4. The power supply voltage value selectively supplied to each of the plurality of output ports is a power supply voltage value required by each integrated circuit element connected to the output port. 4. The integrated circuit device according to claim 1, wherein: 5. A plurality of output ports, and selection control means for selectively giving a plurality of rising speeds or a rising speed specified from a drive current or a drive current to each of the plurality of output ports. An integrated circuit device comprising: 6. The selection control unit includes: a selection unit that prepares a plurality of rising speeds or drive currents that can be selected for each of the plurality of output ports; and provides the selection unit with each of the plurality of output ports. A selection signal generation circuit for generating a selection signal corresponding to a power rising speed or a drive current; and a rising speed corresponding to the selection signal from the selected means in response to the selection signal supplied from the selection signal generation circuit. 6. The integrated circuit device according to claim 5, further comprising a switch for selecting a drive current and supplying the selected drive current to the output port. 7. A rising speed or a drive current selectively supplied to each of the plurality of output ports is determined according to an arrangement state of each integrated circuit element connected to the plurality of output ports. Claim 5
Or an integrated circuit element according to 6. 8. The arrangement state of each integrated circuit element connected to the plurality of output ports is determined based on whether each of the integrated circuit elements shares a substrate of the plurality of output ports. The integrated circuit device according to claim 7, wherein: