JP2008126406A - Integrated circuit for driving of thermal head - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit for the driving of a thermal head which has a plurality of shift registers and prevents spare bits in the shift registers. <P>SOLUTION: One data signal input terminal is set at one shift register SR1 of the plurality of shift registers SR1-SR3 which sequentially transfer and store data signals, and one data signal output terminal is set at the shift register SR3. A switching means 19 is prepared which switches the plurality of shift registers according to a combination of selection signals Sa and Sb of a selecting circuit 14 which selects the number of bits corresponding to the number of dots of heating elements of the thermal head from a total number of bits of the shift registers. When the data signal is inputted to the shift registers and outputted outside, no spare bits are generated in the shift registers even when the number of output bits from the shift registers changes. Moreover, the data signal input terminal and the data signal output terminal can be used in common, so that the integrated circuit dispenses with an additional installation of a data signal output terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thermal head driving integrated circuit used for driving a thermal head and a thermal head using the integrated circuit.

As shown in FIGS. 10 and 11, a head substrate 1 made of an insulating substrate such as ceramics and a printed wiring made of glass epoxy or the like on a support plate 10 made of a metal having good heat dissipation, for example, aluminum. The plate 3 is fixed with an adhesive 9.
A heating element 2 extending in the longitudinal direction is formed on the head substrate 1, and the heating element 2
Individual electrodes 8 are connected to each dot. On the printed wiring board 3, a thermal head driving integrated circuit (hereinafter referred to as a driving IC) 4 for controlling energization to the heating element 2 is mounted with a plurality of driving ICs 4 arranged in the longitudinal direction. ing.

  The pad formed at the end of the individual electrode 8 and the drive output terminal 16 of the drive IC 4 are electrically connected by a wire 15 such as gold. In order to protect the drive IC 4 and the wire 15, a sealing resin 6 such as epoxy is applied. A connector 5 is attached to the printed wiring board 3 for connection to an external control device or the like. Further, a conductor pattern 17 or the like for connecting each terminal of the drive IC 4 to the connector 5 is formed on the surface of the printed wiring board 3. The head substrate 1 and the printed wiring board 3 are formed with a common electrode 1a connected to the heating element 2 and a conductor pattern 3a for guiding the common electrode 1a to the connector 5 through a wire 15.

The driving IC 4 outputs a data signal to energize a necessary heating element. In the driving IC 4, a heat generating element driving element including a shift register for storing a data signal and a MOS transistor is formed. Printing is performed by energizing a heating element connected to the drive output terminal 16 with a heating element driving element corresponding to the data signal in the shift register.
The number of bits of the heating element driving element and shift register formed in the driving IC 4 is the same as the number of heating element dots.

The number of drive ICs used in the thermal head is set according to the number of dots of the heating element, and the number of bits of one drive IC is generally 64 bits.
Dividing the total number of heating element dots by the number of bits of the shift register configured in one driving IC is the number of driving ICs used. For example, in the case of a thermal head having a dot density of 8 dots / mm and an effective print width of 56 mm, the total number of heating element dots is 448.
In the case of a 64-bit driver IC, the number of driver ICs to be used is 448 ÷ 64 = 7.

  Conventionally, when a thermal head uses a plurality of shift registers of a drive IC connected in series, as shown in FIG. 10, each drive IC 4 (reference numerals 4a and 4c are attached to the drive ICs on the input side and the output side). The data signal input terminal 11 and the data signal output terminal 12 provided on the head substrate 1 are connected by a wire 15 such as gold via a conductor pattern 7a formed on the head substrate 1.

  The driving IC operates to shift the data signal from left to right. The data signal is shifted by a clock signal input to the clock terminal of the driving IC 4. The number of clock signals necessary for shifting the data signal for one line is equal to the number of bits of the shift register, that is, the total number of heating element dots.

In the configuration of the thermal head shown in FIG. 10, seven drive ICs 4 are used. However, in the following description, the left-end drive IC is referred to as the input-side drive IC 4a and the right-end drive IC is referred to regardless of the number of drive ICs used. The output side driving IC 4c will be described.
The data signal output terminal 12 of the output side driver IC 4c is electrically connected to the data signal output conductor pattern 17 of the printed wiring board 3 through a conductor pattern 7a formed on the head substrate 1 with a wire. The data signal output conductor pattern 17 is connected to the connector 5 and outputs a data signal to an external control device (not shown).

The drive IC, which is the main component of the thermal head, has a high ratio to the material cost. Therefore, in order to reduce the cost of the drive IC in order to reduce the price, the number of heating element drive elements in one drive IC is increased. A method for increasing the degree of integration is employed.
On the other hand, when the number of heating element driving elements is increased in one driving IC due to high integration of the driving IC, the total number of heating element dots of the thermal head constituted by the existing driving IC depending on the number of driving ICs used. May not match the total number of bits of the shift register.
In general, in order to confirm that the data signal is shifted in the thermal head, it is necessary to output the data signal from the output side driving IC 4 c to the outside through the conductor pattern 17 and the connector 5.

In this type of thermal head, the total number of dots of the heating element and the number of bits of the shift register must be the same.
For example, in the case of a thermal head having a dot density of 8 dots / mm and an effective print width of 56 mm, the total number of dots of the heating element is 448. The number of driving ICs used is a value obtained by dividing the total number of dots of the heating element by the number of bits of the shift register per driving IC. However, if it is not divisible, the rounded up value is the number of driving ICs used.

Although 64 bits are mainly used as the driving IC for the thermal head, in the case of the configuration shown in FIG. 10, the number of driving ICs used is 448/64 = 7. On the other hand, if a highly integrated 192-bit drive IC is used to make the thermal head having the same specifications as described above, three drive ICs are required, 448/192 = 2.33.
When three 192-bit driving ICs are used, the total number of bits of the shift register is 192 × 3 = 576 bits, so that 576-448 = 128 bits remain from the originally required number of bits. Hereinafter, the remaining bits in the shift register are collectively referred to as “remainder bits”.

  When a data signal is output to the outside through the data signal output conductor pattern 17 (FIG. 10), the timing of outputting the data signal is delayed due to the presence of the surplus bits in the shift register. The data signal is shifted in the shift register by the clock signal. However, even if the surplus bits exist, the clock signal that is originally required is determined to be 448, so the data signal for 128 bits is shifted without being shifted. It will remain in the register.

  In this case, the compatibility when outputting a data signal to a thermal head using seven 64-bit drive ICs is impaired, so that the same control program cannot be used. For such a problem, even if there are extra bits in the shift register in the drive IC, a means for outputting the data signal from the drive IC to the outside at a normal timing is required. In order to solve such problems, driving ICs having shift registers as shown in FIGS. 7 and 8 have been proposed (for example, Patent Document 1, Patent Document 2, and Patent Document 3).

JP-A-6-286189 JP-A-7-266597 JP 2000-198231 A

As shown in FIG. 7, three shift registers of a shift register SR1, a shift register SR2, and a shift register SR3 are provided in one driver IC.
The number of bits per shift register is 64 bits. Therefore, the total number of bits of the shift register of this driving IC is 64 × 3 = 192 bits.

The shift register SR1 is provided with a data signal input terminal 11 to which a data signal SI is input, and between the shift register SR1 and the shift register SR2, between the shift register SR2 and the shift register SR3. The shift register SR3 is provided with a plurality of data signal output terminals 13 and 12 for outputting data signals SO1, SO2 and SO3. The shift register SR1 is provided with a data signal input terminal 11 for inputting a data signal SI.
Although not shown, in the drive IC, in addition to the data signal output terminal, a voltage supply terminal for supplying a voltage to the drive IC, a terminal for controlling energization to the data signal output terminal, and a data signal to the shift register A terminal (not shown) for switching between reading and holding is provided.

The following is an example of a thermal head in which the total number of bits of the shift registers of the three driving ICs used for the thermal head is 576 bits (192 × 3), and 128 bits are generated by using only 448 bits. The problem will be explained as follows.
FIG. 9 shows a thermal head using the drive IC shown in FIG.
As shown in FIG. 9, the thermal head uses three drive ICs 4 a, 4 b and 4 c connected to the conductor pattern 7. In order to eliminate the extra bits (128 bits), the 64-bit shift register SR2 and the 64-bit shift register SR3 in the drive IC 4c on the output side are not used.

  Therefore, if only 64 bits of the shift register SR1 among the three shift registers SR1, SR2 and SR3 in the output side driver IC 4c are used, the remaining 128 bits are not generated. The data output terminal 12 from which the data signal SO1 is output from the shift register SR1 of the output side drive IC 4c and the data signal output conductor pattern 17 provided on the printed wiring board 3 are electrically connected by the wire 15 to electrically connect the data output terminal 12 of the drive IC. A data signal can be output to the outside.

At this time, the data signal is also sent to the shift register SR2 and the shift register SR3 (FIG. 7) of the output side drive IC 4c. As shown in FIG. 9, individual electrodes corresponding to these shift registers are provided. Because there is no, printing is not performed.
With such a configuration, the total number of bits of the shift registers connected in the thermal head is 192 × 2 + 64 = 448 bits, so there are no more bits, and compatibility with conventional thermal heads when outputting data signals is achieved. Can be maintained.

FIG. 8 is a block diagram showing a configuration of a shift register of another conventional driving IC.
As shown in FIG. 8, the driving IC includes three shift registers SR1, SR2, and SR3. Each shift register has 64 bits.
For each shift register, a data signal input terminal 11 for inputting data signals SI1, SI2, and SI3, and data signal output terminals 13 and 12 for outputting data signals SO1, SO2, and SO3 are provided. Here, when the shift registers SR1 to SR3 are connected and used, the data signal output terminal 13 and the data signal input terminal 11 are electrically connected to each other. 9 can be handled similarly to the configuration shown in FIG.

  The driving IC of FIG. 7 differs from the driving IC of FIG. 8 in that the driving IC of FIG. 8 can select the data signal input terminal 11 as an arbitrary shift register. By changing the position of the data signal input / output terminal to be used, it is possible to change the position of the shift register assigned for the surplus bits.

In order to eliminate the extra bits in any of the drive IC shift registers, it is necessary to arrange the other input / output terminal terminals except the data input terminal of the shift register SR1 in the middle of the drive IC. As shown in FIG. 9, since the drive output terminal 16 is continuously arranged on one side of the drive IC on the side of the heating element 2, the data signal input / output terminals are arranged in the middle of the drive output terminal 16. Is difficult to manufacture.
When such a highly integrated driving IC is used, the longitudinal dimension of the driving IC is shorter than the range in which the heating elements are arranged. Therefore, the density of the wiring pattern is rough while the driving IC is mounted.

  Incidentally, the conductor on the head substrate of the thermal head is formed of a gold film having a thickness of about 1 μm. However, when a conductor pattern is formed on the head substrate, individual electrodes and the like can be simultaneously formed by etching. On the other hand, when a conductor pattern is formed on a printed wiring board, a copper foil having a thickness of about 20 μm is formed by etching, so that it becomes difficult to form a finer pattern than the head substrate.

  As described above, in the conventional driving IC, the conductor pattern 17 (FIG. 9) for connecting the data signal output terminal to the outside must be provided in the printed wiring board 3, so that the printed wiring board becomes large and the thermal head can be downsized. Hinder. Further, when the number of shift registers is increased, the data signal input / output terminals corresponding to the respective blocks must be provided in the drive IC, so that the size of the drive IC increases.

  When the conventional driving IC is used by changing the number of bits of the shift register, a plurality of data signal input / output terminals are arranged in the driving IC, and are selected and used when connected by a wire outside the driving IC. It has become. In this case, it is difficult to interrupt the data signal output terminal to the outside between the drive output terminals of the drive IC, and the data signal output terminal to the outside is opposite to the side where the drive output terminal of the drive IC is disposed. Must be provided on the side of

An integrated circuit for driving a thermal head according to the present invention includes a pair of one data signal input terminal and one data signal output terminal provided in a plurality of shift registers that sequentially transfer and store serially supplied data signals. A data input / output terminal; and selection means for selecting the number of bits corresponding to the number of heating element dots of the thermal head from the total number of bits of the shift register.
In addition, switching means for switching the plurality of shift registers according to the output of the selection means is provided.

  In the driving IC having the above-described configuration, the combination of the number of bits of the shift register that is enabled by one data signal input terminal, one data signal output terminal, and the number selection signal of the shift register becomes the number of heating element dots of the thermal head. By providing selection means that can be selected in accordance with this, it is not necessary to additionally provide a large number of data signal input / output terminals connected to the shift register in the drive IC.

As will be described later, for example, if one data signal input terminal and one external data signal output terminal and two terminals for setting a combination of selection circuits are provided, a plurality of shift registers provided in the drive IC are provided. The number of terminals for controlling the total number of bits is four.
Here, if two terminals for setting a combination are provided, the selection circuit can be switched in four ways.
As a result, the data signal input / output terminals of the plurality of shift registers can be handled by a pair of input / output terminals of one data signal input terminal and one data signal output terminal, so that the drive output terminal of the drive IC is arranged. It is possible to provide the data signal input / output terminals of the shift register on the same side as the side where the drive output terminal of the drive IC is arranged.

  In addition, by providing a switching circuit that can select the total number of bits of the shift register that is effective in the driver IC from a predetermined combination, by selecting the number of bits to be used as appropriate, the output timing of the data signal to the outside can be reduced. Compatibility can be maintained.

By providing a switching circuit capable of selecting the number of effective bits of the shift register in the drive IC having a plurality of shift registers, the data signal input terminal and the data signal output terminal of the shift register are arranged on the side where the drive output terminal of the drive IC is arranged. Can be placed on the same side.
This facilitates the connection between a plurality of drive ICs with the conductor pattern provided on the head substrate of the thermal head, and eliminates the need to provide the conductor pattern in the printed wiring board, thereby leading to miniaturization of the thermal head.

Embodiments of the driving IC used in the thermal head according to the present invention will be described below. FIG. 1 is a block diagram showing the configuration of a driving IC according to the present invention.
As shown in FIG. 1, the drive IC 4 is provided with three shift registers, for example, a shift register SR1, a shift register SR2, and a shift register SR3. The number of bits per shift register is 64 bits.
Therefore, the total number of bits of the shift register of the driving IC 4 is 64 × 3 = 192 bits. Further, the driving IC 4 includes one data signal input terminal 11 for serially inputting the data signal SI to the shift register SR1 and one data signal output terminal 12 for outputting the data signal SO from the shift register SR3 to the outside. ing.

The shift registers are electrically connected in the driving IC, and lines L1, L2, and L3 that can be connected to the data signal output terminal 12 are formed in the driving IC for each shift register.
An electronic selection switch 19 is formed in the drive IC 4, and the selection switch 19 selects one data signal output SO of the lines for outputting a data signal from each shift register to select a data signal. Connect to output terminal 12.
The selection switch 19 is switched by a selection circuit 14 that is controlled by the output of a logic circuit that operates according to the combination of the potentials of the selection signals SA and SB applied to the selection terminals 18a and 18b.

Table 1 shows an example of logic combinations of the selection circuit 14 for switching the selection switch 19.

The symbol L representing the potentials of the selection signals SA and SB in Table 1 represents the GND level of the driving IC, and H represents the level of the power supply voltage (Vdd) of the driving IC.
When the potential of the selection signal SA of the selection circuit 14 is L and the potential of SB is H, the output of the shift register SR1 is connected to the data signal output terminal 12 via the line L1 by the selection switch 19 to output the data signal. It is output to the outside as SO. At this time, the effective number of bits of the shift register is 64 bits of the shift register SR1.

  When the potential of the selection signal SA of the selection circuit 14 is H and the potential of SB is L, the selection switch 19 connects the output of the shift register SR2 to the data signal output terminal 12 via the line L2. At this time, the effective number of bits of the shift register is 128 bits (64 bits × 2) of the shift register SR1 and the shift register SR2.

When the potential of the selection signal SA is H and the potential of SB is H, the selection switch 19 connects the output of the shift register SR3 to the data signal output terminal 12 via the line L3.
At this time, the effective number of bits of the shift register is 192 bits (64 bits × 3) of the shift register SR1, the shift register SR2, and the shift register SR3.

Whether the potentials of the selection signal SA and the selection signal SB applied to the selection terminals 18a and 18b of the selection circuit 14 are electrically connected to either the GND pattern or the Vdd pattern on the printed wiring board of the thermal head. By selecting, the number of bits used in the shift register can be set. Furthermore, if the selection terminal of the selection switch 19 is connected to an external control device with an individual wiring pattern, the number of bits of the shift register can be arbitrarily variably set by switching the level of the control signal. Is possible.
Here, the setting of the number of bits according to Table 1 corresponds to three types of 64 bits, 128 bits, and 192 bits, but there are four combinations when two selection terminals of the selection circuit 14 are provided. Up to can be set.

FIG. 4 shows a configuration of a thermal head using a drive IC having the shift register shown in FIG.
In the thermal head shown in FIG. 4, the total number of bits of the shift register is 576 bits (64 bits × 3 × 3), and only 448 bits are used. In this case, the remaining bits are 128 bits. The thermal head includes three drive ICs 4a, 4b, and 4c each having a 192-bit (64 bits × 3) shift register shown in FIG.
In order to eliminate the extra 128 bits, the selection circuit 14 is set so that only the shift register SR1 (64 bits) of the three shift registers SR1 to SR3 in the output side drive IC 4c is used. .
Then, by using the selection circuit 14 as described in the configuration of the driving IC in FIG. 1, the surplus bits can be eliminated and the number of bits can be adjusted to 448 bits (192 bits × 2 + 64 bits).

At this time, the conductor pattern 7a provided on the head substrate 1 connected to the data signal output terminal 12 of the drive IC 4c on the output side and the data signal output conductor pattern 17 provided on the printed wiring board 3 are electrically connected by the wire 15. As a result, a data signal can be output to the outside of the thermal head via the connector 5. At this time, since there is no individual electrode corresponding to the shift register SR2 and the shift register SR3, printing is irrelevant.
Here, the wire is connected to the drive output terminal that is not connected to the heating element 2 of the driving IC 4c, so that the common use of the program at the time of wire bonding and the stabilization of the coating shape of the resin sealing can be achieved.

  In the thermal head having the above-described configuration, the total number of bits of the shift registers connected in the thermal head is 192 × 2 + 64 = 448 bits, so there are no more bits. Compatibility with the head can be maintained.

The block diagram of FIG. 2 shows another embodiment of the driving IC.
As shown in FIG. 2, three shift registers SR1, SR2, and SR3 are provided in the drive IC, and the number of bits per shift register is 64 bits. Therefore, the total number of bits of the shift register in this driving IC is 64 × 3 = 192 bits.

There is one data signal input terminal 11 for serially inputting the data signal SI, and three lines L1, L2 and L3 are individually provided on the output side of each shift register.
Further, a line L0 is provided between the data signal input terminal 11 and the shift register SR2, and a data signal can be directly input from the data signal input terminal 11 to the shift register SR2 by switching the lines as will be described later. It is like that.

  The connection of the lines L0, L1, L2, and L3 is switched by two electronically formed selection switches 19a and 19b provided in the drive IC4. In order to connect from the data signal input terminal 11 to the data signal output terminal 12 via an arbitrary shift register, the selection switches 19a and 19b receive the selection signals SA and SB supplied to the selection terminals 18a and 18b of the selection circuit 14, respectively. It is switched according to the combination of potentials.

Table 2 shows an example of combinations of switching of the selection switches 19a and 19b.

In Table 2, the symbol L representing the potentials of the selection signals SA and SB represents the GND level, and the symbol H represents the level of the power supply voltage (Vdd) of the driving IC.
For example, when the potential of the selection signal SA is L and the potential of the selection signal SB is H, the shift register SR1 and the shift register SR2 are connected via the line L1 by the selection circuit 14 and the selection switch 19a, and the shift register SR2 Is connected to the data signal output terminal 12 via the line L2, and is output to the outside as the data signal SO. At this time, the effective number of bits of the shift register is 128 bits. The data signal is also transferred to the shift register SR3, but there is no corresponding heating element, so it is irrelevant to printing.

As another switching method in which the number of bits of the effective shift register becomes 128 bits, the selection signal SA is set to L level, the potential of the selection signal SB is set to H level, the data signal input terminal 11 and the shift register SR2 are connected to the line L0. Further, the output side of the shift register SR3 may be connected to the data signal output terminal 12 via the line L3.
Further, the number of effective bits can be set to 64 and 192 by selecting the levels of the selection signals SA and SB based on Table 2 and switching the lines.

FIG. 5 is a plan view showing a configuration of a thermal head using a drive IC having the shift register shown in FIG.
The thermal head shown in FIG. 5 is an embodiment in which the total number of bits of the shift register is 576 bits and only 448 bits (the number of heating element dots is 448) are used.
In the thermal head, three drive ICs (total number of bits 192 × 3 = 576 bits) having a 192-bit shift register (64 bits × 3) are provided. In this case, the remaining bits are 128 bits (576-448 = 128). In this embodiment, a method of reducing the number of bits of the shift register by 64 bits in each of the driving ICs 4a and 4c on the input side and output side is adopted. is doing.

  First, setting is made so that the shift register SR1 (FIG. 2) of the input side driving IC 4a is not used. In this case, among the combinations of the number of bits by switching the selection switch shown in Table 2, the corresponding number of bits is set to 128 bits using the shift register SR2 and the shift register SR3. Further, the drive IC 4c on the output side is set not to use only the shift register SR3.

In this case, among the combinations of the number of bits shown in Table 2, the corresponding number of bits is set to 128 bits using the shift register SR2 and the shift register SR3. In this way, the number of bits used in the shift register can be adjusted to 448 bits. At this time, the conductor pattern 7a connected to the data signal output terminal 12 of the drive IC 4c on the output side and the data signal output conductor pattern 17 provided on the printed wiring board 2 are electrically connected by the wire 15 to thereby connect the connector 5. The extra bits can be eliminated by outputting a data signal to the outside of the thermal head.

  When the embodiment shown in FIG. 4 is compared with the embodiment shown in FIG. 5, the arrangement of the drive ICs 4a to 4c and the position of the heating element 2 are asymmetric in the thermal head shown in FIG. 8 becomes longer than necessary, and the problem arises that the conductor resistance of these individual electrodes increases. This causes problems such as a decrease in print density due to the heating element on the right side of the figure.

  On the other hand, in the thermal head shown in FIG. 5, since the remaining bits can be equally distributed to the left and right, the difference in length between the individual electrodes can be reduced, so that the increase in the conductor resistance can be suppressed and the print density varies. Therefore, in the case of a thermal head having a large number of heating element dots, the configuration shown in FIG. 5 is preferable.

In the above embodiment, the number of bits of some of the driving ICs is adjusted. However, it is also possible to change the setting of the number of bits used for all of the driving ICs to the same number.
For example, an example in which the total number of bits of the shift register is 192 × 4 = 768 bits and only 640 bits are used in the thermal head using the driving IC shown in FIG.
At this time, the surplus bits are 768−640 = 128 bits. If the number of driving ICs used is 4, in order to make the number of bits per shift register equal, 640 ÷ 4 = 160 bits.

  In Table 1, when the potential of the selection signal SA is L and the potential of the selection signal SB is L, 160 bits can be assigned to each shift register. In this way, the data signal can be output with an arbitrary number of bits even from one block where the shift register is equally divided, for example, other than the block boundary obtained by dividing 192 bits into 64 equal parts.

Here, when the same number of bits is used for each driving IC, the current consumption can be equalized by performing the division driving by the strobe.
FIG. 6 shows a block configuration diagram using the drive IC having the shift register shown in FIG.
As shown in FIG. 6, the drive IC 4 for the thermal head includes drive output terminals DO-1 to DO-192, a power supply terminal VDD, a ground terminal GND, and a data signal input terminal 11 for a data signal SI to which a data signal is serially input. , One data signal output terminal 12 for outputting the output data signal SO from the shift register to the outside, a clock signal input terminal CLK, selection signal input terminals SA and SB, strobe input terminals STR1, STR2 and STR3, a latch signal input terminal LAT, A division drive control signal input terminal CNT is provided.

  A total of 192 heating element dots (not shown) are connected to the drive output terminals DO-1 to DO-192. A drive transistor 20 is open drain connected to each of the drive output terminals. An AND circuit 21 having one output and two inputs is connected to the gate of each driving transistor 20. The first input terminals of the first to 64th first AND circuits are connected to the strobe input terminal STR1 via the inverter 22a and the EXOR circuit 23a, and the first AND terminals of the 65th to 128th second AND circuits. The input terminal is the strobe input terminal STR2 via the inverter 22b and the EXOR circuit 23b, and the first input terminal of the third AND circuit from the 129th to the 192nd is the strobe input terminal STR3 via the inverter 22c and the EXOR circuit 23c. Are commonly connected to each other.

The second input terminals of the first to 192nd AND circuits are all connected to the output side of the latch circuit LA. The latch circuit (LA) is divided into three groups 24a, 24b and 24c corresponding to the first to third AND circuits. These latch circuits LA are commonly connected to a latch signal input terminal LAT via a buffer 25.
Further, the driving IC 4 includes the three shift registers SR1, SR2, and SR3 described with reference to FIG. Each shift register is formed by connecting 64 stages of data flip-flops D-FF, and the output of each D-FF is connected to be input to the latch circuit LA. The D-FFs are commonly connected to a clock signal input terminal CLK via a buffer 25.

The shift registers SR1 of the shift registers SR1, SR2 and SR3 are connected to the data signal input terminal 11 via the buffer 25. Further, the outputs of the shift registers SR1 to SR3 are switched and connected to the data signal output terminal 12 via the switching circuit 19 constituting the driving IC described in FIG.
The switching circuit 19 is switched according to the levels of the selection signals SA and SB input to the selection circuit 14 formed in the driving IC.
In this drive IC, the three shift registers SR1 to SR3 have only one data signal input terminal 11 and one data signal output terminal 12 as described above.

In the driving IC, when only 128 bits are used for the shift register, the selection switch 19 sets the potential of the selection signal SA of the selection circuit 18 to H and the potential of SB to L based on Table 1 by the selection switch 19. The line L2 from the shift register SR2 is connected to the data signal output terminal 12, and the data signal is output to the outside.
At this time, the corresponding AND circuit is opened by using the strobes STR1 and STR2, and the data signal is sent from the latch circuit to the driving transistor 20 to energize the corresponding heating element dot.

  When the potential of the selection signal SA is H and the potential of SB is H, the selection switch 19 connects the data signal output line L3 from the shift register SR3 to the data signal output terminal SO. At this time, the effective number of bits of the shift register is 192 bits (64 bits × 3) of the shift register SR1, the shift register SR2, and the shift register SR3.

  As described above, when the data signal is input to the shift register and output to the outside, the driving IC of the present invention has the same data signal input terminal and data signal output terminal even if the number of output bits from the shift register changes. Thus, there is no need to additionally provide a plurality of data signal output terminals in the driving IC as in the prior art.

In the case of a thermal head that is used in a low supply voltage range of 5 to 7.2 V, it is common to reduce the number of heating element dots that are driven simultaneously in order to reduce power consumption during printing.
Therefore, as shown in FIG. 6, the strobe circuit is provided to divide and drive the heating element dots in the thermal head. When only 128 bits are used, the strobe signal input to the strobe terminals STR1 and STR2 is shifted and input separately to energize the number of heating element dots to be driven simultaneously in units of 64 bits. Power consumption can be reduced.

FIG. 3 is a block diagram of a main part of a thermal head driving integrated circuit according to the present invention. It is a principal part block diagram of the other integrated circuit for thermal head drive by this invention. It is a top view which shows the shape of the integrated circuit for a thermal head drive by this invention. It is a top view which shows the structure of the thermal head using the integrated circuit for thermal head drive by this invention. It is a top view which shows the other structure of the thermal head using the integrated circuit for thermal head drive by this invention. It is a circuit diagram of a split drive type thermal head using the integrated circuit for driving the thermal head of the present invention. It is a principal part block diagram of the conventional thermal head drive integrated circuit. It is a principal part block diagram of the other conventional integrated circuit for thermal head drive. It is a top view which shows the structure of the thermal head using the conventional integrated circuit for thermal head drive. It is a top view which shows the structure of the thermal head using the other conventional integrated circuit for thermal head drive. It is principal part sectional drawing for demonstrating a general thermal head.

Explanation of symbols

4, 4a, 4b, 4c ..Drive ICs SR1, SR2, SR3 ..Shift register 14 ..Shift register selection circuit formed in drive IC 19 ..Selection switch formed in drive IC

Claims (5)

An integrated circuit for driving a thermal head that controls energization of a plurality of heating elements according to a data signal,
A plurality of shift registers for sequentially transferring and storing serially supplied data signals;
One data signal input terminal provided in the plurality of shift registers;
One data signal output terminal provided in the plurality of shift registers;
Selection means for selecting the number of bits corresponding to the number of heating element dots of the thermal head from the total number of bits of the shift register;
An integrated circuit for driving a thermal head, comprising: 2. The thermal head driving integrated circuit according to claim 1, further comprising switching means for switching the plurality of shift registers in accordance with an output of the selection means. 3. The integrated circuit for driving a thermal head according to claim 1, further comprising a strobe circuit that controls driving for each selected predetermined number of bits among the total number of bits of the plurality of shift registers. The data signal input terminal is disposed at one end of a drive output terminal array connected to the plurality of heating elements, and the data signal output terminal is disposed at the other end of the drive output terminal array. An integrated circuit for driving a thermal head according to claim 1, 2, or 3. A thermal head using the thermal head driving integrated circuit according to claim 1.

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