JPH11154219A - Image recognizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously process plural areas at different positions and also to switch an input image and a processed image without disturbance to output by comparing and processing an optional area of plural images that are stored and deciding the abnormality of an image in each area. SOLUTION: A video signal from a video device such as a camera is converted into a digital video signal by an A/D converting part 1 and is temporarily stored in an input buffer 2. A digital image signal which is read from the buffer 2 is selected by a 1st selector 3 and is outputted. In such a case, an operating part 20 inputs a horizontal size, a vertical size and a coordinate at an upper left of a rectangular area and sets them to an area setting part. An image memory setting part reads image data of the set area, inputs it to the selector 3 and an image processing LSI 6 performs comparison operation processing of the image data. An abnormality deciding part 16b knows the occurrence of abnormality according to the change of an image in each area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image recognition apparatus, and more particularly to the setting of an image processing area and the sequential control of an image memory for storing image signals before and after image processing.

[0002]

2. Description of the Related Art Conventionally, when an image recognition apparatus is used in a security system, for example, as shown in FIG.
And temporarily stores a frame image of the digital video signal in an input buffer 2 composed of four field memories (not shown) prepared exclusively for the luminance signal and the color difference signal for each odd and even number. The frame image in the input buffer 2 and the frame image stored in the image memory 7 are read out, compared and processed by the image processing unit 60, and the processed image is stored in another image memory 7 and processed. When it is determined that the result is abnormal, a warning or the like is issued from the warning means 19 to notify the user. Conventionally, if the entire area is to be subjected to image processing, the processing speed is slow. Therefore, a method has been considered in which a single target area for image processing is determined and processed. The digital image input and converted by the A / D converter 1 and the processed image from the image memory 7 are switched by a switch 90 or the like, and converted into an analog signal by the D / A converter 13 and displayed on a monitor or the like. I was trying to do it. However, this method has a problem that a plurality of regions at different positions cannot be processed simultaneously. Further, when the input image and the processed image stored in the image memory are switched and displayed on the monitor, there is a problem that the image is momentarily disturbed.

[0003]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and can simultaneously process a plurality of areas at different positions, and switch between an input image and a processed image without disturbing the output. It is an object of the present invention to provide an image recognition device capable of performing such operations.

[0004]

According to the present invention, there is provided an A / D converter for converting an input video signal into a digital signal, an input buffer for temporarily storing the digital signal, and an input buffer. An image processing unit which inputs a plurality of digital signals from an input buffer or a plurality of image memories and performs various spatial multiply-accumulation operations between the plurality of signals and various three-screen operations, and processed signals from the image processing unit A plurality of output control units for controlling the output of the plurality of image memories to be selectively input to the serial ports of the plurality of image memories configured by a dual port memory; the plurality of image memories; a digital signal from the A / D conversion unit; A fourth selector for selecting and outputting processed signals from the serial ports of the plurality of image memories, a first output buffer for temporarily storing the signal selected by the fourth selector, A D / A converter for converting a signal from the first output buffer into an analog signal and outputting the analog signal, an image memory controller for sequentially controlling access to at least one area of the plurality of image memories, and a program A main control unit that controls the respective units according to the program, and a RAM that temporarily stores data such as calculation results from the image processing unit when the main control unit executes the program. , RAM
An abnormality determination unit that determines an abnormality in the calculation result temporarily stored in the memory and outputs an abnormality signal, and an operation unit that inputs a setting of a predetermined area in the image memory, a designation of a processing mode, and the like. Based on the conditions set by the
Processing the input video signal, storing the same, comparing at least one arbitrary region of the stored plurality of images, determining the abnormality of the image in each region, outputting an abnormal signal By operating the operation unit,
An image recognition device capable of switching and monitoring an input video signal and a processed video signal.

A first selector for selecting three digital signals from the input buffer or a plurality of image memories and outputting first, second, and third signals;
A first 1HDL (1H delay line) for delaying the third signal by 1H and outputting a 1H delay signal, and a first 1H
A second 1HDL for delaying the 1H delay signal of the DL by 1H and outputting a 2H delay signal, a second selector for selectively outputting the first signal or the 2H delay signal, and the second signal or the 1H delay signal A third selector for selecting and outputting
Inputting the signal from the second selector, the signal from the third selector, and the third signal to perform various spatial product-sum operations;
It consists of an image processing LSI that performs various three-screen calculations.

A superimposition section is provided between the first output buffer and the D / A conversion section, and an overlay image memory for storing characters and the like, and an overlay signal from the overlay image memory are temporarily stored. A second output buffer is provided, and signals from the first output buffer and the second output buffer are input to the superimposing unit and superimposed.

[0007] A processed signal from the image processing unit can be stored in the overlay image memory via the output control unit.

An alarm means such as a buzzer for notifying an abnormality is connected to the abnormality determination section.

An I / F for connecting to an external personal computer or the like is connected to the main control unit. The external personal computer sets a predetermined area in the image memory, designates a processing mode, and sets the processing result to a personal computer or the like. Output to external devices.

An input timing generator for generating an input timing signal such as an input clock in synchronization with the input video signal; and a processing timing such as a processing clock in synchronization with the processing of the image processing unit A processing system timing generator for generating a signal; and a timing selector for switching a control signal and a write clock of the first output buffer to the input system timing signal or the processing system timing signal. The timing of switching the fourth selector to switch the writing from the input image to the image from the image memory is determined by the first switch.
The writing of the input image to the output buffer is completed when one frame is completed, and at the same time, the timing selector is switched from the input timing signal to the processing timing signal.

In order to switch the writing to the first output buffer from the image from the image memory to the input image, a fourth
Is switched at the end of frame input of the input video signal, and at the same time, the timing selector is switched from the processing timing signal to the input timing signal.

The switching of the timing selector is performed when the writing of the input image to the first output buffer is completed for one frame, that is, while the fourth selector is selecting the input image, At the time when the frame signal was detected.

One odd field input field memory and one even field input field memory are used for the input buffer, and the luminance signal of the odd field is written into the odd field input field memory from the head address, and the color difference signal is written to the even field. The field memory for field input is written from the address one field ahead of the head address, the luminance signal of the even field is written to the field memory for even field input from the head address, and the color difference signal is written to the field memory for odd field input from the head address. By writing from the address one field ahead, the memory is used effectively.

An input system clock from the input system timing generator is used as a write clock to the input buffer, and processing of a higher frequency than an input system clock from the processing system timing generator is used as a read clock from the input buffer. A system clock, and a timing operation unit is provided. The timing operation unit calculates a timing at which the writing to the input buffer is not overtaken immediately before the writing to the input buffer is completed for one frame. Start reading from.

An input read setting unit for setting reading from the input buffer; an output of the input read setting unit; and a first AN which inputs and outputs the processing system clock.
D circuit is provided, and the output of the first AND circuit is used as a read clock for the input buffer.

A processing system clock having a higher frequency than an input system clock from the processing system timing generator is used as a write clock to the output buffer, and an input from the input system timing generator is used as a read clock from the output buffer. A system clock is used, and a timing calculation unit is provided. The timing calculation unit calculates a timing at which writing to the output buffer does not overtake reading from the output buffer, and starts writing to the output buffer at the same timing. I did it.

An output write setting section for setting the writing of the output buffer; a second AND circuit for receiving the output of the output write setting section and the input system clock and performing an AND output; The output from the second AND circuit was used as a write clock for the output buffer.

The image memory control section includes an area setting section for setting an arbitrary rectangular area in the image memory, and an access type of each image memory (read from area 1, read from area 2, read from area 2, area 2, an image memory access mode setting unit for setting writing, no access, etc.
An image memory address generator that generates an address corresponding to the rectangular area, a horizontal size counter that counts the horizontal size of the area, and counts the vertical size of the area, and transfers the area address to the image memory address generator. A vertical size counter to be supplied, an image memory arbitration unit that arbitrates an image memory bus of each image memory,
The horizontal size counter and the vertical size counter are controlled to be activated by a start command from the main control unit, and a read transfer cycle request is sent to the image memory arbitration unit.
A sequence control unit that outputs an access request such as a write transfer request; and, when the access request is permitted from the image memory arbitration unit, control is performed to the image memory corresponding to the access request set in the image memory access mode setting unit. An image recognition device comprising an image memory control signal generation unit for inputting a signal.

A timer is provided in the image memory control unit, and image processing is automatically performed at predetermined time intervals.

A horizontal coordinate setting section for setting a horizontal start address of at least one rectangular area; a vertical coordinate setting section for setting a vertical start address (hereinafter referred to as vertical coordinate); The image recognition apparatus includes a horizontal size setting unit that sets a transfer size in the horizontal direction (hereinafter referred to as a horizontal size) and a vertical size setting unit that sets a transfer size in the vertical direction (hereinafter referred to as a vertical size).

The horizontal size counter counts the processing clock. When the count of the horizontal counter matches the horizontal size set in the horizontal size setting section of the area setting section, the coincidence signal is sent to the sequential control section. A horizontal size comparison unit, a horizontal auxiliary counter that starts up the sequential control unit by the same coincidence signal and starts counting the processing clock, and when the count output from the horizontal auxiliary counter reaches a predetermined constant value, An image recognition device comprising a decoder for outputting a decode signal.

The vertical size counter sets a vertical coordinate set in a vertical coordinate setting section of the area setting section as an initial value,
At least one vertical counter that counts the number of decode signals of a constant value input to the sequential control unit and outputs a vertical address, and the count number (vertical address-vertical coordinate) of the same vertical counter are determined by the area setting unit. An image recognition device comprising a vertical size comparison unit that inputs a match signal to the sequential control unit when the vertical size matches the vertical size set in the vertical size setting unit.

The image memory address generating section selects a vertical address from each vertical counter of the vertical size counter or a vertical address from the main control section, and sets each horizontal coordinate of the area setting section. Or a horizontal address selector for selecting a horizontal address from the main control unit, and a multiplexer for inputting a vertical address from the vertical address selector and a horizontal address from the horizontal address selector to an address bus of an image memory. The device.

[0024]

As described above, in the image recognition apparatus of the present invention, an A / D converter for converting an input video signal into a digital signal, an input buffer for temporarily storing the digital signal, A first selector for selecting three digital signals from the input buffer or a plurality of image memories to be described later and outputting first, second, and third signals; and delaying the third signal by 1H to 1H First 1H for outputting a delayed signal
DL (1H delay line) and 1 of the first 1HDL
The second which outputs the 2H delay signal by delaying the H delay signal by 1H
1HDL, a second selector for selectively outputting the first signal or the 2H delay signal, and the second signal or 1H.
A third selector for selecting and outputting an H-delay signal;
, The signal from the third selector and the third signal are input to perform various spatial product-sum operations,
An image processing LSI that performs inter-screen calculations and an image processing LSI
A plurality of output controllers for controlling the output of the processed signal and selectively inputting the serial ports of the plurality of image memories comprising a dual port memory; the plurality of image memories; and an overlay for storing characters and the like. Image memory,
A fourth selector for selecting and outputting a digital signal from the A / D converter and a processed signal from a serial port of the plurality of image memories; and temporarily storing a signal selected by the fourth selector. A first output buffer, a second output buffer for temporarily storing an overlay signal from the overlay image memory, and a superimposing unit for superimposing signals from the first output buffer and the second output buffer. A D / A conversion unit for converting a superimposed signal from the superimposition unit into an analog signal and outputting the analog signal; an image memory control unit for sequentially controlling access to at least one of the plurality of image memories; R
OM, a main control unit for controlling the respective units in accordance with the program, a RAM for temporarily storing data and the like, such as calculation results from the image processing LSI, when the main control unit executes the program, An abnormality determination unit that determines that there is an abnormality in the calculation result temporarily stored in the operation unit; an operation unit that inputs a setting of a predetermined area in the image memory, a processing mode designation, and the like; An alarm means such as a buzzer for notifying the user and an I / F connected to an external personal computer or the like. The input video signal is processed based on conditions set by operating the operation unit or controlling from the external personal computer. Then, this is stored, at least one arbitrary region of the stored plurality of images is compared, and as a result of the processing, an abnormality of the image in each region is determined. -To output a processing result to an external device such as a personal computer while operating an operation unit, and monitor the input video signal and the processed video signal by switching them without disturbing the screen. Can be.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image recognition apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 1 is an overall block diagram showing an embodiment of an image recognition device according to the present invention. As shown in FIG. 1, reference numeral 1 denotes an A / D converter for converting a video signal from a video camera or the like into a digital video signal. 2 is the A / D
This is an input buffer for temporarily storing the digital video signal from the conversion unit 1, and comprises an odd field memory 2e and an even field memory 2f. At this time, the luminance signal of the odd field is written from the head address of the odd field memory 2e, and the color difference signal of the odd field is written from the address one field ahead of the even field memory 2f. In half the usual amount. Reference numeral 3 denotes a first selector which selects three digital video signals from the input buffer 2 and three digital signals from image memories 8 (8a, 8b, 8c, 8d) to be described later, and selects first, second, and third digital signals. 3 is output. 4a is the first 1HDL (1H delay line), 4
b is a second 1HDL (1H delay line). 5
a and 5b are a second selector and a third selector, and the second selector 5a is the first signal or the first 1HDL4.
a and the 2H delay signal that has passed through the second 1HDL 4b is selectively output, and the third selector 5b is configured to selectively output the 2H delay signal that has passed through the second signal or the first 1HDL 4a. Reference numeral 6 denotes an image processing LSI, which receives the signal from the second selector 5a, the signal from the third selector 5b, and the third signal from the first selector to perform various spatial product-sum operations, Inter-screen calculations are being performed.

Reference numeral 7 (7a, 7b, 7c, 7d, 7e) denotes an output control unit which controls the output of the processed signal from the image processing LSI 6 to form the plurality of image memories 8 (8a , 8b, 8c, 8d, 8e). 8 (8a, 8b,
8c, 8d, 8e) are the plurality of image memories constituted by a dual port memory, of which the image memory 8e stores an overlay signal such as a character. Reference numeral 9 denotes a fourth selector, which inputs the digital video signal from the A / D converter 1 and the image memory 8
(8c, 8d) and the processed signal from the serial port are selected and output. Reference numerals 9a and 9b denote timing selectors for switching between an input system timing signal from an input system timing generator 21 and a processing system timing signal from a processing system timing generator 22 to be input to an output buffer or the like. Reference numeral 10 denotes a first output buffer for temporarily storing the digital image signal selected by the fourth selector. Reference numeral 11 denotes a second output buffer for temporarily storing an overlay signal of the overlay image memory 8e as an image signal. A superimposing unit 12 superimposes an overlay image signal such as a character from the second output buffer 11 on the digital image signal from the first output buffer 10. A D / A converter 13 converts the digital image signal from the superimposing unit 12 into an analog signal.

Reference numeral 14 denotes an image memory control unit for controlling writing and reading of the image memories 8. 15 is RO
The program is stored in M. A main control unit 16 controls each unit according to a program stored in the ROM. Reference numeral 16a denotes a timing calculation unit which calculates write and read timings of the input buffer 2, the first output buffer 10, and the second output buffer 11. An abnormality determination unit 16b determines an abnormality in an image based on an image change before and after image processing. 17 is RA
At M, data and the like are temporarily stored when the main control unit 16 executes the program in the ROM 15. A serial I / F 18 is connected to an external personal computer or the like to perform data communication. Reference numeral 19 denotes a warning unit which sounds a buzzer or the like to notify the abnormality when the abnormality determination unit 16b determines that the abnormality is abnormal. Reference numeral 20 denotes an operation unit which is an input unit for setting a processing target area of the image memory, a timer, and the like.

Reference numeral 21 denotes the input timing generator for generating and outputting an input timing signal such as an input clock from a synchronization signal of the input video signal. Reference numeral 22 denotes the processing system timing generator that generates and outputs a processing system timing signal such as a processing system clock supplied to the image memory or the like. The frequency of the processing clock generated by the processing timing generator 22 is higher than the frequency of the input clock generated by the input timing generator 21.

FIG. 2 shows a read clock input section 2g for inputting a read clock to the input buffer 2 of the image recognition apparatus according to the present invention, and a write for inputting a write clock to the first output buffer 10 and the second output buffer 11. FIG. 3 is a main part block diagram showing one embodiment of clock input units 10a and 11a. As shown in FIG.
g is an input read setting unit 2ga that sets reading from the input buffer 2, an output of the input read setting unit 2g, and a first AND circuit 2gb that inputs the processing system clock and outputs the result. And the first AND circuit 2
The output of gb is used as a read clock for the input buffer 2. Further, the main control unit 16 is provided with a timing calculation unit 16a, and the timing calculation unit 16a sets the timing immediately before the writing to the input buffer 2 ends one frame.
The input read setting unit 2ga is set so as to calculate the timing at which the writing of 2 to the input buffer is not overtaken and start reading from the input buffer 2 at the same timing.

The write clock input sections 10a, 1a
1a is an output write setting unit 10a for setting the writing of the first output buffer 10 and the second output buffer 11
a, 11aa, and the same output write setting units 10aa, 11aa
And the second AND circuits 10ab and 11ab which receive the output of the input circuit and the input system clock and output the result. The outputs from the second AND circuits 10ab and 11ab are output to the first output buffer 10 or Second output buffer 1
1 write clock. In addition, the timing calculation unit 16a writes the first output buffer 10 or the second output buffer 11 to the output buffer 1 or the second output buffer 11.
The output write setting unit 10a calculates a timing at which the reading from the output buffers 0 and 11 is not overtaken and starts writing to the output buffers 10 and 11 at the same timing.
a and 11aa are set.

FIG. 3 is a main block diagram showing the configuration of the image memory control unit 14. As shown in FIG. As shown in the figure, the image memory control unit 14 includes an area setting unit 14a for setting an arbitrary rectangular area in the image memory 8 and the image memory 8
And an image memory access mode setting unit 14b for setting an access type (reading from the area 1, reading from the area 2, writing to the area 2, no access, etc.) and an address corresponding to the rectangular area. An image memory address generator 14c, a horizontal size counter 14d for counting the horizontal size of the area, a vertical size counter 14e for counting the vertical size of the area and supplying an area address to the image memory address generator 14c. An image memory bus arbitration unit 14f for arbitrating the image memory bus of each image memory 8, and the horizontal size counter 14 according to a start command from the main control unit 16.
d, a sequence control unit 14g for controlling the activation of the vertical size counter 14e and outputting an access request such as a read transfer cycle request and a write transfer request to the image memory arbitration unit 14f, and the access request from the image memory arbitration unit 14f. Is permitted, an image memory control signal generating unit 14h for inputting a control signal to the image memory 8 corresponding to the access request set in the image memory access mode setting unit 14b, and a timer for outputting a time interval of image processing 14i.

The area setting section 14a includes an area 1 setting section for setting a first area and an area 2 setting section for setting a second area. Each of the area setting sections 14a sets a horizontal start address. Horizontal coordinate setting units 14ah1, 14a
h2 and vertical coordinate setting units 14av1 and 14av2 for setting a vertical start address (hereinafter referred to as vertical coordinates).
And a horizontal size setting unit 14ahs for setting a transfer size in the horizontal direction (hereinafter referred to as a horizontal size), and a vertical size setting unit 14vs for setting a transfer size in the vertical direction (hereinafter referred to as a vertical size). . In the present embodiment, the first area and the second area have the same size so that the first area and the second area can be compared.

The horizontal size counter 14d is
Horizontal counter 14d for counting the processing system clock
When the count of the horizontal counter 14d1 matches the horizontal size set in the horizontal size setting section 14hs of the area setting section 14a, the horizontal size comparison section 14d2 inputs a match signal to the sequential control section 14g. The horizontal auxiliary counter 14d3 which starts the sequential control unit 14g by a signal to start counting the processing system clock, and a decoder 14d4 which outputs a decode signal when the count output from the horizontal auxiliary counter 14d3 becomes a predetermined constant value. It consists of:

The vertical size counter 14e is provided with vertical coordinate setting units 14av1, 14av of the area setting unit 14a.
The vertical counters 14e1 and 14e2, which load the vertical coordinate set to 2 as an initial value, count the number of decoding signals of a constant value input to the sequential control unit 14g, and output a vertical address, and counts of the vertical counter 14e1 When the number (vertical address-vertical coordinate) matches the vertical size set in the vertical size setting section 14vs of the area setting section 14a, a vertical size comparison section 14e3 which inputs a coincidence signal to the sequential control section 14g.

The operation of the above configuration will be described next. First, the overall operation will be described with reference to FIG. A video signal from a video device such as a camera is A / D
The data is converted into a digital video signal by the conversion unit 1 and stored in the temporary input buffer 2. At this time, the luminance signal of the odd-numbered field is written from the head address of the odd-numbered field memory 2e, and the color difference signal of the odd-numbered field is written from the address one field ahead of the even-numbered field memory 2f. In half. The write clock to the input buffer 2 is written using the input system clock. For reading from the input buffer 2, a processing system clock is used.
Immediately before the writing of the frame is completed, a timing at which the writing is not overtaken is calculated by the timing calculation unit 16a and read. The digital image signal read from the input buffer 2 is supplied to a first selector 3
Is selected and output. For example, the digital image signal from the input buffer 2 is sequentially output from the first signal output terminal of the first selector 3, and the second selector 5a and the third selector 5b are controlled to control the digital image signal, 1H
The signal delayed by 1H by the DL (1H delay line) 4a and the signal further delayed by 1HDL 4b are input to the image processing LSI 6, and are processed and output. In this case, the 3H digital image is subjected to the comparison operation processing, and can be used for recognition of the position of the boundary line or the like. Further, for example, a digital image signal from the input buffer 2 is output from a first signal output terminal of the first selector 3, and an image signal of a frame before being stored in an image memory 8a from a second signal output terminal; By outputting the image signal of the previous frame before being stored in the image memory 8b from the third signal output terminal and inputting each to the image processing LSI,
Since the comparison calculation processing can be performed on a frame-by-frame basis, the abnormality determination unit 16b can know the occurrence of an abnormality based on a change in an image between frames. The image signals subjected to the image processing in this way are selectively output through the output control unit 7 (7a to 7d), input to the desired serial port of the image memory 8 (8a to 8d), and then output. Image memory 8 (8a to 8d)
Is transferred and stored in the RAM.

In the above, a case has been described in which image processing is performed on the entire screen. However, processing the entire screen not only requires time for image processing, but also impairs the reliability of the abnormality determination. Therefore, in order to save processing time and improve the reliability of abnormality determination, a processing target area of the image memory 8 can be set to limit the processing range. To set the area, the horizontal size and the vertical size and the upper left coordinates (horizontal coordinates and vertical coordinates) of the rectangular area are input from the operation unit 20 and set in the area setting unit. For example, when two regions are provided, the sizes of the two regions are the same so that the image signals in both regions can be subjected to the comparison operation processing. When this area is set, the image memory control unit reads out the image data of the set area, inputs the read image data to the first selector 3, and performs a comparison operation on the image data in the image processing LSI 6. ing.

Next, a case will be described in which, while an input video signal is being displayed, a processed image signal that has been subjected to image processing is read from the image memory 8 and displayed on a monitor or the like. The digital video signal from the A / D converter 1 is also input to the fourth selector 9. The fourth selector 9 receives the processed image signals from the image memory 8c and the image memory 8d and outputs any one of the signals.
Now, in order to switch the fourth selector 9 and display the processed image signal read from the image memory 8 on a monitor or the like,
When the writing of the input image to the first output buffer 10 is completed for one frame, the fourth selector 9 is switched, and at the same time, the timing selector 9a / 9 is switched.
b is switched from the input timing signal to the processing timing signal. Similarly, to switch from the processed image to the input image, the fourth selector is switched at the end of the frame input of the input video signal, and at the same time, the timing selectors 9a / 9b are switched from the processing system timing signal to the input system timing signal. To As a result, it is possible to switch from the input image to the processed image or from the processed image to the input image without disturbing the display screen.

Next, the image memory controller 14 shown in FIG.
Will be described. FIG. 4 is an operation flowchart showing the operation of the image memory control unit 14. Here, a case will be described in which two rectangular areas are set, and the two rectangular areas, area 1 and area 2, are accessed. When the setting of the rectangular area is completed, the access type of each image memory 8 is set. For example, a case will be described in which an image in the area 1 of the image memory 8a is compared with an image in the area 2 of the image memory 8b and then stored in the area 2 of the image memory 8c. First, reading of the area 1 is set in the image memory 8a, reading of the area 2 is set in the image memory 8b, writing of the area 2 is set in the image memory 8c, and no access is set in the other image memories 8d and 8e. When the transfer cycle sequence block is started (started) by a time-up signal of the timer 14i or the like, the sequence control unit 14g issues a read transfer cycle request for the area 1 to the image memory bus arbitration unit 14f.
(ST1), and waits for permission (ST2). When permission is issued from the image memory bus arbitration unit 14f (ST2-Y),
The read control signal is input from the image memory control signal generator 14h to the image memory 8a in which the reading of the area 1 is set, and the address initial value (upper left coordinate) of the area 1 is output from the image memory address generator 14c (ST3). ), And waits for completion of reading of area 1 (ST4). Completion of reading of area 1 (S
T4-Y) Then, similarly, a read transfer cycle request for area 2 is issued (ST5), and permission is waited for (ST5).
6). When permitted (ST6-Y), read control is input to the image memory 8a in which reading of the area 1 is set and the image memory 8b in which reading of the area 2 is set.
The address initial value (upper left coordinate) is output (ST7).
Wait for the reading of the area 2 to be completed (ST8). When reading of the area 2 is completed (ST8-Y), a write transfer cycle request for the area 2 is issued (ST9), and permission is waited for (ST1).
0). When it is permitted (ST10-Y), a write control signal is output to the image memory 8c set to write the area 2, and the initial address of the area 2 (the upper left coordinate)
(ST11), and waits for completion of writing in the area 2 (ST12). Completion of writing in area 2 (ST12-Y)
Then, the next sequence block is executed.

Next, the operation of the horizontal size counter will be described with reference to the operation flowchart shown in FIG. As described above, when the transfer cycle sequence block is started (started) by a time-up signal of the timer 14i or the like, the sequence control unit 1
4g activates the transfer cycle sequence block and activates the horizontal size counter 14d (ST).
21) Then, the horizontal counter 14d1 sets the horizontal size Hs set in the horizontal size setting section 14hs of the area setting section 14a.
Wait for a match with (ST22). When it matches the horizontal size Hs (ST22-Y), a read transfer cycle request for the area 1 is issued (ST23), and waiting for permission (ST24). When permitted (ST24-Y), a read control signal is output to the image memory 8a set to read the area 1 (ST25).
On the other hand, when it matches the horizontal size Hs (ST22-Y), the horizontal auxiliary counter 14d3 is activated (ST27) and waits for a constant value (ST28). Horizontal auxiliary counter 1
When 4d3 becomes a constant value (ST28-Y), a write transfer cycle request for the area 2 is issued (ST29), and waiting for permission (ST30). When permission is granted (ST30-Y), the area 2
A write transfer cycle is performed on the image memory 8c in which writing of data is set (ST31), and the completion is waited (ST3).
2). Upon completion (ST32-Y), the area 2 vertical counter 14e2 is counted up (ST43),
It issues a read transfer cycle request for area 2 (ST33) and waits for permission (ST34). Allowed (ST34-Y)
And a read transfer cycle is performed on the image memories 8b and 8c set to read or write in the area 2 (ST3).
5) Wait for completion (ST36). End (ST35-
Y) and a write request for the area 2 is issued (ST37), and waiting for permission (ST38). If permitted, the writing is performed in the area 2 of the image memory 8c set to the writing of the area 2 (ST39) and the completion is awaited (ST40). Complete (S
T40-Y), the completion signal is input to the area 1 vertical size counter 14e1, and the area 1 vertical counter 14e1 is counted up (ST41). As described above, 1H of the signal of the area 1 of the image memory 8a and the signal of the area 2 of the image memory 8b are subjected to the comparison operation processing and stored in the image memory 8c.

Next, the operation of the vertical size counter will be described with reference to the operation flowchart of FIG. The operation of the vertical size counter 14e is as follows. When the sequence control unit is activated and started, first, the area 1 vertical counter 14e
1 and the area 2 vertical counter 14e2, the area setting unit 14a
, And the upper left vertical coordinates set in (ST51, ST55). Vertical counter 1 in area 1
4e1 is the end of the write transfer cycle immediately after the start shown in FIG. 4 (ST12) or the end of ST39 in FIG. 5 (ST12).
Wait for 40) (ST52). End (ST52-Y)
Then, the area 1 vertical counter 14e1 is counted up (ST53). It is checked whether the count number of the area 1 vertical count 14e1 has reached (vertical coordinate of area 1 + vertical size) (ST54). If the count number does not reach (vertical coordinate of area 1 + vertical size), The process returns to ST52). When the count reaches (vertical coordinate + vertical size) in ST54, the sequence cycle ends. On the other hand, the area 2 vertical counter 14e2
31 (ST56), and ends (ST56-
Y), the area 2 vertical counter 14e2 is counted up (ST57).

The operation of the image memory control unit 14 will be described for the case where the image in the area 1 of the image memory 8a is compared with the image in the area 2 of the image memory 8b and stored in the area 2 of the image memory 8c. However, the setting of the area, the setting of the reading and the writing, and the like can be set by the user from the operation unit in accordance with the purpose of use, so that a wide range of usage is possible.

[0042]

As described above, according to the image recognition apparatus of the present invention, an A / D converter for converting an input video signal into a digital signal, an input buffer for temporarily storing the digital signal, By selecting three digital signals from the same input buffer or a plurality of image memories described later,
A first selector for outputting second and third signals;
1H that outputs the 1H delay signal by delaying the signal of
HDL (1H delay line), a second 1HDL that delays the 1H delay signal of the first 1HDL by 1H and outputs a 2H delay signal, and a second that selectively outputs the first signal or the 2H delay signal. A selector, a third selector for selecting and outputting the second signal or the 1H delay signal, and inputting a signal from the second selector, a signal from the third selector, and a third signal to obtain various spaces. Image processing LSI that performs multiply-accumulate operation and various three-screen calculations, and image processing LSI
A plurality of output control units for controlling the output of the processed signal from the I and selectively inputting the serial ports of the plurality of image memories comprising a dual port memory; the plurality of image memories; and an overlay for storing characters and the like. And a fourth selector for selecting and outputting a digital signal from the A / D converter and a processed signal from the serial ports of the plurality of image memories. A first output buffer for temporarily storing the output signal, a second output buffer for temporarily storing the overlay signal from the overlay image memory, and a signal from the first output buffer and the second output buffer. A D / A conversion unit that converts a superimposed signal from the superimposition unit into an analog signal and outputs the analog signal, and at least an arbitrary one of the plurality of image memories. An image memory control section for sequentially controlling access to two areas, a ROM for storing a program, a main control section for controlling the respective sections in accordance with the program, and temporarily executing the image processing when the main control section executes the program. A RAM for storing data such as calculation results from the LSI, an abnormality determination unit for temporarily determining whether there is an abnormality in the calculation results temporarily stored in the RAM, setting of a predetermined area in the image memory, processing mode An operation unit for inputting designations and the like, and a determination result of the abnormality determination unit,
An alarm means such as a buzzer for notifying an abnormality, and an I / F connected to an external personal computer or the like. The input video signal is transmitted based on conditions set by operating the operation unit or control from the external personal computer. Process, storing this, comparing at least one arbitrary region of the stored plurality of images, and determining the abnormality of the image in each region as a result of the processing, and when it is determined that the image is abnormal, an alarm such as a buzzer is issued. By outputting the processing result to an external device such as a personal computer and operating the operation unit, the input video signal and the processed video signal can be switched and monitored without disturbing the screen.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing an embodiment of an image recognition device according to the present invention.

FIG. 2 is a main block diagram showing an embodiment of a read clock input unit 2g and write clock input units 10a and 11a of the image recognition device according to the present invention.

FIG. 3 is a main block diagram showing a configuration of an image memory control unit 14;

FIG. 4 is an operation flowchart showing an operation of the image memory control unit 14;

FIG. 5 is an operation flowchart showing an operation related to a horizontal size counter of the image memory control unit 14;

FIG. 6 is an operation flowchart showing an operation related to a vertical size counter of the image memory control unit 14;

FIG. 7 is a block diagram illustrating an example of a conventional image recognition device.

[Explanation of symbols]

 Reference Signs List 1 A / D conversion unit 2 Input buffer 2e Odd field memory 2f Even field memory 2g Read clock input unit 2ga Input read setting unit 2gb First AND circuit 3 First selector 4a First 1HDL (1H delay line) 4b 2nd 1HDL (1H delay line) 5a 2nd selector 5b 3rd selector 6 Image processing LSI 7 (7a, 7b, 7c, 7d, 7e) Output control unit 8 (8a, 8b, 8c, 8d, 8e) Image memory 9 Fourth selector 9a, 9b Timing selector 10 First output buffer 10a Write clock input unit 10aa Output write setting unit 10ab Second AND circuit 11 Second output buffer 11a Write clock input unit 11aa Output write setting unit 11ab Second AND circuit 12 Superposition unit 13 D / A conversion Unit 14 image memory control unit 14a area setting unit 14ah1 horizontal coordinate setting unit for region 1 14ah2 horizontal coordinate setting unit for region 2 14av1 vertical coordinate setting unit for region 1 14av2 vertical coordinate setting unit for region 2 14ahs horizontal size setting unit 14avs vertical size Setting unit 14b Image memory access mode setting unit 14c Image memory address generation unit 14d Horizontal size counter 14d1 Horizontal counter 14d2 Horizontal size comparison unit 14d3 Horizontal auxiliary counter 14d4 Decoder 14e Vertical size counter 14e1 Area 1 vertical counter 14e2 Area 2 vertical counter 14e3 Vertical size Comparison unit 14f Image memory bus arbitration unit 14g Sequence control unit 14h Image memory control signal generation unit 14i Timer 15 ROM 16 Main control unit 16a Timing calculation 16b abnormality determination unit 17 RAM 18 Serial I / F 19 alarm means 20 operating portion 21 input system timing generator 22 processing system timing generator

Claims (20)

[Claims] 1. An A / D converter for converting an input video signal into a digital signal, an input buffer for temporarily storing the digital signal, and a plurality of digital signals from the input buffer or a plurality of image memories. An image processing unit for performing various spatial multiply-accumulation operations between a plurality of signals and various three-screen operations, and a plurality of dual port memories configured to control output of processed signals from the image processing unit. A plurality of output control units for selectively inputting to the serial port of the image memory;
A plurality of image memories, a fourth selector for selecting and outputting a digital signal from the A / D converter and a processed signal from a serial port of the plurality of image memories,
A first memory for temporarily storing the signal selected by the fourth selector;
An output buffer, a D / A converter for converting a signal from the first output buffer into an analog signal and outputting the analog signal, and an image memory for sequentially controlling access to at least one of the plurality of image memories A control unit;
A ROM that stores a program, a main control unit that controls the units according to the program, and a RAM that temporarily stores calculation results and the like from the image processing unit when the main control unit executes the program. And the RA
An abnormality determination unit that determines an abnormality of the calculation result temporarily stored in M and outputs an abnormality signal, and an operation unit that inputs a setting of a predetermined area in the image memory, a processing mode designation, and the like,
Based on the conditions set by operating the operation unit, process the input video signal, store this, compare at least one area of the stored plurality of images, the processing result, By judging abnormalities of the image in each area, outputting an abnormal signal, and operating the operation unit,
An image recognition apparatus characterized in that an input video signal and a processed video signal can be switched and monitored. A first selector for selecting three digital signals from the input buffer or a plurality of image memories and outputting first, second, and third signals; and A first 1HDL (1H delay line) that outputs a 1H delay signal by delaying the signal of No. 3 by 1H, and a second 1HDL that outputs a 2H delay signal by delaying the 1H delay signal of the first 1HDL by 1H. , The first signal or 2H
A second selector for selecting and outputting a delay signal; a third selector for selectively outputting the second signal or the 1H delay signal; a signal from the second selector; a signal from the third selector; 2. The image recognition apparatus according to claim 1, comprising an image processing LSI which performs various spatial multiply-accumulate operations and various three-screen operations by inputting the above signals. 3. An overlay image memory for storing a character or the like, and an overlay signal from the overlay image memory for temporarily storing a character or the like, between the first output buffer and the D / A converter. 2. The image recognition apparatus according to claim 1, further comprising a second output buffer for storing, wherein signals from the first output buffer and the second output buffer are input to the superimposing unit and superimposed. apparatus. 4. The image recognition apparatus according to claim 3, wherein a processed signal from said image processing unit can be stored in said overlay image memory via said output control unit. 5. The image recognition apparatus according to claim 1, wherein an alarm means such as a buzzer for notifying an abnormality is connected to the abnormality determination section. 6. An I / F for connecting to an external personal computer or the like is connected to the main control unit, and the setting of a predetermined area in the image memory, the setting of a processing mode, and the like are set from the external personal computer, and the processing result is transmitted to the personal computer. 2. The image recognition device according to claim 1, wherein the image is output to an external device. 7. An input system timing generator for generating an input system timing signal such as an input system clock in synchronization with the input video signal, and a processing system clock or the like in synchronization with the processing of the image processing unit A processing system timing generator for generating a system timing signal; and a timing selector for switching a control signal and a write clock of the first output buffer to the input system timing signal or the processing system timing signal. The timing at which the fourth selector is switched to switch the writing of the input image from the input image to the image from the image memory is the time when the writing of the input image to the first output buffer is completed for one frame, and at the same time, the timing selector Is switched from the input timing signal to the processing timing signal. 2. The image recognition device according to claim 1, wherein: 8. A timing for switching a fourth selector to switch writing to the first output buffer from an image from an image memory to an input image is defined as the end of frame input of an input video signal. 8. The image recognition apparatus according to claim 7, wherein the control unit switches from the processing system timing signal to the input system timing signal. 9. The switching of the timing selector,
When the writing of the input image to the first output buffer is completed for one frame, that is, when the fourth selector is selecting an input image, and when detecting a frame signal from the input system timing generator, and The image recognition device according to claim 7, wherein 10. An odd-numbered field input field memory and an even-numbered field input field memory are respectively used in the input buffer, and a luminance signal of an odd-numbered field is written from an initial address into an odd-numbered field input field memory, and a chrominance signal is input. Is written to the field memory for even-numbered field input from the address one field ahead of the head address, the luminance signal of the even-numbered field is written to the field memory for even-numbered field input from the head address, and the color difference signal is written to the odd-numbered field input field memory. 2. The image recognition apparatus according to claim 1, wherein the memory is effectively used by writing from an address one field ahead of the address. 11. An input clock from the input timing generator is used as a write clock to the input buffer, and a frequency higher than an input clock from the processing timing generator is used as a read clock from the input buffer. And a timing calculation unit is provided. The timing calculation unit calculates a timing at which the writing to the input buffer does not overtake the writing to the input buffer immediately before the writing to the input buffer ends one frame. 8. The image recognition apparatus according to claim 7, wherein reading from the input buffer is started. 12. An input reading setting unit for setting reading from the input buffer, an output of the input reading setting unit,
10. The image recognition apparatus according to claim 9, further comprising: a first AND circuit that inputs the processing system clock and performs AND output, and an output of the first AND circuit is used as a read clock of the input buffer. apparatus. 13. A processing system clock having a higher frequency than an input system clock from the processing system timing generator is used as a write clock to the output buffer, and a clock from the input system timing generator is used as a read clock from the output buffer. And a timing calculation unit is provided, the timing calculation unit calculates a timing at which writing to the output buffer does not overtake reading from the output buffer, and performs writing to the output buffer at the same timing. 8. The image recognition apparatus according to claim 7, wherein the apparatus is started. 14. An output write setting unit for setting the writing of the output buffer, an output of the output write setting unit, and a second AN that inputs and outputs the input system clock.
14. The image recognition apparatus according to claim 13, further comprising a D circuit, wherein an output from the second AND circuit is used as a write clock for the output buffer. 15. An image memory control unit, comprising: an area setting unit for setting an arbitrary rectangular area in the image memory; and an access type of each of the image memories (read from area 1 and read from area 2). , Writing to area 2, no access, etc.), an image memory address generator for generating an address corresponding to the rectangular area, and a horizontal size counter for counting the horizontal size of the area A vertical size counter that counts the vertical size of the region and supplies a region address to the image memory address generation unit, an image memory arbitration unit that arbitrates the image memory bus of each image memory, and the main control unit The start command of the horizontal size counter and the vertical size counter are controlled by the start command of A sequence control unit that outputs an access request such as a read transfer cycle request and a write transfer request to a re-arbitration unit; 2. The image recognition device according to claim 1, further comprising an image memory control signal generation unit that inputs a control signal to an image memory corresponding to the access request. 16. The image recognition apparatus according to claim 1, wherein a timer is provided in the image memory control unit, and image processing is automatically performed at predetermined time intervals. 17. A horizontal coordinate setting section for setting a horizontal start address of at least one rectangular area, and a vertical coordinate setting section for setting a vertical start address (hereinafter referred to as vertical coordinate) of at least one rectangular area. And a horizontal size setting unit for setting a transfer size in the horizontal direction (hereinafter referred to as a horizontal size) and a vertical size setting unit for setting a transfer size in the vertical direction (hereinafter referred to as a vertical size). The image recognition device according to claim 15. 18. The horizontal size counter counts the processing clock. If the count of the horizontal counter matches a horizontal size set in a horizontal size setting unit of the area setting unit, the match signal is sent to the sequential counter. A horizontal size comparison unit input to the control unit, a horizontal auxiliary counter that starts the sequential clock unit and starts counting the processing clock by the same coincidence signal,
16. The image recognition device according to claim 15, wherein the image recognition device comprises a decoder that outputs a decode signal when a count output from the horizontal auxiliary counter reaches a predetermined constant value. 19. The vertical size counter sets a vertical coordinate set in a vertical coordinate setting section of the area setting section as an initial value, counts the number of decoding signals of a constant value input to the sequential control section, and sets a vertical address. And a coincidence signal is sent to the sequential control unit when the count number (vertical address-vertical coordinate) of the same vertical counter matches the vertical size set in the vertical size setting unit of the area setting unit. 16. An input vertical size comparing unit.
An image recognition device according to claim 1. 20. A vertical address selector for selecting a vertical address from each vertical counter of the vertical size counter or a vertical address from the main control unit, and each horizontal address of the area setting unit. A horizontal address selector for selecting a horizontal address from the coordinate setting unit or the main control unit, and a multiplexer for inputting the vertical address from the vertical address selector and the horizontal address from the horizontal address selector to the address bus of the image memory. The image recognition device according to claim 1, wherein: