JP2001268394A - Edge super processing apparatus and edge super processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow super processing by using super processors exclusive for videos in a 525 line system, for character video signals in a 1125 line system. SOLUTION: Super processing circuits 131-13m exclusive for videos in a 525 line system are arranged in parallel, and input memories 121-12m and output memories 141-14m are respectively arranged in the pre-and-post stages of each super processing circuit 131-13m. A memory controller 16 writes character video signals in a 1125 line system in the input memories 121-12m in each system only by the prescribed number of lines, and writes the character video signals in four more lines corresponding to edge width, and then reads them by a sampling frequency rate 13.5 MHz, and starts the write and read of the character video signals back in four lines for the input memory 122 in the next system in the write or read state of the character video signals for the input memory 121 in one system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to, for example, an HDTV.
(High Definition Television) 1125 of signal etc.
The present invention relates to an edge super processing apparatus and an edge super processing method for adding an edge signal around a line type character image.

[0002]

2. Description of the Related Art Conventionally, in a video editing system, a video synthesizing technique of extracting a character video signal such as a character or a person from a video signal and synthesizing this character video with another background image has been actively used. Have been. In this video synthesizing technique, a super processor has been proposed which adds an edge signal around a character video to be extracted so that the synthesized video does not become unnatural.

This super processor performs super processing for adding an edge to an NTSC character image. By the way, when digital broadcasting is started in the future, mixed broadcasting of high-definition television broadcasting of 1125 line system and television broadcasting of NTSC system of a plurality of channels becomes possible. There is a strong demand for the use of a super processor that can perform super processing even for character images.

[0004] However, a super processor dedicated to the 1125 line system has not yet been developed.
Even if an attempt is made to process a character video signal of the 1125 line system using a super processor dedicated to the C system,
The sampling frequency of the character video signal of the line system is 74.25 MHz, and the sampling frequency of the character video signal of the NTSC system is significantly different from 13.5 MHz.

[0005]

As described above, conventionally, there has been no effective means for performing super processing on a 1125-line character video signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an edge super processing apparatus and an edge super processing method capable of effectively performing super processing on a 1125 line type character video signal using a super processor dedicated to 525 line type video. Is to do.

[0007]

An edge super-processing apparatus according to the present invention distributes a 1125-line character video signal to a plurality of systems in an edge super-processing apparatus for adding an edge signal around a 1125-line character video. An input signal distributor, an input memory provided for each system and storing and outputting a distributed character video signal, and a super process provided for each system and adding an edge signal to the output of the input memory. Apply 525
A super processor for line system video, an output memory provided for each system, for storing and outputting the output of the super processor, and an output switcher for selectively deriving each output of the output memory for a plurality of systems. Writes a predetermined number of character signals to the input memory, writes a few extra lines corresponding to the edge width to be added to the character image, and then reads out at the sampling frequency rate for 525-line video. After writing the output of the super processor for a predetermined number of lines to the output memory and writing a few extra lines corresponding to the edge width,
A memory switching controller is provided which controls so as to read out at a sampling frequency rate for 1125 line system video and switches the output switching unit at a predetermined number of cycles of lines to be written to the input memory or the output memory. Things.

In particular, the memory switching controller accesses the next-system input memory in a state where the character video signal is written or read to one input memory, and writes or reads the character video signal to the edge width. Control is performed so as to start from the corresponding several lines before, and in the state where the output of the super processor to the output memory of one system is written or read, the input memory of the next system is accessed, and the super processing of the next system is performed. It is characterized in that the writing or reading of the output of the device is controlled to start several lines before the edge width.

The input memory, the super processor dedicated to the 525-line video, and the output memory have a sampling frequency of 1125-line video signal M, and 52
Assuming that the allowable operating frequency of the super processor dedicated to 5-line video is N, M / N units are arranged in parallel.

That is, according to the present invention, at least M / N super processors dedicated to 525-line video are arranged in parallel, and an input memory and an output memory are provided before and after each super processor. It is intended to realize a high-speed super processor capable of supporting line-type video processing. In addition, the character image signals of the 1125 line system distributed to a plurality of systems are written into the input memory by a predetermined number of lines in each system, and the edge width is increased in order to increase the edge width so as to be added to the character image. 525 after writing corresponding extra lines
At the sampling frequency rate for line-type video, the character video signal is written to or read from one input memory, and the character video signal is read from the next input memory several lines before the edge width corresponding to the edge width. The writing or reading is started. In each system, the output of the super processor is written into the output memory by a predetermined number of lines, and a few extra lines corresponding to the edge width are written, and then read at a sampling frequency rate for 1125-line video, and In a state where the output of the super processor is written to or read from one output memory, writing or reading of the output of the super processor to the next output memory is started several lines before the line corresponding to the edge width. It was made.

Therefore, according to the present invention, the character signal is converted into the 525 line system using the input memory,
Since the super processing output is converted to the 1125 line system using the output memory, it is possible to configure a high speed super processor capable of supporting the 1125 line system video processing while minimizing the complexity of the apparatus configuration and increasing the cost. In addition, for each input memory and output memory in each system,
A character video signal is written by an extra number corresponding to the edge width from a predetermined number of lines, and the character video signal is read from the input memory and the output memory at a frequency rate corresponding to the output side by the number of lines corresponding to the edge width. Output, and is selectively derived in a predetermined number of lines by the output switch, so that each super-processor can smoothly generate a character image to which an edge is added without interruption or disturbance. .

Further, the present invention provides an edge super processing method for adding an edge signal around a 1125-line character image, distributing the 1125-line character image signal to a plurality of systems, and converting the character image signal in each system. A predetermined number of lines are written to the input memory, and a few extra lines corresponding to the edge width are written to be added to the character video, and then read at a sampling frequency rate for a 525-line system video. Is superposed to add an edge signal to the output memory, and this super processed output is written to the output memory for a predetermined number of lines, and a few extra lines corresponding to the edge width are written. Then, at a sampling frequency rate for 1125-line video, Read and output memory for multiple systems Characterized by selectively switching derived in a predetermined number of lines cycle to be written into the input memory or output memory outputs.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an edge super-processing apparatus according to the present invention. In this edge super processing apparatus, a character video signal of the 1125 line system is input and distributed to m systems by a signal distribution circuit 11, and input memories 121 to 1 comprising a FIFO (first in first out) memory.
A predetermined number of lines are written in 2m. Each output of these input memories 121 to 12m is subjected to super processing such as adding an edge around the character video by super processing circuits 131 to 13m dedicated to 525-line video,
A predetermined number of lines are written into each of the output memories 141 to 14m. Each output of these output memories 141 to 14m is selectively derived by the selection circuit 15 and 1125.
It is output as a line-type character video signal. The input memories 121 to 12m, the super processing circuit 131
To 13 m, output memories 141 to 14 m, and selection circuit 1
5 are respectively controlled by the memory controller 16.

The memory controller 16 writes 1125 line type character video signals distributed by the signal distribution circuit 11 to the input memories 121 to 12m for a predetermined number of lines based on the input video synchronizing signal. After writing a few extra lines corresponding to the edge width in order to add to the above, memory control is performed so that reading is performed at a sampling frequency rate of 13.5 MHz in the NTSC system. Then, each of the super processing circuits 131 to 13
The output of m is written to the output memories 141 to 14m by a predetermined number of lines, and a few extra lines corresponding to the edge width are written, and then the memory is controlled so as to be read at a sampling frequency rate of 74.25 MHz of the 1125 line system. Thereafter, the selection circuit 15 is switched and controlled at a predetermined line number cycle.

Next, the processing operation of the above configuration will be described.

First, in the above configuration, super-processing circuits 131 to 13m dedicated to 525-line video are arranged in parallel, and input memories 121 to 12m and output memories 141 are provided before and after each of the super-processing circuits 131 to 13m. ~ 14
By providing m, a high-speed superprocessor capable of supporting 1125-line video processing is realized.

However, if the super-processing circuits 131 to 13m dedicated to the 525-line system video are simply arranged in parallel, the super-processing circuits 131 to 13m are super-processed, and the character video signals selected and derived by the selection circuit 15 are interrupted. In some cases, the character image may be discontinuous and uncomfortable. That is, the conventional super-processing circuit cannot generate a character image with continuity unless there is continuous pixel data in the horizontal and vertical directions.

Therefore, in the present invention, the character video signal is input to the input memories 121 to 12m and the output memories 141 to 14m so that the character video signal derived from the selection circuit 15 is not interrupted or disturbed. Is written more than the predetermined number of lines by the number of lines corresponding to the edge width. FIGS. 2A and 2B show the state of the memory control process in this case. Note that reference numeral 1
To m indicate memory write areas of the input memories 121 to 12m, respectively.

First, the memory controller 16 writes a predetermined number of lines of a character image signal (indicated by T in FIG. 2B) into the input memory 121 and increases the edge width so as to be added to the character image. Then, control is performed so as to write a few extra lines (the margin portion in FIG. 2A). Here, since the edge width corresponds to four lines, a character video signal is written in an extra four lines. Further, the memory controller 16 controls the memory switching so that the writing of the character video signal to the input system 122, which is the next system, starts four lines before in the writing state of the character video signal to the input memory 121. Hereinafter, similarly, the input memory 1
The memory switching control is executed up to 2 m.

The memory controller 16 controls the memory switching so that the reading of the character video signal from the input memory 122 of the next system is started four lines before when the character video signal is read from the input memory 121. Do. Hereinafter, similarly, the input memory 12
The memory switching control is executed up to m.

Further, the memory controller 16 starts writing the output of the super processing circuit 132 to the output memory 142 of the next system four lines before in the state of writing the output of the super processing circuit 131 to the output memory 141. Also, in a state where the character video signal with the edge added to the output memory 141 is read, the reading of the character video signal with the edge added to the output memory 142 of the next system is started four lines before. To control.

By switching the selection circuit 15 every predetermined number of lines, the character video signal of the 1125-line system derived from the selection circuit 15 can be obtained as shown in FIG.
As shown in (b), the input memories 121 to 12m and the output memories 141 to 14m are connected beautifully at the switching boundary (the marginal portion in the figure), and the information is not disturbed.

The input memories 121 to 12m, the super processing circuits 131 to 13m, and the output memories 141 to 1
4 m is 74.25 MHz / 20 MH, assuming that the allowable operating frequency of the super processing circuits 131 to 13 m is 20 MHz.
Four are arranged in parallel with z.

As described above, in the above embodiment, 52
Super processing circuits 131 to 13m dedicated to 5-line video
Are arranged in parallel, and each of the super processing circuits 131 to 13m
By providing input memories 121 to 12m and output memories 141 to 14m before and after, a high-speed edge super processing apparatus capable of supporting 1125-line video processing can be realized without increasing the processing speed. In addition, the memory controller 16 has a
A 125-line character video signal is written by a predetermined number of lines into the input memories 121 to 12m in each system, and four extra lines corresponding to the edge width are added to increase the edge width so as to be added to the character video. After writing to, the sampling frequency rate 13.5M
Hz, and in a state where the character video signal is written to or read from the input memory 121 of one system, the control is performed so that the writing or reading of the character video signal is started four lines before from the input memory 122 of the next system. I do.

The memory controller 16 writes the outputs of the super-processing circuits 131 to 13m into the output memories 141 to 14m by a predetermined number of lines in each system, and writes four extra lines in the output memories 141 to 14m. In the state of reading at 74.25 MHz and writing or reading the output of the super processing circuit 131 to or from the output memory 141 of one system, writing or reading of the output of the super processing circuit 132 to the output memory 142 of the next system is performed in four lines. Control is performed to start from the front.

Therefore, the character video signal is converted into the 525 line system by using the input memories 121 to 12m.
Super processing circuit 1 using output memories 141 to 14m
By converting each output from 31 m to 13 m into a 1125 line system, it is possible to configure a high-speed super processor capable of supporting 1125 line system video processing while minimizing the complexity of the apparatus configuration and increasing the cost.

Further, in the above embodiment, the character video signals are supplied to the input memories 121 to 12m by the respective systems.
In addition, a few extra lines corresponding to the edge width are written in the output memories 141 to 14m more than the predetermined number of lines, and extra lines are read from the input memories 121 to 12m and the output memories 141 to 14m by the number of lines corresponding to the edge width, and Since the selection circuit 15 selectively derives the character image every predetermined number of periods, the superimposing circuits 131 to 13m can provide continuity between the systems to the character image to which the edge is added. This makes it possible to obtain a smooth character image that does not cause a problem.

In the present invention, the number of input memories, super-processing circuits and output memories can be arbitrarily determined according to the character image to be super-processed. Further, the number of lines of the character video signal to be written to the input memory and the number of lines of the character video signal to be written to the output memory can be arbitrarily determined according to the character video to be super-processed. By increasing the number of input memories, super-processing circuits, and output memories, it is possible to realize a higher-speed edge super-processing apparatus compatible with the 1125-line system.

[0030]

As described in detail above, according to the present invention,
525 for 1125 line character video signal
It is possible to provide an edge super processing apparatus and an edge super processing method capable of performing super processing effectively using a super processor dedicated to line type video.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an edge super processing apparatus according to an embodiment of the present invention.

FIG. 2 is a view for explaining a processing operation in the embodiment.

[Explanation of symbols]

 11: signal distribution circuit, 121 to 12m: input memory, 131 to 13m: super processing circuit, 141 to 14m: output memory, 15: selection circuit, 16: memory controller.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masafumi Shiratori 1F, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term (reference) 5C021 PA66 PA79 PA82 XB03 YC04 YC11 5C023 AA07 AA11 AA23 BA13 CA03 CA05 DA04 EA03

Claims (7)

[Claims] 1. An edge super-processing apparatus for adding an edge signal around a 1125-line character image, comprising: an input signal distributor for distributing the 1125-line character video signal to a plurality of systems; An input memory for storing and outputting a distributed character video signal; and a super-processing for a 525-line video, which is provided for each system and performs super-processing for adding the edge signal to the output of the input memory. An output memory that is provided for each system and stores and outputs the output of the super processor; an output switch that selectively derives each output of the plurality of systems of output memories; A predetermined number of lines of the character video signal are written to the memory, and several lines corresponding to the edge width are added to the character video. After writing extra,
After performing control so as to read at a sampling frequency rate for 525-line video, writing the output of the super processor for the predetermined number of lines to the output memory and writing a few extra lines corresponding to the edge width, A memory switching controller for controlling to read at a sampling frequency rate for 1125 line system video and switching the output switch at a predetermined number of line cycles to be written to the input memory or the output memory. An edge super-processing apparatus characterized by comprising: 2. The memory switching controller according to claim 1, wherein the character video signal is written to or read from one input memory, and the next input memory is written to the input memory.
2. The edge super processing apparatus according to claim 1, wherein control is performed such that writing or reading of a character signal is started several lines before the edge width. 3. The memory switching controller according to claim 1, wherein the output of the super processor is written to or read from the output memory of one system, and the input memory of the next system is written to the output memory.
2. The edge super processing apparatus according to claim 1, wherein control is performed such that writing or reading of the output of the super processor of the next system is started several lines before the edge width. 4. The super processor for exclusive use of the 525-line video, wherein the input memory, the super processor dedicated to the 525-line video, and the output memory have a sampling frequency M of the 1125-line video, and 2. The edge super processing apparatus according to claim 1, wherein M / N units are arranged in parallel, where N is an allowable operating frequency of the edge super processing units. 5. An edge superimposing method for adding an edge signal around a 1125-line character image, wherein the 1125-line character image signal is distributed to a plurality of systems, and the character image signal is input to a memory for each system. And a few lines corresponding to the edge width to be added to the character image, and then read at a sampling frequency rate for a 525-line system image. A super processing for adding a signal is performed, and this super processing output is written to the output memory for a predetermined number of lines, and a few extra lines corresponding to the edge width are written, and then read at a sampling frequency rate for 1125-line video, Each output of multiple output memory Ejjisupa processing method characterized by selectively switching derived in a predetermined number of lines period to be written to memory or output memory fill-force. 6. In a state where the character signal is written to or read from one input memory, writing or reading of a character signal to the next input memory is started several lines before the edge width. The edge super processing method according to claim 5, wherein 7. The writing or reading of the output of the super processor to or from the output memory of one system, and the writing or reading of the output of the super processor of the next system to the output memory of the next system is performed to the edge width. 6. The edge super-processing method according to claim 5, wherein the processing is started several lines before.