JPH11145977A - Atm shaping memory search processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve transmission quality by enabling shaping processing of minimum delay time by a cell unit for each connection information number without complicating the contention control at the time of mapping. SOLUTION: One transmission band is shared by cells having connection information for plural logical path identifiers and logical channel identifiers and shaping processing for traffic control in the transmission band is performed. In the case that the storage addresses of a buffer 1 for the shaping processing between the different connection information at the ideal prescribed transmission time compete, the time closest to the prescribed transmission time of the cell is searched. In this case, the search for a free area before/after the logical transmission time is performed through a scheduling processing part 2, a front part search part 4a, a rear part search part 4b and a mapping processing part 3 and the mapping processing of an input cell to the buffer for the shaping processing is performed based on the result of the free area by the search.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM shaping memory search processing apparatus for performing cell flow control on ATM traffic in an ATM (Asynchronous Transfer Mode) network, and more particularly to a user terminal transmitting end and an AT.
The present invention relates to a shaping memory search processing device for performing a shaping process in an M network transmitting / receiving end, a traffic control node in an ATM network, or the like.

[0002]

2. Description of the Related Art Conventionally, in an ATM (Asynchronous Transfer Mode) network, cells (48
(Byte: information field 5 bytes: header field) is transmitted in proportion to the bit rate of each channel. For this reason, cells are stored in a cell delay buffer or the like and waited, and the time axis is adjusted and transferred. In order to improve the non-uniformity of cells in such ATM traffic, contention control is performed when the logical transmission times of cells conflict.

For example, in Japanese Patent Application Laid-Open No. Hei 6-315034, "Cell Flow Control Device and ATM Communication Network", after policing, a cell delay fluctuation (CVD: Cell Delay Fluctuation) generated between a communication terminal and an ATM network. The cell flow whose time axis is displaced by Variation) is formed into the original cell flow. Therefore, the transmission time of the cell is calculated, the cell is stored, and the stored cell is read out to the transmission line. As a result, the allocated transmission bandwidth is reduced,
In addition, the number of passing node stages can be increased, and the degree of freedom of the network configuration is obtained.

[0004] Japanese Patent Application Laid-Open No. 6-276209 "ATM"
In the example of the gazette of "Traffic shaping device in network", in order to improve shaping efficiency, input cells are temporarily stored in a cell memory until transmission is possible, and input cells are logical path identifiers (VPI: Virtual Path Identifie).
r) and a logical channel identifier (VPI: Virtual Channel Iden)
tifier), the time at which the cell is output is determined from the current time defined by the characteristics and the history set corresponding to the history. Cell read information for reading the cell corresponding to the determination time is written to the read control memory.
Then, a cell readable at the current time is detected from the read control memory, and the detected cell is read from the cell memory and transmitted.

[0005] In the conventional example of this publication, contention control is performed when the logical transmission times of cells conflict. That is, a FIFO memory for this contention control is used, the logical transmission time of the arriving cell is determined, and the cells are stored in the FIFO memory in this arrival order. Therefore, in the cell transmission process, the FIFO
When the output of the O memory is in a conflict state, the transmission time of a cell having a low priority is delayed according to the priority.

In such a shaping process, generally, a process of delaying the transmission time of a received cell in any case by memory contention control is performed. Therefore, when a large number of cells having burstiness that the network administrator judges to be acceptable are transmitted intensively among the cells sharing the same transmission band, the cell interval originally given by the shaping parameter is guaranteed. become unable. That is, as the accuracy of the cell interval decreases and the number of cells to be processed increases, the race condition easily occurs.

[0007] Therefore, in the entire shaping processing capability, the degree to which the output is delayed with respect to the predetermined logical transmission time becomes greater, and as a result, it is difficult to guarantee the contract transmission band in the operation of the ATM network. . Such a shaping processing device is connected to a cell transmission path, for example, a UNI (User Network Interface) between networks.
And multi-stage connection by mounting each connection device in the network or NNI (Netwark Node Interface), the transmission quality (delay quality) is deteriorated.

[0008]

As described above, in the above-mentioned conventional example, there is a problem that it is difficult to guarantee a contracted transmission band in the operation of the ATM network. Connection device (UN
I, NNI), and connected in multiple stages, there is a drawback that a predetermined delay quality cannot be obtained and the transmission quality is reduced.

SUMMARY OF THE INVENTION The present invention solves such a problem in the prior art. When the non-uniformity of cell traffic is improved by buffer management in an ATM switch, mapping to a delay buffer for cell shaping processing is performed. Even in the case of multi-stage connection arranged for each connection device of the cell transmission path without complicating the contention control at the time, the shaping process with the shortest delay time in the cell unit for each connection information number becomes possible. An object of the present invention is to provide a shaping memory search processing device in which transmission quality (delay quality) is improved.

[0010]

In order to achieve the above object, according to the present invention, one transmission band is shared by cells having connection information of a plurality of logical path identifiers and logical channel identifiers. In an ATM shaping memory search processing device that performs a shaping process for traffic control in a transmission band, an input cell is output with a delay for a fixed time, a shaping process buffer that performs a shaping process, and an ideal predetermined inter-connection information between different connection information. When the storage address of the shaping processing buffer conflicts with the transmission time, the time closest to the predetermined transmission time of the cell is searched, and when an empty area is detected in this search, the cell corresponding to the detected storage address is searched. And a search unit for performing the mapping of.

According to a second aspect of the present invention, there is provided an ATM shaping memory search processing device, wherein the search means calculates a required delay amount by calculating an interval between an input cell and a previous cell, and a scheduling processing unit. , The empty state of the storage address of the input cell is detected based on the scheduling result, and when the detected address conflicts with the completion of the mapping processing by another cell, the empty state before / after the predetermined transmission time is generated. The configuration includes a forward / backward search unit for searching for an area, and a mapping processing unit for mapping input cells to a shaping processing buffer based on determination of a free area in the forward / backward search unit.

According to a third aspect of the present invention, in the ATM shaping memory search processing device, the forward / backward search unit is prior to a logical transmission time of an input cell and closest to a logical transmission time of an input cell when a conflict occurs. It is configured to search for a free area at a free time.

According to a fourth aspect of the present invention, there is provided an ATM shaping memory search processing device which searches for an empty area before the transmission time and at an empty time closest to the logical transmission time of the input cell by one from the logical transmission time. It is configured to repeatedly search for an empty area for each time before the cell.

According to a fifth aspect of the present invention, in the ATM shaping memory search processing device, the forward / backward search unit may determine that when a conflict occurs, the forward / backward search unit most often searches after the input cell logical transmission time and at the input cell logical transmission time. It is configured to search for a free area at a near free time.

According to a sixth aspect of the present invention, in the ATM shaping memory search processing device, the search for the free area at the free time after the sending time and closest to the logical sending time of the input cell is performed one time from the logical sending time. It is configured to repeatedly search for a free area at each time after each cell.

According to a seventh aspect of the present invention, in the ATM shaping memory search processing device, when the forward search unit searches for a vacant time area before a logical transmission time of an input cell when a conflict occurs, the same connection information is used. The search is performed within an interval that does not come before the time at which the shaping interval is guaranteed from the logical transmission time of the cell preceding the number.

The ATM shaping memory search processing device according to claim 8, wherein the scheduling processing unit includes a header identification unit for identifying a header of an input cell, and a shaping parameter / operation result storage for storing a shaping parameter and an operation result. , A time management unit that manages time, and a scheduling operation unit that performs scheduling operation.

According to a ninth aspect of the present invention, in the ATM shaping memory search processing device, the forward / backward search section manages address information indicating a storage area in a shaping processing buffer corresponding to a logical transmission time of an input cell. The forward / backward search address use state management unit and the forward / backward search address use state management unit determine the free area near the logical transmission time based on the search result of the free area.
And a rear empty address determination unit.

According to a tenth aspect of the present invention, there is provided an ATM shaping memory search processing device, comprising the steps of:
It is configured to be provided at a user communication terminal transmitting end in a network.

[0020] An ATM shaping memory search processing device according to an eleventh aspect of the present invention provides an ATM shaping memory search processing device, which
The configuration is provided at the network transmitting / receiving end.

According to a twelfth aspect of the present invention, there is provided an ATM shaping memory search processing device comprising the steps of:
The configuration is provided in a traffic control node in the network.

In the ATM shaping memory search processing device having such a configuration, one transmission band is shared by cells having connection information of a plurality of logical path identifiers and logical channel identifiers, and shaping for traffic control in this transmission band is performed. Perform processing. In this case, when the storage addresses of the shaping processing buffer at different ideal connection times between the connection information conflict with each other, a time closest to the predetermined transmission time of the cell is searched, and an empty area is detected by this search. At this time, the corresponding cell is mapped to the detected storage address.

When the above-mentioned conflict occurs, an empty area before / after the logical transmission time is searched, and based on the determination of the empty area, the input cell is mapped to the shaping processing buffer. Further, in the search for the empty area before / after the transmission time, the empty area is repeatedly searched for the time before and after the logical transmission time, one cell at a time.

In this search, when contention occurs, when a search is made for a free time area before the logical transmission time of the input cell, the shaping interval is determined from the logical transmission time of the previous cell having the same connection information number. The search is being performed within an interval that is not before the guaranteed time.

As a result, when the non-uniformity of the cell traffic is improved by the buffer management in the ATM switch, the contention control at the time of mapping to the delay buffer for the cell shaping process does not become complicated. Therefore,
Even in the case of multi-stage connection in which a shaping processing device is arranged for each connection device of a cell transmission path, a shaping process with the shortest delay time can be performed in a cell unit for each connection information number, and a predetermined delay quality can be obtained. And its transmission quality is improved.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an ATM shaping memory search processing device of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an ATM shaping memory search processing device according to the present invention. In this example, an input cell is output after being delayed for a fixed time, a shaping process buffer 1 for performing a shaping process, and a scheduling process for calculating an interval between an input cell and a previous cell to determine a necessary delay amount. Part 2.

Further, the ATM shaping memory search processing device detects an empty state of the storage address of the input cell based on the scheduling result in the scheduling processing unit 2, and determines whether the detected address is another cell. When the mapping process ends and a conflict occurs, a forward search unit 4a and a backward search unit 4b that search for an empty area before and after the logical transmission time are provided.
A mapping processing unit that determines a free area close to a logical transmission time based on the search result of the free area by the forward search unit 4a and the backward search unit 4b, and performs a mapping process of the input cell to the shaping process buffer 1. Three.

The shaping processing buffer 1 performs random writing and sequential reading of input cells by using a write address and a read address from the mapping processing unit 3. The scheduling processing unit 2
In order to transmit an input cell at an ideal predetermined cell interval, a time interval with a previous cell of the same connection information number is determined by performing a shaping algorithm operation to determine a necessary delay amount, and an input indicating a predetermined transmission time. The storage address of the cell is output, and the input cells of the plurality of connection information are independently calculated.

The mapping processing unit 3 determines the cell transmission time close to the logical transmission time, which is the search result of the empty area by the forward search unit 4a and the backward search unit 4b.
It outputs the write address information of the input cell to the shaping processing buffer 1 and executes the mapping processing for the input cell.

The forward search section 4a and the backward search section 4b detect an empty state of an address corresponding to the storage address information of the input cell from the scheduling processing section 2, and the detected address is mapped to another cell. Is over,
When a conflict occurs, a search for a free area before / after the logical transmission time is executed. That is, the storage location of the input cell in the shaping processing buffer 1 is determined, and the input cell is stored at the address of a free area indicating the corresponding free area for each connection information number (VPI, VCI) unit.

FIG. 2 is a block diagram showing an arrangement state of the ATM shaping memory search processing device shown in FIG. 1 in an ATM network. In this example, an input of an ATM device, that is, an ATM unit, is used to absorb cell delay fluctuation (CVD) between a plurality of ATM networks (ATM subscriber networks 5, ATM relay networks 6, 7).
ATM shaping memory search processors 8 and 9 are provided in a UNI (User Network Interface) between the subscriber networks 5 and the ATM relay network 6 and in a NNI (Netwark Node Interface) between the ATM relay networks 6 and 7, respectively.

FIG. 3 is a block diagram showing another arrangement state of the ATM shaping memory search processing device shown in FIG. 1 in the network. This example illustrates the output of an ATM device, ie, the ATM subscriber network 5, to absorb cell delay fluctuations (CVD) between a plurality of ATM networks (ATM subscriber networks 5, ATM transit networks 6, 7). ATM shaping memory search processors 10 and 11 are provided at the UNI between the ATM relay networks 6 and 7 and at the NNI between the relay networks.

FIG. 4 is a block diagram showing a configuration of a device in which the ATM shaping memory search processing device shown in FIG. 1 is arranged. In this example, cell delay buffers 13, 14 to which cells from a cell interface (I / F) circuit are input are provided.
.. 1n. Further, the cell delay buffers 13... 1
multiplexed by a multiplexer (MUX) 16 from
At the subsequent stage, the ATM shaping memory search processor 17
Is arranged.

FIG. 5 is a block diagram showing another device configuration in which the ATM shaping memory search processing device shown in FIG. 1 is arranged. In this example, a cell delay buffer 20 or 2 receives a cell from an input port of an ATM switch (SW).
An ATM shaping memory search processing device 30 is provided on the output side of 1,..., 1n, and an ATM switch (SW) 31 is provided as a subsequent stage.

FIG. 6 is a block diagram showing still another device configuration in which the ATM shaping memory search processing device shown in FIG. 1 is arranged. In this example, the cell is an ATM switch (S
.. 3n through W) 32. Also, the output of the ATM shaping memory search processing device 40 provided on the output side, ie, A
A cell is transmitted from an output port as a TM switch (SW).

FIG. 7 is a block diagram showing the internal configuration of the scheduling processing section 2 in FIG. The scheduling processing unit 2 includes a header identification unit 2a for identifying a header of an input cell, and a shaping parameter / operation result storage unit 2b for storing a shaping parameter and an operation result.
A time management unit 2c for managing time,
A scheduling operation unit 2d for performing a scheduling operation.

FIG. 8 is a block diagram showing the internal configuration of the mapping processing section 3 in FIG. This mapping processing unit 3
Selects a determination result of a free area closer to a logical transmission time based on a determination result of a free area in the forward search unit 4a and the backward search unit 4b, and performs a shaping process based on the determination result of the free area. It has an address determination unit 3a that performs a mapping process of an input cell to the use buffer 1.

FIG. 9 is a block diagram showing the internal configuration of the forward search section 4a and the backward search section 4b in FIG. The forward search unit 4a detects an empty state of the storage address of the input cell based on the scheduling result in the scheduling processing unit 2, and when a conflict occurs that the detected address ends the mapping process by another cell. , An address decoder 41a for searching for a free area before the logical transmission time and a forward search address use state management unit 41b. Further, the forward search address use state management unit 41
forward free address determination unit 41 that determines a free area near the logical transmission time based on the search result of the free area in b.
c.

The backward search unit 4b detects an empty state of the storage address of the input cell based on the scheduling result in the scheduling processing unit 2 in the same manner as the forward search unit 4a. It has an address decoder 42a and a backward search address use state management unit 42b for searching for a free area after the logical transmission time when a conflict occurs in which mapping processing is completed by a cell. Further, it has a rear free address determination unit 42c that determines a free area near the logical transmission time based on the search result of the free area in the backward search address use state management unit 42b.

Next, the operation of this embodiment will be described. In FIG. 1, a cell flow having a traffic characteristic with a high burst property within the same transmission band is input to a shaping processing buffer 1 and a scheduling processing unit 2. In the scheduling processing unit 2, the header identification unit 2a shown in FIG. 7 extracts the connection information number (VPI, VPI) in the corresponding cell from the header field of the input cell.

Further, the scheduling processing unit 2 transmits the arrival time of the input cell and the transmission time information of the same connection information number previously input, and the transmission cell information set in advance for the connection information number. The theoretical transmission time of the input cell based on the interval information (external setting parameter) is calculated by using the shaping parameter /
The calculation result storage unit 2b, the time management unit 2c, and the scheduling calculation unit 2d perform the shaping algorithm calculation. The theoretical transmission time of the input cell determined by this operation is transmitted to the forward search unit 4a and the backward search unit 4b.

The forward search section 4a manages address information indicating the storage area of the shaping processing buffer 1 corresponding to the theoretical transmission time of an input cell from the scheduling processing section 2. That is, the address decoder 41a and the forward search address use state management unit 41 shown in FIGS.
b detects an empty state of the storage address of the input cell based on the scheduling result in the scheduling processing unit 2. Then, when a conflict occurs in which the detected address is mapped by another cell, a search for a free area before the logical transmission time is performed.

The forward free address determining section 41c determines a free area close to the logical transmission time on the basis of the search result of the free area by the forward search address use state managing section 41b. 3
Note that the forward empty address determination unit 41c, when searching for an empty time area before the logical transmission time of the input cell when a conflict occurs, sets the time earlier than the logical transmission time of the previous cell of the same connection information number. Is determined when there is no address corresponding to. In other words, when a conflict occurs, when searching for an area having a free time before the logical transmission time of the input cell, the logical transmission time of the previous cell having the same connection information number does not fall before the time at which the shaping interval is guaranteed. The search is performed within the interval.

The backward search section 4b manages address information corresponding to the storage area of the shaping processing buffer 1 corresponding to the theoretical transmission time of the input cell from the scheduling processing section 2. That is, the address decoder 42a and the backward search address use state management unit 42b shown in FIGS. 1 and 9 detect an empty state of the storage address of the input cell based on the scheduling result in the scheduling processing unit 2, and When a conflict occurs in which the detected address is mapped by another cell, a search for a free area after the logical transmission time is performed. Further, the rear empty address determination unit 42c is a rear search address use state management unit 4
Based on the search result of the free area in 2b, a free area close to the logical transmission time is determined, and this determination result is transmitted to the mapping processing unit 3.

The address judging section 3a of the mapping processing section 3 shown in FIGS. 1 and 8 determines an empty area closer to the logical transmission time based on the search results of the forward search section 4a and the backward search section 4b. The determination result is selected, and the input cell is mapped to the shaping processing buffer 1 based on the determination result of the empty area.

As a result, when the non-uniformity of the cell traffic is improved by the buffer management in the ATM switch or the like, the competition control at the time of mapping to the shaping processing buffer 1 is not complicated. In other words, even in the case of multi-stage connection in which the shaping process is set for each connection device of the cell transmission path, the shaping process with the shortest delay time can be performed in the cell unit for each connection information number, and a highly accurate delay quality can be obtained. And the transmission quality is improved.

Next, the main part of this embodiment will be described in detail. As described above, when a cell flow having a traffic characteristic with a high burst property in the same transmission band is input to the shaping processing buffer 1 and the scheduling processing unit 2, the header identification unit 2a shown in FIG. , The connection information number (VPI, VPI) in the corresponding cell is extracted from the header field.

The shaping processing buffer 1 performs random writing and sequential reading of input cells by using a write address and a read address from the mapping processing unit 3. The scheduling processing unit 2
In order to transmit an input cell at an ideal predetermined interval, a time interval between the input cell and the previous cell having the same connection information number is subjected to a shaping algorithm operation to determine a necessary delay amount. In addition, a storage address of an input cell indicating an ideal predetermined transmission time is output, and input cells having a plurality of connection information numbers are individually calculated.

The forward search unit 4a and the backward search unit 4b detect the free state of the corresponding address based on the storage address information of the input cell from the scheduling processing unit 2,
Alternatively, when the mapping process ends in another cell at the corresponding address and a conflict occurs, a search for a free area before / after the logical transmission time is executed. That is, the storage location of the input cell in the shaping processing buffer 1 is determined, and the input cell is stored in a free area address indicating the corresponding free area for each connection information number (VPI, VCI) unit.

FIG. 10 is a diagram showing the contents of the cell empty area management table. The forward search unit 4a and the backward search unit 4b
The state of vacancy or the presence / absence of mapping processing (vacant area) is managed for each connection information number unit.
That is, as shown in FIG. 10, the forward search unit 4a and the backward search unit 4b execute n + 1 address transmission time management.

FIGS. 11 and 12 are diagrams for explaining a forward search process and a backward search process of a free area for an input cell, respectively. The forward search unit 4a performs a forward search process of an empty area for the input cell as shown in FIG.
In addition, the backward search unit 4b executes a backward search process for a free area as shown in FIG. The search results of the free area in the forward search unit 4a and the backward search unit 4b are input to the mapping processing unit 3.

FIG. 13 shows a forward search section 4a and a backward search section 4.
FIG. 14 is a diagram for explaining another operation example in b. The forward search unit 4a, when the storage addresses of the shaping processing buffer 1 conflict with different connection information and at an ideal predetermined transmission time, before the logical transmission time of the input cell and the logical A search is made for a free area having a free time closest to the transmission time. This search repeatedly searches for a free area one cell before the logical transmission time. That is, an area one cell time before the logical transmission time is searched, and if this area is empty, it is stored in the area one cell before. If a conflict occurs even in the area one cell before, it is further stored in the area one time before the next cell.
In this way, the empty area before the time is repeatedly searched one cell at a time.

Similarly to the forward search unit 4a, the backward search unit 4b, when the storage addresses of the shaping processing buffers conflict, after the logical transmission time of the input cell and
A search is made for a free area at the free time closest to the logical transmission time of the input cell. This search is performed one time from the logical transmission time.
The area after the cell time is searched, and if this area is empty, it is stored in the area one cell later. If a conflict occurs in the area one cell later, the data is further stored in the area one cell later. As described above, the empty area after the time of one cell is repeatedly searched.

FIG. 14 is a flowchart showing a processing procedure of the mapping judgment in the mapping processing section 3, and FIG.
FIG. 3 is a diagram for explaining a result of mapping an input cell in a mapping processing unit 3; FIG.
As shown in FIG. 4, the search results are input to the forward search result B and the backward search result A from the forward search unit 4a and the backward search unit 4b (step S1). Next, the difference between the backward search result A and the logical sending time C and the difference between the logical sending time C and the forward search result B are compared by “AC ≧ CB” (step S).
2).

Next, the backward search result A and the logical sending time C
If the difference "AC" is large, the forward search result B from the forward search unit 4a is determined to be an ideal predetermined transmission time (step S3). If the difference “AC” between the backward search result A and the logical sending time C is smaller than the difference “CB” between the logical sending time C and the forward search result B, the signal from the backward search unit 4b is output. The backward search result A is determined to be an ideal predetermined transmission time (step S4). Based on the determination result of the cell transmission time close to the logical transmission time of the free area search result, as shown in FIG. 15, the write address information of the input cell to the shaping processing buffer 1 is output to Execute the mapping process.

[0056]

As is apparent from the above description, according to the ATM shaping memory search processing apparatus of the present invention, the storage addresses of the shaping processing buffer at different ideal connection times and at different predetermined connection information conflict. At this time, a time closest to a predetermined transmission time of the cell is searched, and when an empty area is detected in the search, the corresponding cell is mapped to the detected storage address.

As a result, when the non-uniformity of the cell traffic is improved by the buffer management for each ATM switch, the competition control at the time of mapping to the delay buffer for the cell shaping process does not become complicated. In other words, even in the case of multi-stage connection in which a shaping processing device is arranged for each connection device of a cell transmission line, the shaping process with the shortest delay time can be performed in a cell unit for each connection information number, and a highly accurate delay quality can be obtained. And the transmission quality is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an ATM shaping memory search processing device according to the present invention.

FIG. 2 is a block diagram showing an arrangement state of an ATM shaping memory search processing device in an ATM network according to the embodiment;

FIG. 3 is a block diagram showing another arrangement state of the ATM shaping memory search processing device in the network according to the embodiment.

FIG. 4 is a block diagram showing a configuration of an apparatus in which an ATM shaping memory search processing device is arranged in the embodiment.

FIG. 5 is a block diagram showing another device configuration in which the ATM shaping memory search processing device is arranged in the embodiment.

FIG. 6 is a block diagram showing still another device configuration in which an ATM shaping memory search processing device is arranged in the embodiment.

FIG. 7 is a block diagram illustrating an internal configuration of a scheduling processing unit in FIG. 1;

FIG. 8 is a block diagram illustrating an internal configuration of a mapping processing unit in FIG. 1;

FIG. 9 is a block diagram illustrating an internal configuration of a forward search unit and a backward search unit in FIG. 1;

FIG. 10 is a diagram showing contents of a cell empty area management table in the embodiment.

FIG. 11 is a diagram illustrating a forward search process according to the embodiment.

FIG. 12 is a diagram illustrating a backward search process according to the embodiment.

FIG. 13 is a diagram for explaining another operation example in the forward / backward search unit in the embodiment.

FIG. 14 is a flowchart illustrating a processing procedure of mapping determination in the embodiment.

FIG. 15 is a diagram illustrating a mapping result of an input cell in the embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 shaping processing buffer 2 scheduling processing unit 2a header identification unit 2b shaping parameter / calculation result storage unit 2c time management unit 2d scheduling calculation unit 3 mapping processing unit 3a address determination unit 4a forward search unit 4b backward search unit 41a, 42a Address decoder 41b Forward search address use state management unit 41c Forward empty address determination unit 42b Backward search address use state management unit 42c Back empty address determination unit

Claims (12)

[Claims] An ATM shaping memory search processing device for sharing one transmission band with cells having connection information of a plurality of logical path identifiers and logical channel identifiers and performing a shaping process for traffic control in the transmission band. The input cell is output after being delayed for a certain period of time, and a shaping process buffer for performing a shaping process, and when the storage addresses of the shaping process buffer conflict between different connection information and at an ideal predetermined transmission time, ATM shaping means for searching for a time closest to a predetermined transmission time of a cell, and when an empty area is detected in this search, mapping means for mapping the corresponding cell to the detected storage address. Memory search processing device. 2. A scheduling processing unit for calculating a required delay amount by calculating an interval between an input cell and a previous cell, as the search means, and an input based on a scheduling result in the scheduling processing unit. Detects the empty state of the cell storage address,
And a forward / backward search unit for searching for an empty area before / after a predetermined transmission time when a conflict occurs in which the detected address is mapped by another cell, and an empty space in the forward / backward search unit. The ATM shaping memory search processing device according to claim 1, further comprising: a mapping processing unit that performs a mapping process of input cells to a shaping process buffer based on the determination of the area. 3. The forward / backward search unit, when a conflict occurs, before a logical transmission time of an input cell, and
3. The AT according to claim 2, wherein a search is made for a free area having a free time closest to the logical transmission time of the input cell.
M shaping memory search processing device. 4. Searching for an empty area at an empty time before the transmission time and closest to the logical transmission time of the input cell, repeating the empty area at each time one cell before the logical transmission time. 4. The ATM shaping memory search processing device according to claim 3, wherein the search is performed by searching. 5. The forward / backward search unit searches for a free area at a free time after the logical transmission time of the input cell and closest to the logical transmission time of the input cell when a conflict occurs. The ATM shaping memory search processing device according to claim 2, wherein: 6. A search for an empty area at an empty time after the transmission time and closest to the logical transmission time of the input cell is performed by repeating the empty area at each time one cell after the logical transmission time. 6. The ATM shaping memory search processing device according to claim 5, wherein the search is performed by searching. 7. When the forward search section searches for an empty time area before the logical transmission time of an input cell when a conflict occurs, the forward search section performs shaping from the logical transmission time of the previous cell having the same connection information number. 3. The ATM shaping memory search processing device according to claim 2, wherein the search is performed within an interval that is not before the time at which the interval is guaranteed. 8. A scheduling unit, comprising: a header identification unit for identifying a header of an input cell; a shaping parameter / operation result storage unit for storing a shaping parameter and an operation result; and a time management unit for managing time. The ATM shaping memory search processing device according to claim 2, further comprising: a scheduling operation unit that performs a scheduling operation. 9. A forward / backward search address use state managing unit for managing address information indicating a storage area in a shaping processing buffer corresponding to a logical transmission time of an input cell, as the forward / backward search unit, A forward / backward vacant address determining unit that determines a vacant region near a logical transmission time based on a vacant region search result by the forward / backward search address use state management unit. 3. The ATM shaping memory search processing device according to 3. 10. An ATM shaping memory search processing device, wherein the device according to claim 1 is provided at a transmitting end of a user communication terminal in an ATM network. 11. The ATM according to claim 1, wherein said apparatus is provided at an ATM network transmitting / receiving end.
Shaping memory search processing device. 12. An ATM shaping memory search processing device, wherein the device according to claim 1 is provided in a traffic control node in an ATM network.