JPH11136254A - Atm shaping memory storage processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the accurate scrapping/processing of an inputted ATM cell even in a transmission band whose the burst property is increased without increasing the capacity of a shaping processing buffer. SOLUTION: ATM cells having the connection information of plural logical path identifiers and logical channel identifiers share one transmission band and shaping processing is conducted for traffic control in the transmission bond. A shaping processing buffer 1 delays an input ATM cell for a prescribed time and outputs the delayed cell. A scheduling processing section 2 calculates an interval between the input ATM cell and a preceding ATM cell in the unit of the connection information to decide a required delay amt. Furthermore, a mapping processing section 3 retrieves a closest vacant time after the logical transmission time of the ATM cell in the case that the contention of storage addresses in the shaping processing buffer 1 is generated at a prescribed transmission time between the connection information and conducts the mapping processing of the corresponding ATM cells for the corresponding storage address at the time of detecting the vacant area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM shaping memory for performing shaping processing on ATM traffic, such as a user communication terminal transmitting end, an ATM (asynchronous transfer mode) network transmitting / receiving end, and a traffic control node in an ATM network. The present invention relates to a processing device, and more particularly, to an ATM shaping memory storage processing device that searches for a free area even when an overflow exceeds the capacity of a shaping processing buffer.

[0002]

2. Description of the Related Art Conventionally, an ATM network uses an ATM.
The number of ATM cells (48 bytes: information field, 5 bytes: header field) in traffic is transmitted in proportion to the bit rate of each channel. For this reason, ATM cells are stored in a cell delay buffer and waited, and the time axis thereof is adjusted and transferred. That is, A
Shaping (alignment) processing for improving non-uniformity of ATM cells in TM traffic is performed.

In this shaping process, one transmission band is assigned to a plurality of logical path identifiers (VPI: Virtual Path Identifi
er) and a logical channel identifier (VPI: Virtual Channel Ide
In the case where the ATM cells having the connection information of the ATM network share the transmission band of one ATM network, in particular, to reduce the burstiness of the ATM cell flow generated inside this transmission band due to the traffic characteristics of the ATM network. , ATM cell flow transmission time management,
That is, an input ATM cell (received ATM cell) is transmitted with a predetermined interval of delay based on a predetermined parameter in a contract or the like.

For example, in Japanese Unexamined Patent Publication No. Hei 6-46085, "Multiplexing Cross Connect Device", the result of measurement of the queue length of a buffer in a multiplexing cross connect device reaches a certain value smaller than the buffer length. At this time, a restriction signal for restricting reception of a call to a required path is transmitted. This reduces ATM cell discard due to buffer overflow. In this publication, in order to improve the non-uniformity of ATM cells in ATM traffic, a buffering function in an ATM switch is used and a shaping process is performed under the control of the CPU. It cannot handle shaping processing with traffic.

[0005] In ATM traffic, when sharing the same transmission band, a burst occurs that the network administrator determines to be acceptable. That is, a large number of ATM cell multiplexing in an ATM network and tagging for allowing a violating ATM cell are included. Therefore, a cell delay buffer necessary for a shaping process corresponding to a predetermined design value such as ATM traffic is used. I have. That is, in order to reduce the burst property, the operation of separating the ATM cell interval of the input ATM cell from the previous ATM cell by a certain interval or more is performed. In this case, a burst ATM cell that exceeds the capacity of a cell delay buffer that delays an input ATM cell by a certain interval or more is likely to occur.

[0006] Input ATM cells exceeding this capacity are unconditionally discarded. In this case, the capacity of the cell delay buffer is increased as a countermeasure. However, the appropriate increase in the capacity is not easily known in advance, that is, when designing the ATM network. Further, if the capacity of the cell delay buffer is increased, the size of the device is increased.

[0007]

As described above, in the above conventional example, a burst ATM cell exceeding the capacity of the cell delay buffer is likely to be generated, and the input A exceeding the capacity is required.
TM cells are unconditionally discarded, and the reliability of data transmission is reduced. If the capacity of the cell delay buffer is increased as a countermeasure, an appropriate increase in the capacity is not easily known in advance, that is, at the time of designing the ATM network. The scale increases. If the necessary capacity is not increased, the reliability of data transmission is reduced as described above.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art, and can be implemented by multiplexing ATM cells or tagging ATM cells in an ATM network without increasing the capacity of a buffer for shaping processing. Even in the transmission band where the burst property has increased,
It is an object of the present invention to provide an ATM shaping memory storage processing device capable of accurately and reliably discarding input ATM cells (received ATM cells).

[0009]

To achieve the above object, according to the present invention, an ATM cell having connection information of a plurality of logical path identifiers and logical channel identifiers shares one transmission band, AT for performing shaping processing for traffic control in this transmission band
In the M-shaping memory storage processing device, the input AT
A shaping processing buffer for delaying and outputting M cells, an input ATM cell in connection information units, and a previous AT
Address management means for calculating a required delay amount by calculating an interval from the M cell, and searching for a free area in the shaping processing buffer upon overflow based on the connection information and the scheduling result of the input ATM cell; It is provided as a configuration.

According to a second aspect of the present invention, in the ATM shaping memory storage processing device, the address management means calculates a space between an input ATM cell and a previous ATM cell in connection information units to determine a required delay amount. When a storage address conflict in the shaping process buffer occurs between the unit and the connection information and at a predetermined transmission time, a search is performed for the closest free time after the logical transmission time of the ATM cell, and this free area is detected. And a mapping processing unit that performs a mapping process on the ATM cell corresponding to the corresponding storage address.

According to a third aspect of the present invention, there is provided an ATM shaping memory storage processing device which stores input ATM cells of connection information having a burst property exceeding the capacity of the shaping processing buffer in the shaping processing buffer in connection information units. The configuration is such that the shaping process is performed within the capacity of the shaping process buffer.

According to a fourth aspect of the present invention, in the ATM shaping memory storage processing device, the scheduling processing unit includes a header identifying unit for identifying a header of an input ATM cell, and a shaping parameter / operation result for storing a shaping parameter and an operation result. The configuration includes a storage unit, a time management unit that manages time, and a scheduling operation unit that performs scheduling operation.

According to a fifth aspect of the present invention, in the ATM shaping memory storage processing device, an input A is used as the mapping processing unit.
The configuration includes an address use / unused management unit that manages address information indicating a storage area in the shaping processing buffer corresponding to a logical transmission time of a TM cell, and a vacant address determination unit that determines a vacant address. .

According to a sixth aspect of the present invention, in the ATM shaping memory storage processing device, identification information identifying high priority information indicating that the header field of the ATM cell cannot be discarded or low priority information indicating unconditional discarding is transmitted to the mapping processing unit. Further comprising an ATM cell identification unit for identifying high-priority information or low-priority information for an input ATM cell, and when the identification information is low-priority information,
The configuration is such that input ATM cells are unconditionally discarded at the time of overflow due to processing through the mapping processing unit.

According to a seventh aspect of the present invention, there is provided an ATM shaping memory storage processing device comprising the steps of:
The configuration is provided at a user communication terminal transmitting end in a TM network.

According to an eighth aspect of the present invention, an ATM shaping memory storage processing device is provided in which the device according to the first to fourth aspects is configured such that:
It is configured to be provided at the transmission / reception end of the TM network.

According to a ninth aspect of the present invention, there is provided an ATM shaping memory storage processing device comprising the steps of:
The configuration is provided in a traffic control node in a TM network.

An ATM shaping memory storage processing device according to claims 1 to 5 and 7 to 9 having such a configuration,
The required delay amount is determined by calculating the interval between the input ATM cell and the previous ATM cell in connection information units, and based on the connection information of the input ATM cell and the scheduling result, the time required for the overflow in the shaping processing buffer is determined. Searching for free space.

Therefore, if the corresponding storage area in the transmission time management is free, the mapping processing is performed on the corresponding address. If another ATM cell has already completed the mapping processing and competes, the result of the search for the free area is performed. When an empty address is detected, mapping processing for the address can be performed, and storage at the end of the shaping processing buffer can be performed at the time of an overflow calculation result in the scheduling processing.

The ATM shaping memory storage processing device according to any one of claims 6 to 9 is characterized in that an input ATM cell is processed by an AT
High priority information (CLP = 0) indicating non-discardability of the header field of the M cell or low priority information (CL
P = 1), and processing for unconditionally discarding an input ATM cell upon overflow is performed based on the identification information when the low priority information is identified.

As a result, without increasing the capacity of the shaping processing buffer, even in the transmission band where the burstiness caused by ATM cell multiplexing or tagging ATM cells in the ATM network is increased,
It is possible to accurately and reliably discard input ATM cells (received ATM cells).

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an ATM shaping memory storage processing apparatus of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an ATM shaping memory storage processing device according to a first embodiment of the present invention. In this example, a shaping processing buffer 1 for delaying and outputting an input ATM cell for a fixed time, and a scheduling for determining a required delay amount by calculating an interval between the input ATM cell and the previous ATM cell in connection information units. And a processing unit 2. Further, when a conflict occurs between the connection information and the storage address in the shaping processing buffer 1 at a predetermined transmission time, the corresponding A
It has a mapping processing unit 3 that searches for the closest free time after the logical transmission time of the TM cell and performs a mapping process on the ATM cell corresponding to the corresponding storage address when a free area is detected by this search.

The shaping processing buffer 1 has an input A
Random writing and sequential reading of the TM cell are performed by using the write address and the read address from the mapping processing unit 3 shown in FIGS. The scheduling processing unit 2 transmits the input ATM cell at a predetermined interval so that the previous AT in the same connection information is transmitted.
After determining the necessary delay amount by calculating the interval from the M cell by a shaping algorithm operation, the storage address of the input ATM cell indicating a predetermined transmission time is transmitted.

The mapping processing unit 3 detects the vacancy status at the corresponding address based on the input ATM cell storage address from the scheduling processing unit 2, or the contention occurs when the corresponding address ends mapping of another ATM cell. When the state is reached, a search for the nearest free area after the corresponding address is executed. In this execution, the storage area of the input ATM cell in the shaping processing buffer 1 is determined, and the connection information number of the input ATM cell and the presence / absence information of the storage of the ATM cell are stored in the free area address indicating the corresponding free area. Further, the mapping processing section 3 outputs the write address of the input ATM cell to the shaping processing buffer 1 and executes the mapping processing of the input ATM cell.

FIG. 2 is a block diagram showing the arrangement of the ATM shaping memory storage processor shown in FIG. 1 in an ATM network. In this example, the ATM cell delay fluctuation (CVD: Cel) between a plurality of ATM networks (ATM subscriber network 5, ATM relay networks 6, 7).
l Delay Variation), the input unit of the ATM device, that is, UNI (User Network Interface) between ATM subscriber network 5 and ATM relay network 6
And NNI (Netwar between ATM relay networks 6 and 7)
The ATM shaping memory storage processing devices 8 and 9 are provided at (k Node Interface).

FIG. 3 is a block diagram showing another arrangement state of the ATM shaping memory storage processing device shown in FIG. 1 in the network. This example shows an ATM cell delay fluctuation (CVD) between a plurality of ATM networks (ATM subscriber network 5, ATM relay networks 6, 7).
Output of the ATM device to absorb the
Subscriber network 5, ATM relay network 6,7
ATM shaping memory storage processing devices 10 and 11 are provided in the UNI between them and the NNI between relay networks.

FIG. 4 is a block diagram showing a configuration of a device in which the ATM shaping memory storage processing device shown in FIG. 1 is arranged. This example uses an ATM cell interface (I /
F) It has cell delay buffers 13, 14,... 1n to which ATM cells from the circuit are input. Further, the ATM cells from the cell delay buffers 13...
X), multiplexed by 16, and an ATM shaping memory storage processing device 17 is arranged at the subsequent stage.

FIG. 5 is a block diagram showing another device configuration in which the ATM shaping memory storage processing device shown in FIG. 1 is arranged. In this example, a cell delay buffer 2 into which an ATM cell is input from an input port of an ATM switch (SW) is shown.
An ATM shaping memory storage processor 30 is provided on the output side of 0, 21... 1n, and an ATM switch (SW) 31 is provided as a subsequent stage.

FIG. 6 is a block diagram showing still another device configuration in which the ATM shaping memory storage processing device shown in FIG. 1 is arranged. In this example, an ATM cell is transmitted through an ATM switch (SW) 32 to cell delay buffers 33, 34,.
n, and the output of the ATM shaping memory storage processor 40 provided on this output side,
ATM from output port as ATM switch (SW)
A cell is sent.

FIG. 7 is a block diagram showing the internal configuration of the scheduling processing section 2 in FIG. The scheduling processing unit 2 has a header identification unit 2a for identifying a header of an input ATM cell, a shaping parameter / operation result storage unit 2b for storing a shaping parameter and an operation result, and further manages time. Time management unit 2
c and a scheduling operation unit 2d for performing a scheduling operation.

FIG. 8 is a block diagram showing the internal configuration of the mapping processing unit 3 in FIG. This mapping processing unit 3
Includes an address use / unused management section 3a for managing address information indicating a storage area in the shaping processing buffer 1 corresponding to a logical transmission time of an input ATM cell, and an empty address determination section 3b for determining an empty address. Have. The mapping processing unit 3 and the scheduling processing unit 2 shown in FIG. 7 can be realized by a logical operation such as a microprocessor (MPU).

Next, the operation of the first embodiment will be described. In FIG. 1, an ATM cell stream having a traffic characteristic with a high burst property in the same transmission band is input to a shaping processing buffer 1 and a scheduling processing unit 2. In the scheduling processing unit 2, the header identification unit 2a shown in FIG. 7 extracts the connection information number (VPI, VPI) in the corresponding ATM cell from the header field of the input ATM cell.

The scheduling processing unit 2 sends the arrival time of the input ATM cell, the transmission time information of the same connection information number previously inputted, and the transmission ATM information set in advance for the connection information number. Based on the cell interval information, the theoretical transmission time of the input ATM cell is shown in FIG. 7 by a shaping parameter / operation result storage unit 2b, a time management unit 2c, and a scheduling operation unit 2d.
Performs the shaping algorithm operation.
The theoretical transmission time of the input ATM cell determined by this operation is transmitted to the mapping processing unit 3.

Upon receiving the address information from the scheduling processing unit 2, the mapping processing unit 3 manages the address information indicating the storage area in the shaping processing buffer 1 corresponding to the logical transmission time of the input ATM cell. Used / unused management section 3a and empty address determination section 3
In step b, a determination is made as to whether or not the address is available at a predetermined transmission time of the input ATM cell.

When address information that causes an overflow in the shaping processing buffer 1 is input from the scheduling processing unit 2 as an operation result, the mapping processing unit 3
The closest corresponding AT in the storage area of the shaping processing buffer 1 from the arrival time of the input ATM cell.
The connection information number of the input ATM cell and the ATM cell storage end information are stored in the address use / unused management section 3a and the empty address determination section 3b, using the M cell transmission time as the corresponding address, and the corresponding address information is shaped. Output to the processing buffer 1 as write address information. As a result, the shaping process is performed without discarding the input ATM cell.

Next, the main part of the first embodiment will be described. FIG. 9 is a block diagram showing the contents of the ATM cell empty area management table. As described above, when the ATM cell stream having the traffic characteristics with high burst characteristics in the same transmission band is input to the shaping processing buffer 1 and the scheduling processing unit 2, the header identification unit 2a shown in FIG. From the header field of the ATM cell, the connection information number (VPI,
VPI).

After this extraction, the theoretical transmission time of the input ATM cell is determined based on the arrival time of the arrival time of the input ATM cell and the transmission ATM cell interval information set in advance for the corresponding connection information number. Is transmitted to the mapping processing unit 3 through the shaping parameter / operation result storage unit 2b, the time management unit 2c, and the scheduling operation unit 2d shown in FIG.

Upon receiving the address information from the scheduling processing unit 2, the mapping processing unit 3 manages the address information indicating the storage area in the shaping processing buffer 1 corresponding to the logical transmission time of the input ATM cell. Used / unused management section 3a and empty address determination section 3
Through the processing of b, the vacant state of the address corresponding to the predetermined transmission time of the input ATM cell is determined.

When address information that causes an overflow in the shaping processing buffer 1 is input from the scheduling processing unit 2 as an operation result, the mapping processing unit 3
As shown in FIG. 9, 1 ATM of the arrival time of the input ATM cell
ATM from shaping processing buffer 1 before cell time
The management address at which the cell is transmitted and becomes an empty area, that is, the address corresponding to the ATM cell transmission time closest to the overflow in the storage area of the shaping processing buffer 1 from the ATM cell arrival time corresponding to the overflow, The write address information to be stored in the shaping processing buffer 1 is determined.

FIG. 10 is a block diagram showing the configuration of the second embodiment. In the second embodiment, the first embodiment shown in FIG.
In addition to the shaping processing buffer 1, the scheduling processing unit 2, and the mapping processing unit 3 of the configuration of the embodiment,
An ATM cell identification unit 4 for identifying the CLP bit of the header field of the ATM cell is provided.

In the second embodiment, the shaping buffer 1, the scheduling unit 2, and the mapping unit 3 operate in the same manner as in the first embodiment. The ATM cell identification unit 4 identifies CLP = 0, which is high-priority information indicating that discarding is not possible, or CLP = 1, which is low-priority information indicating unconditional discarding, for an input ATM cell. The ATM cell identification unit 4 sends this identification information to the mapping processing unit 3. The mapping processing unit 3 executes a process for unconditionally discarding an input ATM cell when an overflow occurs, based on the identification information of CLP = 1, which is low priority information indicating unconditional discard.

[0042]

As is apparent from the above description, according to the ATM shaping memory storage processing device according to the first to fifth and seventh to ninth aspects, the input A is performed in connection information units.
The required delay amount is determined by calculating the interval between the TM cell and the previous ATM cell, and based on the connection information of the input ATM cell and the scheduling result, a search for an empty area is performed even when an overflow occurs in the shaping processing buffer. Is going.

Also, in the ATM shaping memory storage processing device according to the present invention, the input ATM cell is unconditionally determined when the input ATM cell overflows, based on the identification information when the low priority information is identified. Perform the process of discarding.

As a result, without increasing the capacity of the shaping processing buffer, even in a transmission band where the burstiness generated by ATM cell multiplexing and tagging ATM cells in an ATM network is increased.
Accurate and reliable discard processing of input ATM cells becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an ATM shaping memory storage processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an arrangement state of an ATM shaping memory storage processing device in the first embodiment.

FIG. 3 is a block diagram showing another arrangement state of the ATM shaping memory storage processing device in the first embodiment.

FIG. 4 is a block diagram showing a device configuration in which an ATM shaping memory storage processing device is arranged in the first embodiment.

FIG. 5 is a block diagram showing another device configuration in which the ATM shaping memory storage processing device is arranged in the first embodiment.

FIG. 6 is a block diagram showing still another device configuration in which the ATM shaping memory storage processing device is arranged in the first embodiment.

FIG. 7 is a block diagram illustrating an internal configuration of a scheduling processing unit in FIG. 1;

FIG. 8 is a block diagram illustrating an internal configuration of a mapping processing unit in FIG. 1;

FIG. 9 is a block diagram showing the contents of an ATM cell empty area management table in the first embodiment.

FIG. 10 is a block diagram illustrating a configuration of a second embodiment.

[Explanation of symbols]

Reference Signs List 1 buffer for shaping process 2 scheduling processing unit 2a header identification unit 2b shaping parameter / calculation result storage unit 2c time management unit 2d scheduling calculation unit 3 mapping processing unit 3a address use / unused management unit 3b empty address determination unit 4 ATM Cell identification unit 8 to 11, 17, 30, 40 ATM shaping memory storage processing device

Claims (9)

[Claims] 1. A transmission band having connection information of a plurality of logical path identifiers and logical channel identifiers.
An ATM shaping memory storage processing device for sharing a TM cell and performing a shaping process for traffic control in the transmission band, comprising: a shaping process buffer for delaying and outputting the input ATM cell; and an input for each connection information unit. ATM cell and previous AT
Address management means for calculating a required delay amount by calculating an interval from the M cell, and searching for a free area in the shaping processing buffer upon overflow based on the connection information and the scheduling result of the input ATM cell; and An ATM shaping memory storage processing device, comprising: 2. A scheduling processing unit for calculating an interval between an input ATM cell and a previous ATM cell in connection information units to determine a required delay amount, as the address management means, In the case where a storage address conflict occurs in the shaping processing buffer, the nearest vacant time after the logical transmission time of the ATM cell is searched, and when this vacant area is detected, the ATM corresponding to the corresponding storage address is searched. The ATM shaping memory storage processing device according to claim 1, further comprising: a mapping processing unit that performs a cell mapping process. 3. An input A of connection information having a burst property exceeding a capacity of the shaping processing buffer.
2. The ATM shaping memory storage processing device according to claim 1, wherein the TM cells are stored in the shaping processing buffer in connection information units, and the shaping processing is performed within the capacity of the shaping processing buffer. 4. A scheduling unit, a header identification unit for identifying a header of an input ATM cell, a shaping parameter / operation result storage unit for storing a shaping parameter and an operation result, and a time management unit for managing time. 3. The ATM shaping memory storage processing device according to claim 2, further comprising a scheduling unit and a scheduling operation unit that performs a scheduling operation. 5. An address use / unused management section for managing address information indicating a storage area in a shaping processing buffer corresponding to a logical transmission time of an input ATM cell, and a vacant address as the mapping processing section. 3. The ATM shaping memory storage processing device according to claim 2, further comprising: an empty address judging unit for judging. 6. An A for transmitting high-priority information indicating that the header field of the ATM cell cannot be discarded or low-priority information indicating unconditional discarding of the header field of the ATM cell to the mapping processing unit.
The ATM cell identifying unit further identifies high-priority information or low-priority information with respect to an input ATM cell, and when the identification information is low-priority information, passes through the mapping processing unit. 3. The ATM shaping memory storage processing device according to claim 2, wherein the input ATM cell is discarded unconditionally when an overflow occurs due to the processing. 7. An apparatus according to claim 1, wherein said apparatus is an AT.
An ATM shaping memory storage processing device provided at a transmitting end of a user communication terminal in an M network. 8. An apparatus according to claim 1, wherein said apparatus is an AT.
A provided at the transmitting / receiving end of the M network
TM shaping memory storage processor. 9. The apparatus according to claim 1, wherein said apparatus is an AT.
An ATM shaping memory storage processing device provided at a traffic control node in an M network.