JP2756766B2 - Cell priority processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell priority processing apparatus for selecting and outputting only valid cells from low priority cells when processing and outputting cell information input from a plurality of paths. is there.

[0002]

2. Description of the Related Art As is well known, in the ATM system, when congestion occurs in a relay node, cells that cannot be processed are discarded. In this case, inconvenience may occur if unprocessed cells are uniformly discarded simply because they could not be processed. For example, when transmitting image information, loss of outline information causes a fatal defect, but even if color information of a thin portion such as hair is lost, the quality does not significantly deteriorate.

In such a case, a high-priority cell that transmits information that is lost or hindered on the receiving side is stored in a high-priority buffer, and a low-priority cell that transmits information that is not hindered even if lost is low. There is a method in which data is stored in a high-priority buffer and data in a low-priority buffer is read out only after all information in a high-priority buffer is read. FIG. 5A is a diagram for explaining an example when there is no congestion in performing such a read operation.
High priority cells written in uppercase alphabets from
This is an example in which low-priority cells described in lowercase alphabets are alternately input. As shown in FIG. 5, both the high-priority cell and the low-priority cell are configured such that two cells of the same type continue, followed by two cells of different types. In this example, the high-priority cells are 2 at times t1 and t2.
One or more low-priority cells are alternately input at times t3 and t4. In this example, the output path first includes the high priority cells A1, B
1, A1 ', B1' are read out, and after reading out, the low priority cells a1, b1, a1 ', b1' are read out. However, when congestion occurs, as shown in FIG. 5B, after the low-priority cells a1 'and b1' arrive at time t4, and the high-priority cells A2, B2, A2 'and B2' arrive at time t5 and t6. , Since the high-priority cells are read first in the output path, the high-priority cells A1, B1, A1 ', B1',
A2, B2, A2 ', B2' are read, and only after that are the low priority cells a1, b1,.
Here, A1, A1 ', a1, a1' are information of the same group, for example, a set of information in which high-priority information and low-priority information of the first pixel are combined. A2, A2 ', a
2, a2 'is a set of information in which high-priority information and low-priority information of a second pixel, which is a place completely different from the first pixel, are combined, for example, information different from the set of information.
According to this method, when congestion occurs in the relay node and continues forever, the low-priority buffer becomes full, and the data in the low-priority buffer is not read until the reading of the data in the high-priority buffer is completed. The priority buffer overflows and subsequently arriving low priority cells are discarded.

[0004]

In such an example, when there is no congestion as shown in FIG. 5 (a), when the path 1 and the path 2 have the information of the group A at the time from t1 to t4, the information of the group A and the information of the group Since the information of the irrelevant B group is processed without interruption, the low priority cell can be read after the high priority cell. That is, the low priority cell a
1, a1 'is separated from the high-priority cells A1 and A1',
It can be managed that the low-priority cells a1 and a1 'follow the high-priority cells A1 and A1'. However, when congestion occurs and the state is as shown in FIG. 5B, since the set of the high-priority cells A1 and the set of the high-priority cells A2 are completely different information, there is no relation after the high-priority cells A1 and A1 '. High priority cells A2 and A2 'without an interrupt
Thereafter, the low-priority cells a1 and a1 'corresponding to the high-priority cells A1 and A1' arrive and are output. Therefore, the processing of the A1 group information is cut off halfway, and the low-priority cells output later are output. a1 and a1 'cannot be used. That is, for example, the low priority cells a1 and a1 'are invalidated. The invalidated low priority cell is not used even if it is read. If the invalidated low-priority cell is accumulated in the low-priority buffer in this way, even if the low-priority cell of another path overflows from the buffer and is discarded or is temporarily stored in the low-priority buffer, it is invalid. Unless the changed low priority cell is read, the low priority cell arriving later is not read. For this reason, the low priority cells arriving later are added with the delay, and the low priority cells arriving later are invalidated depending on the amount of delay, causing a problem that the quality of the entire network deteriorates. The present invention has been made in view of such a situation, and has been made to prevent quality deterioration of the entire network caused by invalid low-priority cells remaining in a low-priority buffer. .

[0005]

In order to achieve the above object, the invention according to claim 1 provides an arrival cell indicating the beginning of a frame.
Timing detection that detects the beginning of the frame based on the
Output means and the head timing detection means
If the head is detected, the high-priority cell at the beginning of the frame is detected.
Of the previous frame that arrived earlier from the same path as
Judge the low priority cells as invalid cells and only these low priority cells
Discard judgment processing means to display discard for
Priority cells are read out from the
When all high priority cells are read from the priority buffer
Has a low priority that is not discarded from the low priority buffer
Selective reading means for reading and transmitting only cells
Things. The invention of claim 2 is the invention of claim 1.
At the end of the frame
Same as low priority cell after arrival of low priority cell indicating tail
A high-priority cell that does not indicate the end of the frame arrives from
The frame head is detected when
You.

[0006]

When the head timing of the high priority cell arriving after the low priority cell is detected, the low priority cell arriving before that is invalidated, and the low priority cell which has not been invalidated when reading the low priority cell is selected. Read.

[0007]

FIG. 1 is a block diagram showing an embodiment of the present invention. Prior to the transfer of information, the transmitting terminal determines a peak band and a guaranteed band which must be transmitted reliably even when the network is congested. The network secures a high-priority buffer for the calling terminal up to this guaranteed bandwidth by the capacity corresponding to the request, and lowers the bandwidth up to the peak rate exceeding that bandwidth in consideration of the statistical multiplexing effect. Allocate a priority buffer. Furthermore, the information to be transmitted here assumes that low-priority cells can be discarded, such as moving images,
The source terminal assigns priorities to information in one frame, for example, in the order of frame synchronization information, skeleton information, color information, and the like, and converts the information into ATM cells in the order of information having the highest priority. And the block of the low priority cell occur alternately. At this time, AT
In the M cell header, two types of priority identifiers using, for example, a CLP (Cell Loss Priority) field, according to the information priority and the information unit, and AAL5
An identifier in units of PDU (protocol data unit) composed of an identifier in units of packets using a PT (payload type field) in the (ATM adaptation layer) is added.

In FIG. 1, when a plurality of paths n are respectively connected to identification circuits 1-1 to 1-n corresponding to the paths, and a calling terminal connected to the paths makes a call,
For example, when there is a call request from the calling terminal, the call admission control unit 2 detects the request, notifies the calling terminal of the VPI value and the VCI value, and sets the VPI value in the table 3a in the low priority buffer queue management unit 3 , "1" is written into the call acceptance flag at the position corresponding to the VCI-compatible address as information indicating that the call is permitted. The table 3a is designed to write information in the format of FIG. 2 (a). The contents of the writing will be described later, but the table 3a is used to detect the head position of the high priority cell arriving after the low priority cell. You.
Note that "0" is written in the call acceptance flag when the call is released.

Then, a cell is transmitted from the calling terminal to the identification circuit 1 for example.
-1 when it arrives at the VP by referring to the header of the cell.
The control unit 3b of the low priority buffer queue management unit 3 is notified of the I, VCI value, CLP value, and PT value. The control unit 3b detects an address corresponding to the VPI and VCI values in the table 3a, and checks whether or not the call reception flag corresponding to the address is set to “1”. When this flag is set to “1”, CLP is controlled by the control circuit 3b.
The value and the PT value are written to the table 3a. Then C
The LP value is directly written into the CLP flag in FIG. On the other hand, in ALL5, a block is composed of two or more blocks and transmitted.
The T value is determined to be “000” or “010.” In this case, “0” is written to the PT flag in FIG. The cell at the end of the block is determined so that the PT value is “001” or “011”. At this time, "1" is written to the PT flag. However, if the call acceptance flag written in the address corresponding to the VPI and VCI values is "0", it means that a call that has not been permitted to arrive has arrived, and the arriving cell is discarded.

When the CLP value is “0”, the cell is a high-priority cell. Therefore, the control circuit 3 b of the low-priority buffer queue management unit 3 controls the high-priority buffer to write the arriving cell into the high-priority buffer 4. Is controlled. C
When the LP value is “1”, the cell is a low-priority cell, and the control circuit 3 b controls the low-priority buffer write control unit 7 to write the arriving cell into the low-priority buffer 6. When data is written to the low-priority buffer 6, the write VPI, VC
The I value and the cell write start address of the low priority buffer 6 are written. In the table 3b, information is written in the form of FIG. 2B. The VPI and VCI values of the low-priority cells to be written into the low-priority buffer, the write start address,
Information for determining whether the written cell is valid or invalid is written to the address indicated by the write pointer. The operation of writing valid or invalid information will be described later.

The same processing is performed on cells arriving one after another, but the control circuit 3b of the low priority buffer queue management unit 3 checks the CLP flag and PT flag of the table 3a and the CLP value and PT value of the arriving cell. With reference to C
LP flag = 1, the condition of PT flag 1 is satisfied, and reception CLP value = 0 and reception PT value = 0
When all the conditions are satisfied, the table 3
The CLP flag and the PT flag of a are updated, and an invalid cell determination described later is performed. . When the relationship between the CLP value and the PT value described above does not hold, the CLP flag and the PT flag in the table 3a are only updated according to the received value without determining the invalid cell.

The cell information written in the high-priority buffer 4 is read out in the order of writing under the control of the read control unit 8 of the high-priority buffer. The high-priority buffer phase difference detection circuit 9 refers to the contents of the write control circuit 5 and the contents of the read control circuit 8, and when they match, it means that all the contents of the high-priority buffer 4 have been read. Since the contents of the low-priority buffer 6 can be read after that point, the phase difference detection circuit 9 notifies the control circuit 3b of the low-priority buffer queue management unit 3 of the fact. As a result, the control circuit 3b operates the read control unit 10 for reading the low-priority buffer.
To read the information of the low priority buffer 6.

From the header of the arriving cell, the condition of CLP flag = 1 and PT flag 1 is satisfied, and the reception CL
When P value = 0 and all the conditions of the received PT value = 0 are satisfied, the control circuit 3b updates the CLP flag and the PT flag of the table 3a according to the received value as described above. Thus, the determination of the invalid cell is also performed. At this time, the write VPI, V
If the CI value is registered, it is determined that the cell is an invalid cell, and the discard flag in the table 3c is set to “1”.

As described above, in the AAL5, when the PT is 000, that is, when the PT flag = 0, it means that the end of the frame is not attained. When the PT is 001, that is, the PT flag = 1 is at the end of the frame. Utilizes what is negotiated to mean. For this reason, the end of the frame is detected, and the end is that of the low-priority cell. If the cell that arrives next is the high-priority cell, it is the head of the high-priority cell. If there is a low-priority cell that has not been read at that time, it is already invalid, so it is determined to be an invalid cell, and the discard flag in the table 3c is set to "1".

This will be described in more detail as follows. In this example, as shown in FIG. 3, cells sequentially arrive at the input path 1 and the input path 2, are processed by the ATM relay node, and transmitted to the output path. Then, it is assumed that the call acceptance processing is completed for all the paths, and that the calling is permitted, and the VPI / VCI correspondence address of the path 1 is as shown in FIG.
And the address corresponding to the VPI and VCI of the path 2 is “e” in FIG.

FIG. 4 (a) is a table in which only the portions where the VPI and VCI addresses are "c" and "e" are extracted from the information of the table 3a written each time a cell arrives.
At time t1 shown in FIG. 3, the A1 cell of path 1 has arrived. Since this cell is a high-priority cell, the CLP value of the CLP flag in FIG. At t1, the data is written to the table 3a. The table 3a is originally rewritten to the contents each time a cell arrives at each time in FIG. 2. However, in order to explain the time conversion, the CLP flag, P
The T flag is also shown in the order of arrival with the cell symbol.

At time t1 in FIG. 3, cells A1 and B1 arrive, but cell A1 is at the end of the block, that is, the symbol A
It is not the end of the high priority cell set following 1, A1 '. Since the CLP value indicating the high-priority cell is “0”, “0” is written in a portion corresponding to the cell A1 at time t1 in the CLP flag in FIG. Since the block is not at the end of the block, the PT flag indicating this is “0”, and “0” is written in a portion corresponding to the cell A1 at time t1 in the PT flag. Next at the same time t1
In the input path 2, since the cell B1 has arrived, the cell B1 is similarly placed in the portion "e" which is the VPI / VCI correspondence address in FIG.
P = 0 and PT = 0 indicating that it is not the end of the block are written. That is, “0” is written in a portion corresponding to the cell B1 at the time t1 in the CLP flag of FIG. 4A, and “0” is written in the position of the cell B1 in the PT flag at the time t1. At time t2 in FIG.
1 'and B1' arrive, but since this is a high priority cell, CLP = 0. Also, PT = 1 because it is the end of the block, that is, the end of the set of cell A and cell B.
Therefore, “0” is written at the position of the cell A1 ′ at the time t2 of the CLP flag in FIG. 4, and “0” is written at the position of the cell B1 ′. Further, since this cell is the end of the block of the high priority cell, PT = 1. Therefore, “1” is written at the position of the cell A1 ′ at the time t2 of the PT flag, and “1” is written at the position of the cell B1 ′.

At time t3 in FIG. 3, cells a1 and b1 arrive and are CLP flags = 1 because they are low priority cells.
And PT = 0 because it is not the end of the block. Therefore, the cell a at the time t3 of the CLP flag in FIG.
“1” is written at the position of “1”, and “1” is written at the position of the cell b1. Also, the cell a1 at the time t3 of the PT flag
"0" is written at the position of cell b1 and "0" is written at the position of cell b1. At time t4, CLP = 1 because cells a1 'and b1' are low priority cells, and P
T = 1. Then, as shown in FIG. 4A, “1” is written at the position of the cell a1 ′ and “1” is written at the position of the cell b2 ′ at the time t4 of the CLP flag,
At the time t4 of the PT flag, “1” is written at the position of the cell a1 ′, and “1” is written at the position of the cell b1 ′.
Hereinafter, information is similarly written in the table 3a.

When a low-priority cell is written into the low-priority buffer 6, the information of the write VC is also stored in the table 3c.
The I and VPI values, the low-priority cell write start address, and the discard flag are written as shown in FIG. Write V
As the PI and VCI values, the VPI and VCI values of the arriving cell are written as is at the address indicated by the write pointer. In the description of FIG. 4A, it has been described that the addresses “C” and “E” are written at the same time.
Is set as the VPI and VCI values each time a low priority cell arrives.
"C" and "e" are written. However, in FIG. 4B, for easy understanding, information indicating which cell the written value corresponds to is also described. The write start address is described as “1” corresponding to the cell a1, and the address is increased by “1” every time a write is performed.

Since the reading is performed one timing later than the writing, as shown in FIG. 3, the cells are read as A1, B1, A1 ', and B1' in the order in which the high priority cells are written. Since the high-priority cells written in the high-priority buffer 4 of FIG. 1 are read before the low-priority cells, all the information in the high-priority buffer 4 is eventually read. The phase difference detection circuit 9 detects this and notifies the low priority buffer queue management unit 3 of the fact, so that the low priority buffer queue management unit 3 starts reading the cell a1 of the low priority buffer 6 from time t6. As described above, when the condition of CLP = 1 and PT = 1 is satisfied from the header of the arriving cell and the condition of received CLP value = 0 and received PT value = 0 is satisfied, writing of the table 3c is performed. If the VPI and VCI values are registered, it is determined that the cell is invalid, and the table 3c is determined.
Is set to "1".
In the example of FIG. 4A, the condition of CLP = 1 and PT = 1 is satisfied at time t4. At this time, the condition that the reception CLP value = 0 and the reception PT value = 0 is satisfied at time t5. That is, when the head cell of the high-priority cell arriving next to the low-priority cell is received, the discard condition of the low-priority cell on the path is determined. This determination is made for the cell between the read pointer and the write pointer shown in FIG. In FIG. 4, at time t5, a discard determination process is performed on the paths 1 and 2, and the cells a1, b1, and a1 'are discarded.
Since the write VPI and VCI values have been written up to b1 'at this point, the discard flag = 1 is set in that portion. In the example of FIG. 4B, the flag “1” is put in parentheses in the meaning that the discard flag is set at the time of this determination, not at the time of writing the information.

After time t7, the high-priority cell A
2, B2, A2 'and B2' are sequentially read. Cell B
Since the reading of all the contents of the high-priority buffer 4 is completed when 2 'is read, the contents of the low-priority buffer are read at time t12. At time t9, the low priority cell a
2 and b2 have arrived, so at time t12 table 3
Cell c is read, but cells with the discard flag set are not read. Therefore, the cells from address 1 to address 4 in FIG. 4B are not read out, and the low priority cells after cell a2 after address 5 are read out.

In the output path of FIG. 3, the read cells are described in order, but as can be seen from this figure, the cells become invalid after the high priority cells A2 and B2 are read. The low-priority cells a1 'and b1' surrounded by an ellipse are not read out, and when they are read out, the low-priority cells a2 and b2 that arrive later are read out. in this way,
When a high-priority cell arriving later is read out, the low-priority cell arriving earlier is invalidated because there is no opportunity to use it even if it is read out. Even at the read timing of the low-priority cell, if the invalid low-priority cell that is still valid at that time is read without reading such invalid low-priority cell, the read time of the low-priority cell to be read becomes There is no later than necessary. Although a specific method is not shown in the above example, it is assumed that a cycling buffer is used as the low-priority buffer, and the address is counted up by reading only the addresses occupied by invalid cells by this control. Accordingly, a new cell can be written by that amount, and the queue of low priority cells on the input side is less likely to overflow.

[0023]

As described above, according to the present invention, only the valid low-priority cells are read at the read timing of the low-priority buffer without reading the invalid low-priority cells. By adding a minute delay, it is possible to prevent a state where other valid cells are further delayed,
There is an effect that the transfer quality of ATM can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a diagram showing a structure of tables 3a and 3c.

FIG. 3 is a diagram illustrating a relationship between input cells and output cells.

FIG. 4 is a diagram showing an example of contents written in tables 3a and 3c.

FIG. 5 is a diagram showing a conventional read example.

[Explanation of symbols]

1-1 to 1-n: identification circuit, 2: call admission control unit, 3: low priority buffer queue management unit, 3a, 3c: table, 3
b: control circuit, 4: high priority buffer, 5, 7: write control unit, 6: low priority buffer, 8, 10, read control unit, 9 ...
Phase difference detection circuit.

Claims (2)

(57) [Claims] A plurality of image frame information is stored in each file.
High priority cells based on the importance of each information for each frame
Transfer with the lower priority cell that follows.
Based on the priority of each cell arriving from multiple paths
Arriving cells into high-priority and low-priority buffers
Each cell is stored, and the cells stored in these buffers are stored.
The number of cells stored in each buffer depends on the product status.
In the cell priority processing device that selects and sends one of the two, the top of the frame is determined based on the arrival cell indicating the top of the frame.
The head of the frame is detected by the head timing detection means to be detected and the head timing detection method.
Is the same as the high-priority cell at the beginning of the frame.
The lower priority cell of the previous frame that arrived earlier from the path
Are considered invalid cells, and only these low priority cells are discarded.
A discard determination processing unit for performing discard indication; and a high-priority cell read out from the high-priority buffer with priority and transmitted.
All high priority cells are read from the high priority buffer.
Is not discarded from the low-priority buffer,
Reading means for reading and transmitting only the low priority cells
Cell priority processing apparatus comprising: a. 2. A cell priority processing apparatus according to claim 1, wherein
Te, head timing detection means, after the arrival of the low priority cells showing the frame end, the low priority
High priority cells that do not indicate the end of the frame from the same path as the cell
A cell priority processing device for detecting the head of a frame when a packet arrives .