JPH08265324A - Cell preferential processor - Google Patents

Abstract

PURPOSE: To improve the transfer quality of an ATM by invalidating a cell with low priority arriving before the arrival of a cell with high priority when the leading timing of the cell with high priority arriving after the arrival of the cell with low priority is detected. CONSTITUTION: When the cell arrives from a transmission terminal at, for example, an identification circuit 1-1, a VPI, a VCI value, a CLP value and a PT value are informed to the control circuit 3b of a low priority buffer queue managing part 3 by referring to the header of the cell. Since the cell is the one with high priority when the CLP value shows zero, the circuit 3b controls a write control part 5 for high priority buffer so as to write an arriving cell on a high priority buffer 4. In such a constitution, when the cell with low priority arriving before the arrival of the one with high priority remains when the cell with high priority arriving later is written, processing to invalidate and prevent a remaining cell with low priority from being read out is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell priority processing apparatus for selecting and outputting only valid cells among low priority cells when processing and outputting cell information input from a plurality of paths. is there.

[0002]

2. Description of the Related Art As is well known, in the ATM system, when congestion occurs in a relay node, cells that cannot be processed are discarded. In this case, if unprocessed cells are uniformly discarded because the cells cannot be completely processed, inconvenience may occur. For example, in the case of transmitting image information, loss of contour information causes a fatal defect, but even if the color information of a thin portion such as hair is lost, the quality does not seem to deteriorate so much.

In such a case, the high-priority cells that transmit information that would otherwise be lost on the receiving side are stored in a high-priority buffer, and the low-priority cells that transmit information that is not significantly lost even if they are lost are low. There is a method of storing the data in the priority buffer and reading the data of the low priority buffer only after all the information of the high priority buffer is read. FIG. 5A is a diagram for explaining an example when there is no congestion in the case of performing such reading, and the path 1 and the path 2 are provided to the same node.
From the high-priority cells written in capital letters from
This is an example in which low-priority cells described in lowercase alphabets are alternately input. As shown in FIG. 5, two high-priority cells and two low-priority cells are of the same type, followed by two consecutive cells of different types. In this example, there are 2 high priority cells at times t1 and t2.
One or more consecutive low priority cells are alternately input in the form of two or more consecutive low priority cells at times t3 and t4. In this example, the high priority cells A1 and B are first provided in the output path.
1, A1 ', B1' are read, and after they are read, the low priority cells a1, b1, a1 ', b1' are read. However, when congestion occurs, low priority cells a1 ′ and b1 ′ arrive at time t4 and then high priority cells A2, B2, A2 ′ and B2 ′ arrive at times t5 and t6 as shown in FIG. 5B. , The high priority cells are read first in the output path, so the high priority cells A1, B1, A1 ′, B1 ′,
A2, B2, A2 ', B2' are read, and then the low-priority cells a1, b1, ... Are read for the first time.
Here, A1, A1 ', a1, and a1' are information of the same group, for example, a set of information in which high priority information and low priority information of the first pixel are combined. Also, A2, A2 ', a
2, a2 ′ is a set of information different from the set of information, for example, a combination of the high priority information and the low priority information of the second pixel which is a completely different place from the first pixel.
According to this method, when congestion occurs in the relay node and it continues forever, the low priority buffer becomes full, and the data in the low priority buffer cannot be read until the data in the high priority buffer has been read. The priority buffer overflows and low priority cells arriving after that are discarded.

[0004]

In such an example, as shown in FIG. 5 (a), when there is no congestion, the information of the group A of the path 1 and the path 2 is from t1 to t4, and Since the information of the irrelevant group B is processed seamlessly, there is no problem even if the low priority cells are read after the high priority cells. That is, the low priority cell a
1, a1 'is separated from the high priority cells A1, A1',
It can be managed that the low-priority cells a1 and a1 'follow the high-priority cells A1 and A1'. However, when congestion occurs and the state shown in FIG. 5 (b) is reached, since the set of high priority cells A1 and the set of high priority cells A2 are completely different information, there is no relation after the high priority cells A1 and A1 '. High priority cells A2 and A2 'which have no
Since the low-priority cells a1 and a1 ′ corresponding to the high-priority cells A1 and A1 ′ arrive and are output after that, the processing is cut off in the middle of the information of the A1 group, and the low-priority cells output later are output. a1 and a1 'cannot be used. That is, for example, the low-priority cells a1 and a1 'are invalidated. The invalid low-priority cell is not used even if it is read. When the invalid low priority cells are accumulated in the low priority buffer in this way, even if the low priority cells of other paths overflow from the buffer and are discarded or are stored in the low priority buffer, they are invalid. The low-priority cells that arrive later are not read unless the low-priority cells that have become read are read. Therefore, the low-priority cells arriving later are added with the delay, and even the low-priority cells arriving later are invalidated depending on the delay amount, which causes a problem that the quality deterioration of the entire network is spread. The present invention has been made in view of such a situation, and is intended to prevent the quality deterioration of the entire network caused by the retention of invalid low-priority cells in the low-priority buffer. .

[0005]

In order to achieve such an object, the invention of claim 1 is to write a high-priority cell arriving later, and when a low-priority cell arriving before that remains. Indicates that the remaining low-priority cells are processed as invalid and are not read. The invention according to claim 2 is a head timing detection unit (Table 3) for detecting the head timing of a high priority cell that arrives after a low priority cell.
a, control circuit 3b), and an invalid cell processing unit (phase difference sending circuit 9, tables 3a and 3c, control circuit 3) for invalidating the low-priority cells that arrived before the start timing.
b, a write control unit 7) and a selective read unit (control circuit 3b, read control unit 10) for selecting and reading the low-priority cells that have not been invalidated during low-priority cell reading.

[0006]

When the start timing of the high priority cell that arrives after the low priority cell is detected, the low priority cells that have arrived before that are invalidated, and the low priority cells that have not been invalidated at the time of reading the low priority cells are selected. Read.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, prior to the transfer of information, the calling terminal has a peak bandwidth and the guaranteed bandwidth that must be surely transmitted even when the network is in a congested state. The network secures a high-priority buffer for the calling terminal up to this guaranteed bandwidth by the capacity corresponding to the request, and lowers the bandwidth up to the peak rate exceeding that bandwidth in consideration of the statistical multiplexing effect. Allocate a preferred buffer. Furthermore, the information transmitted here is assumed to be one in which low-priority cells may be discarded, such as moving images,
In the calling terminal, the information in one frame is prioritized in the order of, for example, frame synchronization information, skeleton information, color information, etc., and ATM cells are formed in the order of higher priority information, so that high priority cells are placed on the path. Blocks of low priority cells and blocks of low priority cells occur alternately. At this time, AT
In the cell header of M, two types of priority identifiers using, for example, a CLP (cell loss priority) field according to the priority order of the information and the information unit, and AAL5
An identifier in PDU (protocol data unit) unit, which is composed of an identifier in packet unit using PT (payload type field) in (ATM adaptation layer), is added.

In FIG. 1, when a plurality of paths n are respectively connected to the identification circuits 1-1 to 1-n corresponding to the paths and the calling terminal connected to the paths makes a call,
For example, when there is a call request from the calling terminal, the call admission control unit 2 detects the call request, notifies the calling terminal of the VPI value and the VCI value, and at the same time, the VPI of the table 3a in the low priority buffer queue management unit 3 is detected. , "1" is written in the call acceptance flag at the position corresponding to the VCI compatible address as the information allowing the call. The table 3a is adapted to write information in the format of FIG. 2 (a), and although the writing content will be described later, the table 3a is used to detect the head position of the high priority cell that arrives after the low priority cell. It
The call acceptance flag is written with "0" when the call is released.

The cell from the calling terminal is, for example, the identification circuit 1
When it reaches -1, it refers to the header of the cell and
The control unit 3b of the low priority buffer queue management unit 3 is notified of the I, VCI value, CLP value, and PT value. The control unit 3b detects an address corresponding to the VPI and VCI values in the table 3a and checks whether the call admission flag corresponding to the address is set to "1". When this flag is set to "1", the CLP is controlled by the control circuit 3b.
The value and the PT value are written in the table 3a. At this time C
The LP value is directly written in the CLP flag in FIG. On the other hand, in ALL5, a block is composed of two or more blocks and is transmitted, but the ongoing cell of the block is P
It is determined that the T value is “000” or “010.” At this time, “0” is written in the PT flag of FIG. The PT value of the cell at the end of the block is determined to be "001" or "011". At this time, "1" is written in the PT flag. However, if the call acceptance flag written in the address corresponding to the VPI and VCI values is "0", it means that the call is not permitted and the arriving cell is discarded.

When the CLP value is "0", the cell is a high priority cell. Therefore, the control circuit 3b of the low priority buffer queue management unit 3 writes the arrived cell into the high priority buffer 4 so that the high priority buffer is used. The writing control unit 5 of FIG. C
When the LP value is "1", the cell is a low priority cell, so the control circuit 3b controls the write control section 7 for the low priority buffer to write the arrived cell in the low priority buffer 6. When writing to the low-priority buffer 6, the write VPI, VC is written in the table 3b of the low-priority buffer queue management unit 3.
The I value and the cell writing start address of the low priority buffer 6 are written. Information is written in the table 3b in the form of FIG. 2B, but the VPI and VCI values of the low-priority cells written in the low-priority buffer, and the write start address,
Information for determining whether the written cell is valid or invalid is written at the address indicated by the write pointer. The operation of writing valid or invalid information will be described later.

Similar processing is performed for cells that arrive one after another, but the control circuit 3b of the low-priority buffer queue management unit 3 uses the CLP flag and PT flag of the table 3a and the CLP and PT values of the arriving cells. And refer to C
The condition of LP flag = 1 and the condition of PT flag 1 is satisfied, and the reception CLP value = 0 and the reception PT value = 0.
When all the conditions of are satisfied, the table 3
The CLP flag and PT flag of a are updated, and the invalid cell determination described later is performed. . When the above-mentioned relationship between the CLP value and the PT value is not established, the CLP flag and the PT flag of the table 3a are only updated according to the received value without determining the invalid cell.

The cell information written in the high-priority buffer 4 is read in the order in which they are written under the control of the read control unit 8 of the high-priority buffer. The phase difference detection circuit 9 of the high-priority buffer refers to the contents of the write control circuit 5 and the contents of the read control circuit 8, and when they match, it means that all the contents of the high-priority buffer 4 have been read. Since the content of the low-priority buffer 6 can be read after that time, the phase difference detection circuit 9 notifies the control circuit 3b of the low-priority buffer queue management unit 3 to that effect. As a result, the control circuit 3b causes the read control unit 10 for reading the low priority buffer.
Is controlled to read the information in the low-priority buffer 6.

From the header of the arriving cell, the condition of CLP flag = 1 and PT flag 1 is satisfied, and reception CL
When all the conditions of P value = 0 and reception PT value = 0 are satisfied, the control circuit 3b updates the CLP flag and the PT flag of the table 3a according to the reception value as described above. Thus, the invalid cell is also determined. This is the write VPI, V of the table 3c at that time.
If the CI value is registered, it is determined that the cell is an invalid cell, and the discard flag of the table 3c is set to "1".

As described above, in AAL5, this processing means that when PT is 000, that is, PT flag = 0, it is not the end of the frame, and when it is 001, that is, PT flag = 1 is the end of the frame. It makes use of what is meant to mean. Therefore, if the end of the frame is detected and the end is for a low priority cell and the next cell to arrive is a high priority cell, it is the beginning of the high priority cell. If there is a low-priority cell that has not been read at that time, it is already invalid, so it is determined to be an invalid cell, and the discard flag of the table 3c is set to "1".

This will be described in more detail as follows. In this example, it is assumed that cells sequentially arrive at the input path 1 and the input path 2 as shown in FIG. 3, are processed by the ATM relay node, and are sent to the output path. Then, it is assumed that the call admission processing has been completed for all the paths and the calling is permitted, and the VPI and VCI compatible addresses of the path 1 are as shown in FIG.
2 and the address corresponding to the VPI and VCI of the path 2 is the symbol "e" in FIG.

FIG. 4 (a) shows a part of the information of the table 3a written each time a cell arrives, in which the VPI and VCI addresses are "H" and "H".
At time t1 shown in FIG. 3, the A1 cell of the path 1 arrives, but since this is a high priority cell, the CLP value is “0” indicating the high priority cell and the time of the CLP flag in FIG. 4 (a). At t1, it is written in the table 3a. Originally, the table 3a is rewritten with the contents each time the cell arrives at each time in FIG. 2, but since the explanation is made following the time conversion here, the CLP flag, P
The T flag and the cell symbols are also shown in the order in which they arrive.

At time t1 in FIG. 3, cells A1 and B1 arrive, but cell A1 is at the end of the block, that is, symbol A.
It is not the end of the high priority cell set that follows 1, A1 '. Since the CLP value representing the high-priority cell is "0", "0" is written in the portion corresponding to the cell A1 at the time t1 in the CLP flag of FIG. 4 (a). Further, since it is not the end of the block, the PT flag indicating that is "0", and "0" is written in the portion corresponding to the cell A1 at time t1 in the PT flag. Next, at the same time t1
Since the cell B1 has arrived at the input path 2, CL indicating that it is a high priority cell is similarly present in the portion of "e" which is the VPI / VCI corresponding address of FIG. 4A.
P = 0, PT = 0 indicating that it is not the end of the block is written. That is, "0" is written in the portion corresponding to the cell B1 at time t1 in the CLP flag of FIG. 4A, and "0" is written in the position of the cell B1 at time t1 in the PT flag. At time t2 in FIG.
1 ′ and B1 ′ arrive, but since this is a high priority cell, CLP = 0. Further, since it is the end of the block, that is, the end of the set of the cell A and the cell B, PT = 1.
Therefore, “0” is written in the position of the cell A1 ′ and “0” is written in the position of the cell B1 ′ at the time t2 of the CLP flag in FIG. Also, since this cell is the end of the block of high priority cells, PT = 1. Therefore, “1” is written in the position of the cell A1 ′ at the time t2 of the PT flag, and “1” is written in the position of the cell B1 ′.

At time t3 in FIG. 3, cells a1 and b1 arrive, and since these are low priority cells, CLP flag = 1.
Since it is not the end of the block, PT = 0. Therefore, the cell a at the time t3 of the CLP flag in FIG.
"1" is written in the position of 1, and "1" is written in the position of the cell b1. Further, the cell a1 at the time t3 of the PT flag
"0" is written in the position of, and "0" is written in the position of the cell b1. Similarly at time t4, cells a1 'and b1' are low priority cells, so CLP = 1, and P is because it is at the end of the block.
T = 1. Then, as shown in FIG. 4A, “1” is written in the position of the cell a1 ′ and “1” is written in the position of the cell b2 ′ at the time t4 of the CLP flag,
In addition, “1” is written in the position of the cell a1 ′ and “1” is written in the position of the cell b1 ′ at the time t4 of the PT flag.
Thereafter, information is similarly written in the table 3a.

When a low-priority cell is written in the low-priority buffer 6, the write VC of the information is also written in the table 3c.
The I and VPI values, the low-priority cell write start address, and the discard flag are written as shown in FIG. Write V
As the PI and VCI values, the VPI and VCI values of the arrived cell are written as they are at the address indicated by the write pointer. In the description of FIG. 4A, the addresses “HA” and “HO” are written at the same time, so that FIG.
Also, each time a low priority cell arrives, the VPI and VCI values are
“Ha” and “ho” are written. However, in FIG. 4B, for easy understanding, information about which cell the write value corresponds to is also described. Also, the write start address is described as "1" corresponding to the cell a1, and the address is incremented by "1" each time writing is performed.

Since reading is performed one timing behind writing, as shown in FIG. 3, A1, B1, A1 'and B1' are read in the order in which the high priority cells are written. Since the high-priority cells written in the high-priority buffer 4 in FIG. 1 are read before the low-priority cells, all the information in the high-priority buffer 4 is eventually read. The phase difference detection circuit 9 detects this and notifies it to the low priority buffer queue management unit 3, so that the low priority buffer queue management unit 3 starts reading the cell a1 of the low priority buffer 6 from time t6. As described above, when the conditions of CLP = 1 and PT = 1 are satisfied from the header of the arrived cell and the conditions of the reception CLP value = 0 and the reception PT value = 0 are satisfied, the writing of the table 3c is performed. If the VPI and VCI values are registered, it is determined as an invalid cell, and the table 3c
Is to be set to "1".
In the example of FIG. 4A, the condition of CLP = 1 and PT = 1 is satisfied at the timing of time t4. Then, at that time, the condition of the reception CLP value = 0 and the reception PT value = 0 is satisfied at the timing of time t5. That is, when the head cell of the high-priority cell arriving next to the low-priority cell is received, the discard condition of the low-priority cell of the path is determined. This determination is made for the cell between the read pointer and the write pointer shown in FIG. In FIG. 4, at time t5, the discard determination processing is performed on the path 1 and the path 2, and the cells a1, b1, a1 ′ are displayed.
Since the write VPI and VCI values have been written up to b1 ′ at this time, the discard flag = 1 is set in that portion. In the example of FIG. 4B, the flag "1" is put in parentheses in the sense that the discard flag is set at the time of this judgment, not at the time of writing information.

After time t7, the high-priority cell A is also the same as described above.
2, B2, A2 ', B2' are sequentially read. Cell B
Since the contents of the high-priority buffer 4 are completely read when 2 ′ is read, the contents of the low-priority buffer are read at time t12. At time t9, the low priority cell a
2 and b2 have arrived, so at time t12 table 3
Although the cell c is read, the cell in which the discard flag is set is not read. Therefore, the cells from the address 1 to the address 4 in FIG. 4B are not read, and the low priority cells after the cell a2 at the address 5 are read.

Although read cells are sequentially described in the output path of FIG. 3, as can be seen from this figure, the high priority cells A2 and B2 are invalid after being read. The low-priority cells a1 'and b1' surrounded by an ellipse are not read out, and the low-priority cells a2 and b2 arriving later are read out when they are originally read out. in this way,
When a high-priority cell that arrives later is read, the low-priority cell that arrives earlier is invalid because there is no opportunity to use it even if it is read. Even if it is the read timing of the low priority cell, if the low priority cell that is still valid at that time is read without reading such an invalid low priority cell, the read time of the read low priority cell becomes It will never be later than necessary. Although a specific method is not shown in the above example, a cycling buffer is assumed as the low-priority buffer, and this control is used to read only the addresses occupied by invalid cells and count up the addresses. As a result, new cells can be written by that amount, and the low priority cells are less likely to overflow in the queue on the input side.

[0023]

As described above, the present invention does not read invalid low-priority cells at the read timing of the low-priority buffer but only valid ones. By adding the delay of minutes, it is possible to prevent the state in which other valid cells are further delayed,
It has an effect that the transfer quality of ATM can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a structure of tables 3a and 3c.

FIG. 3 is a diagram showing a relationship between an input cell and an output cell.

FIG. 4 is a diagram showing an example of contents written in tables 3a and 3c.

FIG. 5 is a diagram showing a conventional read example.

[Description of Reference Signs] 1-1 to 1-n ... Identification circuit, 2 ... Call admission control unit, 3 ... Low-priority buffer queue management unit, 3a, 3c ... Table, 3
b ... Control circuit, 4 ... High priority buffer, 5, 7 ... Write control unit, 6 ... Low priority buffer, 8, 10 ... Read control unit, 9 ...
Phase difference detection circuit.

Claims (2)

[Claims] 1. A cell priority processing apparatus for transmitting a low priority cell after transmission of all high priority cells is completed at a relay node which processes a path in which high priority cells and low priority cells alternately arrive on the same path. , When writing a high priority cell that arrives later on the same path, if a low priority cell that arrives earlier than that remains, the remaining low priority cells are treated as invalid and are not read. Cell priority processing device. 2. A low priority cell is transmitted when a low priority cell is transmitted after transmission of all high priority cells is completed at a relay node which processes a path in which high priority cells and low priority cells alternately arrive on the same path. In a cell priority processing apparatus that selects and sends only valid cells, a head timing detection unit that detects the head timing of a high priority cell that arrives after a low priority cell, and a low priority that arrived before the head timing. A cell priority processing apparatus comprising: an invalid cell processing unit that invalidates a cell; and a selective reading unit that selects and reads a low priority cell that has not been invalidated when reading a low priority cell.