JPH11145494A - Thin-film silicon photoelectric converting device and manufacture thereof - Google Patents

Thin-film silicon photoelectric converting device and manufacture thereof

Info

Publication number
JPH11145494A
JPH11145494A JP9325417A JP32541797A JPH11145494A JP H11145494 A JPH11145494 A JP H11145494A JP 9325417 A JP9325417 A JP 9325417A JP 32541797 A JP32541797 A JP 32541797A JP H11145494 A JPH11145494 A JP H11145494A
Authority
JP
Japan
Prior art keywords
photoelectric conversion
film
thin
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9325417A
Other languages
Japanese (ja)
Other versions
JP4098386B2 (en
Inventor
Masashi Yoshimi
雅士 吉見
Kenji Yamamoto
憲治 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanegafuchi Chemical Industry Co Ltd
Original Assignee
Kanegafuchi Chemical Industry Co Ltd
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Filing date
Publication date
Application filed by Kanegafuchi Chemical Industry Co Ltd filed Critical Kanegafuchi Chemical Industry Co Ltd
Priority to JP32541797A priority Critical patent/JP4098386B2/en
Publication of JPH11145494A publication Critical patent/JPH11145494A/en
Application granted granted Critical
Publication of JP4098386B2 publication Critical patent/JP4098386B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film crystalline silicon photoelectric converting device, wherein an excellent semiconductor junction can be formed and photoelectric converting characteristics can be improved. SOLUTION: A thin-film silicon photoelectric converting device contains a thin-film crystalline silicon photoelectric converting layer 3 and a microscopic crystal silicon conductive thin film layer 4 containing a conductivity determinant impurity atom of 0.01 atomic % or more, formed by coming into contact with the photoelectric converting layer through a semiconductor junction interface. The rate of interfacial region having an angle of deviation of 15 deg. or less of the equivalent crystal orientational axis corresponding to both sides of junction interface is in the range of 5 to 50%.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は薄膜光電変換装置に
関し、特に、低コストで製造し得る薄膜結晶質シリコン
系光電変換装置の性能改善に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film photoelectric conversion device, and more particularly to improvement in performance of a thin-film crystalline silicon-based photoelectric conversion device which can be manufactured at low cost.

【0002】なお、本明細書において、「結晶質シリコ
ン」と「微結晶シリコン」の用語は部分的にアモルファ
スシリコンを含むものをも意味するものとする。
[0002] In this specification, the terms "crystalline silicon" and "microcrystalline silicon" also mean those partially containing amorphous silicon.

【0003】[0003]

【従来の技術】太陽電池等の光電変換装置をはじめとす
る半導体デバイスに関する最も重要な技術の1つとし
て、半導体接合形成プロセスがある。光電変換装置にお
いては、特に光電変換層の光入射側に形成される半導体
接合の特性がその装置の性能に直接的に大きな影響を及
ぼす。現在、バルク結晶シリコン系材料をベースにして
半導体接合を形成するために工業上広く用いられている
手法として、ドーパント原子の熱拡散やイオン注入、さ
らにはCVD法等の成膜プロセスによるエピタキシャル
成長法等がある。
2. Description of the Related Art One of the most important technologies relating to semiconductor devices such as a photoelectric conversion device such as a solar cell is a semiconductor junction forming process. In the photoelectric conversion device, particularly, the characteristics of a semiconductor junction formed on the light incident side of the photoelectric conversion layer have a large direct influence on the performance of the device. At present, methods widely used in industry for forming a semiconductor junction based on a bulk crystalline silicon-based material include thermal diffusion of dopant atoms, ion implantation, and an epitaxial growth method by a film forming process such as a CVD method. There is.

【0004】一方、低温において低コストで製造し得る
薄膜光電変換装置の1つであるアモルファスシリコン系
光電変換装置は、プラズマCVD法によって一導電型
層、光電変換層および逆導電型層が順次堆積されてなる
pin接合を含んでいる。この場合、光電変換層よりも
エネルギバンドギャップの大きい材料を光入射側の導電
型層として堆積させて接合形成を行なうことによって、
拡散電位の増大や光吸収損失の低減化のようないわゆる
ヘテロ接合窓効果による光電変換効率の向上を図ること
ができる。そのような窓層のための材料として、代表的
なものに、アモルファスシリコンカーバイドや微結晶シ
リコンなどがある。
On the other hand, an amorphous silicon photoelectric conversion device, which is one of the thin film photoelectric conversion devices which can be manufactured at low temperature at low cost, has a layer of one conductivity type, a photoelectric conversion layer and a layer of opposite conductivity type sequentially deposited by a plasma CVD method. It includes a pin junction. In this case, a material having a larger energy band gap than that of the photoelectric conversion layer is deposited as a conductive type layer on the light incident side to form a junction.
The photoelectric conversion efficiency can be improved by a so-called heterojunction window effect such as an increase in diffusion potential and a reduction in light absorption loss. Representative materials for such a window layer include amorphous silicon carbide and microcrystalline silicon.

【0005】特開平8−116080においては、光入
射側導電型層に用いる微結晶シリコンを150℃以下の
低温で堆積させれば、従来の150℃以上の条件やアモ
ルファスシリコンカーバイドを用いた場合よりも拡散電
位が大きくなって、光電変換効率も向上する旨が報告さ
れている。しかし、この場合に接合形成の対象となる光
電変換層はアモルファス膜であって、より具体的にはア
モルファスシリコン膜の光電変換層上に導電型微結晶シ
リコン層を堆積させているものであり、接合界面の欠陥
を積極的に低減しようという意図は全く存在していな
い。また、もともと高い欠陥密度を有するアモルファス
光電変換層との組合せでは、接合界面特性の大幅な改善
は実質的に困難である。
In Japanese Patent Application Laid-Open No. Hei 8-116080, if microcrystalline silicon used for the light-incident side conductive type layer is deposited at a low temperature of 150 ° C. or less, the conventional condition of 150 ° C. or more or amorphous silicon carbide is used. It has also been reported that the diffusion potential increases and the photoelectric conversion efficiency also increases. However, in this case, the photoelectric conversion layer to be bonded is an amorphous film, and more specifically, a conductive microcrystalline silicon layer is deposited on the amorphous silicon film photoelectric conversion layer, There is no intention to actively reduce defects at the bonding interface. Also, in combination with an amorphous photoelectric conversion layer having an originally high defect density, it is substantially difficult to greatly improve the junction interface characteristics.

【0006】近年、薄膜多結晶シリコン太陽電池に代表
されるように、低コストでかつ高性能の薄膜光電変換装
置の実用化を目指した研究開発が行なわれている。低コ
スト化の実現のためには、安価なガラス,金属,有機フ
ィルム等の基板が使用可能で薄膜の大面積化が容易であ
りかつ成熟された簡易な低温成膜プロセスを導入するこ
とが望ましい。このとき、デバイス構成材料の中心とな
る光電変換層の低温形成もさることながら、同時に、半
導体接合形成プロセスの低温化も望まれるので、前述の
ようなバルク結晶シリコン系材料において用いられる熱
拡散等の高温プロセスは用いることができない。
[0006] In recent years, as represented by a thin-film polycrystalline silicon solar cell, research and development aiming at practical use of a low-cost and high-performance thin-film photoelectric conversion device have been conducted. In order to realize cost reduction, it is desirable to use a simple low-temperature film forming process that can use inexpensive substrates such as glass, metal, and organic films, can easily increase the area of thin films, and is mature. . At this time, not only the low temperature formation of the photoelectric conversion layer, which is the center of the device constituent material, but also the low temperature of the semiconductor junction formation process is desired. High temperature process cannot be used.

【0007】したがって、薄膜結晶質シリコン系光電変
換装置においても、アモルファスシリコン系光電変換装
置と同様に、プラズマCVD法により低温で導電型層を
形成することによって簡便に半導体接合を形成する多く
の試みが、たとえば特開平3−218683等において
行なわれている。この場合にも、堆積される導電型層の
材料にはアモルファスシリコン,微結晶シリコン,また
はこれらの合金系材料が用いられ、いずれも結晶シリコ
ンと比べて大きなエネルギバンドギャップを有している
ので、やはり光電変換装置におけるヘテロ接合窓効果に
よる光電変換効率の向上が期待される。
Accordingly, many attempts to form a semiconductor junction easily by forming a conductive layer at a low temperature by a plasma CVD method in a thin-film crystalline silicon-based photoelectric conversion device, similarly to an amorphous silicon-based photoelectric conversion device. This is performed, for example, in JP-A-3-218683. Also in this case, amorphous silicon, microcrystalline silicon, or an alloy thereof is used as the material of the conductive type layer to be deposited, and all have a large energy band gap as compared with crystalline silicon. Again, improvement in photoelectric conversion efficiency due to the heterojunction window effect in the photoelectric conversion device is expected.

【0008】[0008]

【発明が解決しようとする課題】他方、このような低温
形成された導電型材料と下地の結晶質シリコン系材料と
の接合界面においては、上述のような熱拡散等の確立さ
れた高温プロセスによる接合形成の場合と比べれば、一
般的に接合界面近傍に多く存在する結晶粒界や格子不整
合等に基づいて、エネルギ準位に多くの欠陥準位が存在
する。このような問題が光電変換特性を制限している1
つの要因となっているにもかかわらず、それを解決する
ためのアプローチが今までに試みられていなかった。
On the other hand, at the bonding interface between the conductive type material formed at such a low temperature and the underlying crystalline silicon-based material, an established high-temperature process such as the above-mentioned thermal diffusion is used. Compared to the case of forming a junction, there are generally more defect levels in the energy level based on crystal grain boundaries, lattice mismatch, etc., which generally exist near the junction interface. Such a problem limits the photoelectric conversion characteristics 1
Despite these factors, no approach has been attempted to solve them.

【0009】このような観点から、本発明の主要な目的
は、低温で形成される薄膜結晶質シリコン系光電変換装
置における良好な半導体接合特性と光電変換特性を得る
ことであり、そのためにさらに、導電型層と光電変換層
との界面における結晶粒界密度が低減された欠陥の少な
い高品質の半導体接合の形成を低温における簡便なプロ
セスにて行ない得る方法を提供することにある。
From such a viewpoint, a main object of the present invention is to obtain good semiconductor junction characteristics and photoelectric conversion characteristics in a thin-film crystalline silicon-based photoelectric conversion device formed at a low temperature. It is an object of the present invention to provide a method capable of forming a high-quality semiconductor junction with a reduced number of crystal grain boundaries at an interface between a conductive layer and a photoelectric conversion layer and having few defects by a simple process at a low temperature.

【0010】[0010]

【課題を解決するための手段】本発明の1つの態様によ
る薄膜シリコン系光電変換装置は、薄膜結晶質シリコン
系光電変換層と;半導体接合界面を介してその光電変換
層に接して形成されていて0.01原子%以上の導電型
決定不純物原子を含む微結晶シリコン系導電型薄膜層と
を含み;半導体接合界面の両側において対応する等価な
結晶配向軸の少なくとも1つのずれ角が15度以下であ
る界面領域の割合が5%以上で50%以下の範囲内にあ
ることを特徴としている。
A thin-film silicon-based photoelectric conversion device according to one embodiment of the present invention is formed in contact with a thin-film crystalline silicon-based photoelectric conversion layer and a photoelectric conversion layer via a semiconductor junction interface. A microcrystalline silicon-based conductive type thin film layer containing 0.01 atomic% or more of a conductive type determining impurity atom; at least one misalignment angle of a corresponding equivalent crystal orientation axis on both sides of a semiconductor junction interface is 15 degrees or less. The ratio of the interface region is within a range of 5% or more and 50% or less.

【0011】本発明のもう1つの態様による薄膜シリコ
ン系光電変換装置の製造方法は、プラズマCVD法によ
って20℃以上で200℃未満の範囲内の下地温度のも
とで光電変換層上に導電型薄膜層を堆積することを特徴
としている。
According to another aspect of the present invention, there is provided a method of manufacturing a thin film silicon-based photoelectric conversion device, wherein a conductive type is formed on a photoelectric conversion layer by a plasma CVD method at a base temperature in a range of 20 ° C. or more and less than 200 ° C. The method is characterized in that a thin film layer is deposited.

【0012】[0012]

【発明の実施の形態】図1において、本発明の実施の形
態の一例として適用し得る薄膜結晶質シリコン系光電変
換装置の基本的構造が模式的な分解斜視図で示されてい
る。この光電変換装置において、基板1としては、金
属,有機フィルム,または低融点の安価なガラス等が用
いられ得る。下地電極2は、たとえば蒸着法やスパッタ
法で形成されるAg等の金属電極やZnO等の透明導電
酸化膜,プラズマCVD法で成膜された高濃度ドープの
アモルファスシリコン層をパルスレーザアニール処理に
よって多結晶化して得られる低抵抗シリコン膜,プラズ
マCVD法で形成される微結晶シリコン系導電型薄膜等
のいずれか、またはこれらのうちの複数層の組合せによ
って構成され得る。
FIG. 1 is a schematic exploded perspective view showing a basic structure of a thin-film crystalline silicon-based photoelectric conversion device applicable as an example of an embodiment of the present invention. In this photoelectric conversion device, as the substrate 1, a metal, an organic film, a low-melting-point inexpensive glass, or the like can be used. The base electrode 2 is formed, for example, by subjecting a metal electrode such as Ag formed by vapor deposition or sputtering, a transparent conductive oxide film such as ZnO, or a highly doped amorphous silicon layer formed by plasma CVD to pulse laser annealing. Any of a low-resistance silicon film obtained by polycrystallization, a microcrystalline silicon-based conductive thin film formed by a plasma CVD method, or the like, or a combination of a plurality of these layers can be used.

【0013】薄膜結晶質シリコン系光電変換層3は、上
述のような安価な基板が使用し得るように、550℃以
下の比較的低温度にてプラズマCVD法によって形成さ
れる。成膜用の主原料ガスとしては、モノシラン等の水
素化シラン系ガスはもちろんのこと、四フッ化ケイ素や
ジクロルシラン等のハロゲン系ガスも用いられ得る。こ
れらの主原料ガスに加えて、水素ガスやアルゴンガスが
希釈ガスやキャリアガスとして混合されて用いられる。
光電変換層3として堆積される膜は、ノンドープの真性
半導体の薄膜多結晶シリコンや体積結晶化分率が80%
以上の微結晶シリコン、もしくはこれらと同様のシリコ
ン系合金材料、またはそれらに微量の不純物が含まれて
いて弱いp型もしくはn型で光電変換機能を十分備えて
いる薄膜シリコン系材料である。このような光電変換層
3は低温度条件にて形成されるので比較的多くの水素原
子を含み、その膜中水素含有量は0.1原子%以上で3
0原子%以下の範囲内にある。また、その膜厚は好まし
くは0.5〜20μmの範囲内に設定され、これは薄膜
シリコン系光電変換層3として必要かつ十分な膜厚であ
る。なお、光電変換層3に含まれる結晶粒の多くは、下
地電極2から上方に柱状に延びて成長している。そし
て、それらの多くの結晶粒は膜面に平行に(110)の
優先結晶配向面を有し、X線回折で求めた(220)回
折ピークに対する(111)回折ピークの強度比が0.
2以下である。
The thin-film crystalline silicon-based photoelectric conversion layer 3 is formed by a plasma CVD method at a relatively low temperature of 550 ° C. or less so that an inexpensive substrate as described above can be used. As a main source gas for film formation, not only a hydrogenated silane-based gas such as monosilane, but also a halogen-based gas such as silicon tetrafluoride or dichlorosilane can be used. In addition to these main source gases, a hydrogen gas or an argon gas is mixed and used as a diluent gas or a carrier gas.
The film deposited as the photoelectric conversion layer 3 may be a non-doped intrinsic semiconductor thin film polycrystalline silicon or a volume crystallization fraction of 80%.
The above microcrystalline silicon, or a silicon alloy material similar to these, or a thin p-type or n-type thin film silicon material which contains a small amount of impurities and has a sufficient photoelectric conversion function. Since such a photoelectric conversion layer 3 is formed under a low temperature condition, it contains a relatively large amount of hydrogen atoms.
It is in the range of 0 atomic% or less. The film thickness is preferably set in the range of 0.5 to 20 μm, which is a necessary and sufficient film thickness for the thin-film silicon-based photoelectric conversion layer 3. Note that many of the crystal grains included in the photoelectric conversion layer 3 extend upwardly from the base electrode 2 in a columnar shape. Many of these crystal grains have a preferential crystal orientation plane of (110) parallel to the film plane, and the intensity ratio of the (111) diffraction peak to the (220) diffraction peak determined by X-ray diffraction is 0.1%.
2 or less.

【0014】光電変換層3の堆積に続いて、光7を受入
れる窓層4として、体積結晶化分率20%以上の微結晶
シリコン系導電型薄膜層がプラズマCVD法にて堆積さ
れる。微結晶シリコン系導電型薄膜層4としては、たと
えば導電型決定不純物原子であるボロン原子が0.01
原子%以上ドープされたp型微結晶シリコン、またはリ
ン原子が0.01原子%以上ドープされたn型微結晶シ
リコンなどが用いられ得る。しかし、これらの条件は限
定的なものではなく、たとえば導電型決定不純物原子と
しては、p型微結晶シリコンを得るためにアルミニウム
を用いてもよい。また、窓層4として、微結晶シリコン
膜よりもさらに大きな光学バンドギャップを有する微結
晶シリコンカーバイド等の合金材料を用いてもよい。
Subsequent to the deposition of the photoelectric conversion layer 3, a microcrystalline silicon-based conductive thin film layer having a volume crystallization fraction of 20% or more is deposited as a window layer 4 for receiving the light 7 by a plasma CVD method. As the microcrystalline silicon-based conductive type thin film layer 4, for example, boron atoms that are conductive type determining impurity atoms are 0.01%.
P-type microcrystalline silicon doped with at least atomic% or n-type microcrystalline silicon doped with at least 0.01 atomic% of phosphorus atoms can be used. However, these conditions are not limited, and for example, aluminum may be used as a conductivity type determining impurity atom to obtain p-type microcrystalline silicon. Further, as the window layer 4, an alloy material such as microcrystalline silicon carbide having an optical band gap larger than that of the microcrystalline silicon film may be used.

【0015】微結晶シリコン層4の成膜工程としては、
通常広く用いられているRFプラズマCVD法、その他
にECRプラズマCVD法、さらにはこれらの組合せな
どが用いられ得る。成膜用原料ガスとしては、モノシラ
ン等の水素化シラン系の他に、四フッ化硅素,ジクロル
シラン等のハロゲン系ガスも用いられ得る。また、ドー
パントガスには、たとえばジボランやホスフィン等が用
いられ得る。さらに、これらのガスに加えて、水素ガス
が混合されて用いられる。
The film forming process of the microcrystalline silicon layer 4 includes:
An RF plasma CVD method generally used widely, an ECR plasma CVD method, a combination thereof, or the like may be used. As a source gas for film formation, a halogenated gas such as silicon tetrafluoride or dichlorosilane may be used in addition to a hydrogenated silane gas such as monosilane. Further, for example, diborane or phosphine may be used as the dopant gas. Further, in addition to these gases, a hydrogen gas is mixed and used.

【0016】RFプラズマCVD法によるp型微結晶シ
リコンの窓層4の場合の一例として、より具体的に説明
すれば、基板温度は室温から200℃未満の範囲内に設
定され、微結晶シリコンの形成温度としては従来の通例
より比較的低温の条件にされる。また、反応室内圧力は
0.1〜2.0Torrの範囲内にあり、RFパワーは
10〜500mV/cm2 の範囲内にある。原料ガスに
はシランを用いて、ドーピングガスにはジボランを用
い、このときのシランに対するジボランガスの混合率は
好ましくは0.02〜10%の範囲内にあり、より好ま
しくは0.1〜5%の範囲内にある。これに加えて、シ
ランガスの10倍以上の水素ガスが混合される。こうし
て形成される微結晶シリコン層4の膜厚は、好ましくは
3〜100nmの範囲内にあり、より好ましくは5〜5
0nmの範囲内にある。
More specifically, as an example of the window layer 4 of p-type microcrystalline silicon formed by RF plasma CVD, the substrate temperature is set in a range from room temperature to less than 200 ° C. The forming temperature is set at a relatively lower temperature than in the conventional case. The pressure in the reaction chamber is in the range of 0.1 to 2.0 Torr, and the RF power is in the range of 10 to 500 mV / cm 2 . Silane is used as a source gas, and diborane is used as a doping gas. At this time, the mixing ratio of the diborane gas to the silane is preferably in the range of 0.02 to 10%, more preferably 0.1 to 5%. Within the range. In addition, a hydrogen gas 10 times or more the silane gas is mixed. The thickness of the microcrystalline silicon layer 4 thus formed is preferably in the range of 3 to 100 nm, more preferably 5 to 5 nm.
It is in the range of 0 nm.

【0017】このような形成条件にてガラス基板上に直
接堆積されたp型微結晶シリコン膜の暗導電率と光学バ
ンドギャップは、それぞれ30S/cm以下と2.0e
V以上にすることができ、十分な導電性とヘテロ接合形
成のための広いバンドギャップを兼ね備えたものとし得
る。この場合の暗導電率は、微結晶シリコン膜上に蒸着
されたコプレーナ型の金属電極間の抵抗値とそのシリコ
ン膜の厚さとから求められた。また、光学バンドギャッ
プEOPT は、光吸収係数αの光エネルギhν依存性に基
づくTaucの式 (αhν)1/2 ∝hν−EOPT を用いて求められた。他方、赤外吸収スペクトルから定
量的に求められる水素原子含有量は10原子%以上で2
5原子%以下の範囲内にすることができ、低温で成膜さ
れているために膜中に多量の水素原子を含んでいるが、
この水素の存在によって、微結晶膜中の結晶粒界パッシ
ベーションとワイドバンドギャップ化の効果が得られ
る。ここで示した種々の物性値および膜組成は、ガラス
基板上に直接堆積された微結晶シリコン膜に関するもの
であるので、図1に示されたような実際の光電変換装置
における薄膜結晶質シリコン光電変換層3上に堆積され
た場合とは物性値の絶対値が多少異なるものと思われる
ものの、ほぼ類似した傾向を示すものと考えることがで
きる。
Under these conditions, the p-type microcrystalline silicon film directly deposited on the glass substrate has a dark conductivity of less than 30 S / cm and an optical band gap of 2.0 e.
V or more, and can have both sufficient conductivity and a wide band gap for forming a heterojunction. The dark conductivity in this case was determined from the resistance between the coplanar metal electrodes deposited on the microcrystalline silicon film and the thickness of the silicon film. The optical band gap E OPT is obtained by using the equation (αhν) 1/2 αhν-E OPT of Tauc based on the light energy hν dependency of the light absorption coefficient alpha. On the other hand, the hydrogen atom content quantitatively determined from the infrared absorption spectrum
It can be within the range of 5 atomic% or less, and contains a large amount of hydrogen atoms in the film because it is formed at a low temperature.
Due to the presence of hydrogen, the effects of passivation at the crystal grain boundaries in the microcrystalline film and widening the band gap can be obtained. Since the various physical property values and film compositions shown here relate to a microcrystalline silicon film directly deposited on a glass substrate, a thin film crystalline silicon photoelectric converter in an actual photoelectric conversion device as shown in FIG. Although it is considered that the absolute values of the physical properties are slightly different from those in the case of being deposited on the conversion layer 3, it can be considered that they show almost similar tendencies.

【0018】図2は、上述のような製造条件で得られた
薄膜結晶質シリコン系光電変換装置の断面の透過電子顕
微鏡(TEM)写真の一例であって、光電変換層3と窓
側微結晶シリコン層4との界面近傍が拡大されて示され
た結晶格子像であり、白い点々がSi原子に対応してい
る。このTEM写真から明らかなように、これらの2つ
の層3,4の間に明確に構造上不連続な界面が存在しな
い部分がある。すなわち、下地の結晶質シリコン光電変
換層3の結晶配向性の影響を受けて微結晶シリコン導電
型膜4がエピタキシャル的に成長している部分が存在す
ることがわかる。このようなエピタキシャル的な成長に
より、接合界面における格子不整合等による欠陥準位が
減少する。また、窓側微結晶シリコン層4が低温条件の
もとで堆積されるので、プラズマ中に存在するイオン等
のエネルギ粒子による堆積膜表面近傍へのダメージが低
減される効果も重畳され、より良好な界面特性を有する
半導体接合が形成される。このような接合界面特性の改
善は界面近傍でのキャリアの再結合の低減等に直接的に
寄与するので、薄膜結晶質シリコン系光電変換装置にお
いて高い光電変換効率を得ることが可能となる。
FIG. 2 is an example of a transmission electron microscope (TEM) photograph of a cross section of the thin-film crystalline silicon-based photoelectric conversion device obtained under the above-described manufacturing conditions, and shows the photoelectric conversion layer 3 and the window-side microcrystalline silicon. The crystal lattice image in which the vicinity of the interface with the layer 4 is enlarged is shown, and white dots correspond to Si atoms. As is apparent from this TEM photograph, there is a portion where there is no clearly structurally discontinuous interface between these two layers 3 and 4. That is, it is understood that there is a portion where the microcrystalline silicon conductive type film 4 is epitaxially grown under the influence of the crystal orientation of the underlying crystalline silicon photoelectric conversion layer 3. Such epitaxial growth reduces defect levels due to lattice mismatch or the like at the junction interface. In addition, since the window-side microcrystalline silicon layer 4 is deposited under low-temperature conditions, the effect of reducing damage to the vicinity of the surface of the deposited film due to energetic particles such as ions present in the plasma is also superimposed, and a more favorable effect is obtained. A semiconductor junction having interface properties is formed. Such an improvement in the junction interface characteristics directly contributes to reduction of carrier recombination near the interface and the like, so that a high photoelectric conversion efficiency can be obtained in the thin-film crystalline silicon-based photoelectric conversion device.

【0019】ところで、堆積温度が比較的高くてこの接
合界面におけるエピタキシャル的成長が起こる領域が増
加すれば、成膜された微結晶シリコン導電型層4は光電
変換層3と同質の結晶膜に近づく。この場合、両者間の
接合は実質的にホモ接合に近くなって界面欠陥等は低減
されるが、比較的高い堆積温度の下では微結晶導電型層
4中の水素含有量の低減に伴ってバンドギャップが小さ
くなり、ヘテロ接合窓効果が低下するので、光電変換装
置における光電変換効率は逆に低下してしまう。このよ
うな理由により、接合界面におけるエピタキシャル的成
長が起こる領域の割合には好ましい範囲が存在する。本
発明では、微結晶シリコン導電型層4の堆積が200℃
未満の低温で行なわれるので、この接合界面の全領域に
おいてエピタキシャル的に成長するということはなく、
接合界面の両側において対応する等価な結晶配向軸の少
なくとも1つのずれ角が15度以下である界面領域の割
合が5%以上で50%以下の範囲内であることを特徴と
している。
If the deposition temperature is relatively high and the region where epitaxial growth occurs at the junction interface increases, the formed microcrystalline silicon conductive type layer 4 approaches a crystalline film of the same quality as the photoelectric conversion layer 3. . In this case, the junction between the two is substantially close to a homojunction and interface defects and the like are reduced. However, at a relatively high deposition temperature, the hydrogen content in the microcrystalline conductivity type layer 4 is reduced. Since the band gap is reduced and the heterojunction window effect is reduced, the photoelectric conversion efficiency of the photoelectric conversion device is reduced. For these reasons, there is a preferable range of the ratio of the region where the epitaxial growth occurs at the junction interface. In the present invention, the deposition of the microcrystalline silicon conductive type layer 4 is performed at 200 ° C.
Since it is performed at a low temperature of less than, it does not grow epitaxially in the entire region of the junction interface,
It is characterized in that the ratio of the interface region in which at least one corresponding crystal orientation axis has a shift angle of 15 degrees or less on both sides of the bonding interface is within a range of 5% or more and 50% or less.

【0020】[0020]

【実施例】以下において、図1を参照して、本発明の実
施例による光電変換装置と先行技術による比較例の光電
変換装置とについて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a photoelectric conversion device according to an embodiment of the present invention and a photoelectric conversion device of a comparative example according to the prior art will be described with reference to FIG.

【0021】(実施例1)ガラス基板1上に、下地電極
層2を形成するためにAg薄膜層、ZnO薄膜層および
リンドープされた厚さ30nmのn型多結晶シリコン層
を順次堆積し、次いで光電変換層3としてのノンドープ
薄膜多結晶シリコン層を3μmの厚さに堆積した後に、
p型微結晶シリコン膜4をRFプラズマCVD法により
15nmの厚さに成膜することによってnip接合が形
成された。さらに、上部電極5として80nm厚さのI
TO透明導電膜と電流取出しのためのAgの櫛型金属電
極6が形成された。
(Example 1) An Ag thin film layer, a ZnO thin film layer and a phosphorus-doped n-type polycrystalline silicon layer having a thickness of 30 nm are sequentially deposited on a glass substrate 1 to form a base electrode layer 2, and then, After depositing a non-doped thin-film polycrystalline silicon layer as the photoelectric conversion layer 3 to a thickness of 3 μm,
By forming the p-type microcrystalline silicon film 4 to a thickness of 15 nm by RF plasma CVD, a nip junction was formed. Further, an 80 nm thick I
The TO transparent conductive film and the Ag comb-shaped metal electrode 6 for current extraction were formed.

【0022】薄膜多結晶シリコン層3は400℃の成膜
温度において堆積され、4.5原子%の水素を含んでい
た。p型微結晶シリコン膜4は、従来より低い100℃
の成膜温度において堆積された。これと同一の成膜条件
でガラス基板上に直接200nmの厚さに堆積されたp
型微結晶シリコン膜において、暗導電率は0.68S/
cm、光学バンドギャップは2.1eV、そして含有水
素量は15原子%であった。また、断面TEM像観察に
よれば、薄膜多結晶シリコン層3とp型微結晶シリコン
膜4との接合界面において、エピタキシャル的成長が起
こっていると見られる界面領域、すなわち接合界面の両
側において対応する等価な結晶配向軸の少なくとも1つ
のずれ角が15度以下である界面領域の割合は40%で
あった。
The thin polycrystalline silicon layer 3 was deposited at a deposition temperature of 400 ° C. and contained 4.5 atomic% of hydrogen. The p-type microcrystalline silicon film 4 has a lower temperature of 100.degree.
At a film formation temperature of. Under the same film forming conditions, p deposited directly on a glass substrate to a thickness of 200 nm
In the type microcrystalline silicon film, the dark conductivity is 0.68 S /
cm, the optical band gap was 2.1 eV, and the hydrogen content was 15 atomic%. Also, according to the cross-sectional TEM image observation, at the junction interface between the thin-film polycrystalline silicon layer 3 and the p-type microcrystalline silicon film 4, the interface region where epitaxial growth appears to be occurring, that is, both sides of the junction interface The ratio of the interface region in which at least one shift angle of the equivalent crystal orientation axis is 15 degrees or less was 40%.

【0023】AM1.5の光で100mA/cm2 の光
量のもとにおけるこの実施例1の太陽電池の出力特性
は、その開放電圧が0.510volt、短絡電流が2
6.8mA/cm2 、曲線因子が73.5%、そして変
換効率が10.0%であった。
The output characteristics of the solar cell of Example 1 under the light intensity of 100 mA / cm 2 with the light of AM 1.5 are such that the open-circuit voltage is 0.510 volt and the short-circuit current is 2
6.8 mA / cm 2 , fill factor 73.5%, and conversion efficiency 10.0%.

【0024】(比較例1)p型微結晶シリコン膜4の成
膜温度が従来通りに200℃より高い250℃であった
ことを除いて、実施例1と同じ条件のもとに比較例1と
しての光電変換装置が作製された。これと同一の成膜条
件でガラス基板上に直接200nm厚さに堆積されたp
型微結晶シリコン膜においては、暗導電率が1.2S/
cm、光学バンドギャップが1.9eV、そして含有水
素量が8.5原子%であった。また、この比較例1にお
ける断面TEM像観察では、エピタキシャル的成長が起
こっている界面領域の割合は70%であった。
Comparative Example 1 Comparative Example 1 was performed under the same conditions as in Example 1 except that the film forming temperature of the p-type microcrystalline silicon film 4 was 250 ° C., which was higher than 200 ° C. as in the conventional case. Was manufactured. Under the same film forming conditions, p deposited directly on a glass substrate to a thickness of 200 nm
Type microcrystalline silicon film has a dark conductivity of 1.2 S /
cm, the optical band gap was 1.9 eV, and the hydrogen content was 8.5 atomic%. In the cross-sectional TEM image observation in Comparative Example 1, the ratio of the interface region where epitaxial growth had occurred was 70%.

【0025】AM1.5の光で100mA/cm2 の光
量のもとにおけるこの比較例1の太陽電池の出力特性
は、その開放電圧が0.460volt、短絡電流が2
4.3mA/cm2 、曲線因子が72.8%、そして変
換効率が8.1%であった。すなわち、この比較例1に
おいては、実施例1の場合に比べて、p型微結晶シリコ
ン膜4の光学バンドギャップが狭く、ホモ接合特性に近
いものであるために、変換効率が低くなっている。
The output characteristics of the solar cell of Comparative Example 1 under the light intensity of 100 mA / cm 2 with the light of AM 1.5 were as follows: the open-circuit voltage was 0.460 volt and the short-circuit current was 2
4.3 mA / cm 2 , fill factor 72.8%, and conversion efficiency 8.1%. In other words, in Comparative Example 1, the conversion efficiency is lower because the optical band gap of the p-type microcrystalline silicon film 4 is narrower and closer to the homojunction characteristics than in Example 1. .

【0026】(比較例2)p型微結晶シリコン膜4の成
膜温度がかなり低くて65℃であったことを除いて、実
施例1と同じ条件の下に比較例2としての光電変換装置
が作製された。これと同一の成膜条件でガラス基板上に
直接200nmの厚さに堆積されたp型微結晶シリコン
膜においては、暗導電率が低くて0.0021s/c
m、光学バンドギャップが1.95eV、そして含有水
素量が27.4原子%であった。断面TEM像観察によ
れば、薄膜多結晶シリコン層3とp型微結晶シリコン層
4との接合界面において、エピタキシャル的成長が起こ
っている領域の割合は非常に少なく、その界面領域の1
%以下であった。
(Comparative Example 2) A photoelectric conversion device as Comparative Example 2 under the same conditions as in Example 1 except that the film forming temperature of the p-type microcrystalline silicon film 4 was considerably low and was 65 ° C. Was produced. A p-type microcrystalline silicon film deposited directly on a glass substrate to a thickness of 200 nm under the same film forming conditions has a low dark conductivity of 0.0021 s / c.
m, the optical band gap was 1.95 eV, and the hydrogen content was 27.4 atomic%. According to the cross-sectional TEM image observation, at the junction interface between the thin-film polycrystalline silicon layer 3 and the p-type microcrystalline silicon layer 4, the ratio of the region where epitaxial growth has occurred is very small, and one of the interface regions
% Or less.

【0027】AM1.5の光で100mA/cm2 の光
量の下におけるこの比較例2の太陽電池の出力特性は、
その開放電圧が0.490volt、短絡電流密度が2
4.5mA/cm2 、曲線因子が64.9%、そして変
換効率が7.8%であった。すなわち、この比較例2に
おいてはp型微結晶シリコン膜4がほとんどアモルファ
ス膜に近いものであり、また光電変換層3とp型層4と
の間の接合界面の欠陥密度も高い等の理由により、実施
例1の場合に比べて変換効率が低くなっている。
The output characteristics of the solar cell of Comparative Example 2 under the light intensity of 100 mA / cm 2 with the light of AM 1.5 are as follows:
The open-circuit voltage is 0.490 volt and the short-circuit current density is 2
The charge factor was 4.5 mA / cm 2 , the fill factor was 64.9%, and the conversion efficiency was 7.8%. That is, in Comparative Example 2, the p-type microcrystalline silicon film 4 is almost similar to an amorphous film, and the defect density at the junction interface between the photoelectric conversion layer 3 and the p-type layer 4 is high. , The conversion efficiency is lower than that of the first embodiment.

【0028】(実施例2)上述の実施例1に示されたよ
うな低温での接合形成により光電変換効率が改善された
薄膜結晶質シリコン系太陽電池は、可視光領域で大きな
感度を有するアモルファスシリコン系太陽電池が追加積
層されたスタック型セルの作製のためにも好ましく用い
られ得る。本発明による薄膜結晶質シリコン太陽電池と
0.4μm厚さのノンドープ層を含むアモルファスシリ
コン太陽電池とを積層したタンデム型セルにおいて、実
施例1と同じ光照射条件の下で、13.0mA/cm2
の短絡電流,1.38voltの開放端電圧,および1
3.0%の変換効率が得られた。
(Embodiment 2) A thin-film crystalline silicon-based solar cell having improved photoelectric conversion efficiency by forming a junction at a low temperature as shown in the above-described embodiment 1 is an amorphous silicon solar cell having a large sensitivity in the visible light region. It can be preferably used also for producing a stack type cell in which a silicon-based solar cell is additionally laminated. In a tandem cell in which a thin-film crystalline silicon solar cell according to the present invention and an amorphous silicon solar cell including a non-doped layer having a thickness of 0.4 μm were stacked, 13.0 mA / cm was obtained under the same light irradiation conditions as in Example 1. Two
Short circuit current, open circuit voltage of 1.38 volt, and 1
A conversion efficiency of 3.0% was obtained.

【0029】[0029]

【発明の効果】以上のように、本発明によれば、薄膜結
晶質シリコン系材料において優れた界面特性を有する半
導体接合の形成を行なうことができ、その接合形成技術
を用いて薄膜結晶質シリコン系光電変換装置において、
高い光電変換効率を得ることができる。
As described above, according to the present invention, a semiconductor junction having excellent interface characteristics can be formed in a thin-film crystalline silicon-based material. System photoelectric conversion device,
High photoelectric conversion efficiency can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】光電変換装置の基本的な構造の一例を示す模式
的な斜視図である。
FIG. 1 is a schematic perspective view illustrating an example of a basic structure of a photoelectric conversion device.

【図2】本発明による光電変換装置に含まれる結晶構造
の一例を示す透過型電子顕微鏡による顕微鏡写真図であ
る。
FIG. 2 is a photomicrograph by a transmission electron microscope showing an example of a crystal structure included in the photoelectric conversion device according to the present invention.

【符号の説明】[Explanation of symbols]

1 ガラス等からなる基板 2 下地電極層 3 光電変換層 4 窓層 5 透明電極層 6 櫛形金属電極 7 入射光 DESCRIPTION OF SYMBOLS 1 Substrate made of glass etc. 2 Base electrode layer 3 Photoelectric conversion layer 4 Window layer 5 Transparent electrode layer 6 Comb-shaped metal electrode 7 Incident light

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 薄膜結晶質シリコン系光電変換層と、 半導体接合界面を介して前記光電変換層に接して形成さ
れていて0.01原子%以上の導電型決定不純物原子を
含む微結晶シリコン系導電型薄膜層とを含み、 前記接合界面の両側において対応する等価な結晶配向軸
の少なくとも1つのずれ角が15度以下である界面領域
の割合が5%以上で50%以下の範囲内にあることを特
徴とする薄膜シリコン系光電変換装置。
1. A microcrystalline silicon-based photoelectric conversion layer comprising: a thin-film crystalline silicon-based photoelectric conversion layer; and a microcrystalline silicon-based photoelectric conversion layer formed by being in contact with the photoelectric conversion layer via a semiconductor junction interface and containing not less than 0.01 atomic% of conductivity-type determining impurity atoms. A conductive type thin film layer, and a ratio of an interface region in which at least one equivalent crystal orientation axis has a shift angle of 15 degrees or less on both sides of the bonding interface is in a range of 5% or more and 50% or less. A thin-film silicon-based photoelectric conversion device characterized by the above-mentioned.
【請求項2】 前記光電変換層はプラズマCVD法によ
って550℃以下の下地温度の下で形成されたものであ
って、80%以上の体積結晶化分率と、0.1原子%以
上で30原子%以下の範囲内の水素含有量と、0.5μ
m以上で20μm以下の範囲内の厚さとを有するととも
に、その膜面に平行に(110)の優先結晶配向面を有
し、そのX線回折における(220)回折ピークに対す
る(111)回折ピークの強度比が0.2以下であるこ
とを特徴とする請求項1に記載の薄膜シリコン系光電変
換装置。
2. The method according to claim 1, wherein the photoelectric conversion layer is formed at a base temperature of 550 ° C. or less by a plasma CVD method, and has a volume crystallization fraction of 80% or more and a volume crystallization fraction of 30% or more. Hydrogen content in the range of at most atomic%,
m and a thickness in the range of 20 μm or less, and has a (110) preferred crystal orientation plane parallel to the film plane, and the (111) diffraction peak of the (220) diffraction peak in the X-ray diffraction thereof. 2. The thin-film silicon-based photoelectric conversion device according to claim 1, wherein the intensity ratio is 0.2 or less.
【請求項3】 前記導電型薄膜層は10原子%以上で2
5原子%以下の範囲内の水素を含有し、かつ2.0eV
以上の光学バンドギャップを有することを特徴とする請
求項1または2に記載の薄膜シリコン系光電変換装置。
3. The method according to claim 1, wherein the conductive type thin film layer is not less than
Contains hydrogen in the range of 5 atomic% or less and 2.0 eV
3. The thin-film silicon-based photoelectric conversion device according to claim 1, having the above optical band gap.
【請求項4】 請求項1から3のいずれかの項に記載の
薄膜シリコン系光電変換装置を製造するための方法であ
って、 前記導電型薄膜層はプラズマCVD法によって80℃以
上で200℃未満の範囲内の下地温度のもとで前記光電
変換層上に堆積させられることを特徴とする薄膜シリコ
ン系光電変換装置の製造方法。
4. The method for manufacturing a thin-film silicon-based photoelectric conversion device according to claim 1, wherein the conductive thin-film layer is formed at a temperature of 80 ° C. or higher and 200 ° C. by a plasma CVD method. A method for manufacturing a thin-film silicon-based photoelectric conversion device, wherein the thin-film silicon-based photoelectric conversion device is deposited on the photoelectric conversion layer at a base temperature within the range of
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