JPH11135934A - Bare ic and smd mixed mounting method - Google Patents

Bare ic and smd mixed mounting method

Info

Publication number
JPH11135934A
JPH11135934A JP19183498A JP19183498A JPH11135934A JP H11135934 A JPH11135934 A JP H11135934A JP 19183498 A JP19183498 A JP 19183498A JP 19183498 A JP19183498 A JP 19183498A JP H11135934 A JPH11135934 A JP H11135934A
Authority
JP
Japan
Prior art keywords
bare
smd
circuit board
electrode
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19183498A
Other languages
Japanese (ja)
Inventor
Kenichiro Suetsugu
憲一郎 末次
Atsushi Yamaguchi
敦史 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19183498A priority Critical patent/JPH11135934A/en
Publication of JPH11135934A publication Critical patent/JPH11135934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To mount a surface mounting method part and a bare IC parallel in the same process line, utilizing laser ablation two processes for supplying a junction material to an electrode pad of a terminal electrode of a bare IC and supplying a sealing material to a part including a bare IC and a circuit board. SOLUTION: A terminal electrodes 4 and 4' are laminated on a circuit board 5. Eutectic solder 7 is supplied to a junction part of an electrode 9 of a surface mounted device(SMD) 6. Although the eutectic solder 7 is used as a junction material in the method, lead-free solder can be also used. Meanwhile, a junction material consisting of alloy of two or more kinds of metals is supplied on the electrode pad 2 of an electrode terminal of a bare IC by a laser ablasion method, and a bump electrode 3 is formed. After the bump electrode 3 and the terminal electrode 4 are joined, a sealing material is supplied to a part including the bare IC 1. for total resin sealing as shown in a resin sealing layer 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ベアICと表面実
装方式部品(以下、SMDと称す)を回路基板上に混載
する半導体装置の実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device in which a bare IC and a surface mount type component (hereinafter referred to as SMD) are mixedly mounted on a circuit board.

【0002】[0002]

【従来の技術】従来、ベアICとSMDを基板上に混載
する実装方法では、ベアICを実装する半導体実装工程
後、SMDを実装する表面実装工程(以下、SMT工程
と称す)が行われていた。半導体実装工程において、ベ
アICの電極パッド上に備えられたバンプ電極を、導電
フィラーとして2種以上の金属の合金からなる微粉を含
む導電性接着剤により、回路基板上の端子電極に電気的
に接続していた。その接続には2時間以上の時間が必要
であった。また、電気的に接続されたバンプ電極と回路
基板上の端子電極を、エポキシ系封止材を使用して樹脂
封止していた。その樹脂封止には、2時間から4時間の
時間が必要であった。
2. Description of the Related Art Conventionally, in a mounting method in which a bare IC and an SMD are mixedly mounted on a substrate, a surface mounting step (hereinafter, referred to as an SMT step) of mounting the SMD is performed after a semiconductor mounting step of mounting the bare IC. Was. In the semiconductor mounting process, the bump electrode provided on the electrode pad of the bare IC is electrically connected to the terminal electrode on the circuit board by a conductive adhesive containing fine powder of an alloy of two or more metals as a conductive filler. I was connected. The connection required more than two hours. Also, the electrically connected bump electrodes and the terminal electrodes on the circuit board are resin-sealed using an epoxy-based sealing material. Two to four hours were required for the resin sealing.

【0003】[0003]

【発明が解決しようとする課題】このように従来のベア
ICのバンプ電極の回路基板上の端子電極への接続と、
回路基板上に接続されたベアICの樹脂封止には長時間
が必要であった。このため、半導体実装工程の以上の工
程はラインタクトが1分以内のSMT工程とタクト時間
が異なりすぎる点でマッチングできなかった。従って、
ベアICとSMDを、同じ工程ラインの流れの中で回路
基板上に並行して実装することが困難であった。そのた
め、半導体実装工程とSMT工程を同じ工程ラインの流
れの中で並行して行うことができる実装方法の実現が求
められていた。本発明は、このような課題を解決し、半
導体実装工程とSMT工程を同じ工程ラインの流れの中
で行うことのできるベアICとSMDの実装方法を提供
することを目的とする。
As described above, the connection of the bump electrode of the conventional bare IC to the terminal electrode on the circuit board is as follows.
It took a long time to seal the bare IC connected to the circuit board with resin. For this reason, the above steps of the semiconductor mounting step could not be matched because the tact time was too different from that of the SMT step in which the line tact was within 1 minute. Therefore,
It has been difficult to mount the bare IC and the SMD in parallel on the circuit board in the same process line flow. Therefore, there has been a demand for a mounting method capable of performing the semiconductor mounting process and the SMT process in parallel in the same process line flow. An object of the present invention is to solve such a problem and to provide a method of mounting a bare IC and an SMD in which a semiconductor mounting process and an SMT process can be performed in the same process line flow.

【0004】[0004]

【課題を解決するための手段】本発明のベアIC及びS
MD混載実装方法は、ベアICとSMDを回路基板上に
実装する半導体装置の実装方法であって、SMDの電極
に接合材料の供給を行う工程、ベアICの端子電極の電
極パッドにレーザ・アブレーション法により2種以上の
金属の合金からなる接合材料の供給を行ってバンプを形
成し前記バンプに対しフッラクススプレーを行う工程、
前記SMD及び前記ベアICを回路基板の端子電極上に
マウントする工程、前記SMDと前記ベアICがマウン
トされた回路基板にリフロー半田付処理を施して、前記
SMDの電極の前記回路基板への接合並びに前記バンプ
の前記回路基板の端子電極への接合をする工程、及び前
記バンプと前記回路基板を含む部分にレーザ・アブレー
ション法により封止材を供給して全面樹脂封止する工
程、を有する。ここで、レーザー・アブレーション法と
は、原子間結合又は分子間結合をレーザーのエネルギー
によって励起させてこの結合を切断し、この切断した原
子若しくは原子団又は分子若しくは分子団をレーザのエ
ネルギーによって対象物に移送して供給する加工方法を
意味する。本発明によれば、レーザ・アブレーション法
を利用することにより、ベアICとSMDを同じ工程ラ
インの流れの中で回路基板上に並行して実装することが
できる。
SUMMARY OF THE INVENTION The bare IC and S according to the present invention are provided.
The MD mounting method is a method for mounting a semiconductor device in which a bare IC and an SMD are mounted on a circuit board. Supplying a bonding material comprising an alloy of two or more metals by a method to form a bump and performing flux spray on the bump;
Mounting the SMD and the bare IC on terminal electrodes of a circuit board, performing reflow soldering on the circuit board on which the SMD and the bare IC are mounted, and joining the SMD electrodes to the circuit board; And a step of joining the bump to a terminal electrode of the circuit board, and a step of supplying a sealing material to a portion including the bump and the circuit board by a laser ablation method to perform resin sealing on the entire surface. Here, the laser ablation method is to excite interatomic bonds or intermolecular bonds by the energy of a laser to cut the bonds, and to apply the cut atoms or atomic groups or molecules or molecular groups to an object by laser energy. Means a processing method that is transferred to and supplied to According to the present invention, by using the laser ablation method, the bare IC and the SMD can be mounted in parallel on the circuit board in the same process line flow.

【0005】[0005]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。 《実施例》本発明の実施例における半導体装置のベアI
C及びSMD混載実装方法について図1及び図2を用い
て説明する。図1は、本発明によるベアIC及びSMD
混載実装方法により混載実装し封止前の回路基板の断面
図である。図2は、本発明によるベアIC及びSMD混
載実装方法により混載実装した後さらに封止をした後の
回路基板の断面図である。図1に示す封止前の回路基板
は、回路基板5、回路基板5の上に設けられた端子電極
4,4’、ベアIC 1の下面に設けた電極パッド2、
電極パッド2に設けたバンプ電極3、及びSMD 6の
電極9の接合部に設けた接合ハンダとしての共晶はんだ
7を有する。端子電極4上にはバンプ電極3がレーザ・
アブレーション法により接合され、他の端子電極4’の
上にはSMD 6の電極9が共晶はんだ7によって接合
されている。図2に示す封止後の回路基板は、図1の各
構成要素に加えて、ベアIC 1とその下面の電極パッ
ド2、及びバンプ電極3を封止する樹脂封止層8を備え
ている。
Embodiments of the present invention will be described below with reference to the drawings. << Embodiment >> Bare I of a semiconductor device in an embodiment of the present invention
The C and SMD mixed mounting method will be described with reference to FIGS. FIG. 1 shows a bare IC and an SMD according to the present invention.
FIG. 4 is a cross-sectional view of a circuit board before mounting and sealing by a mixed mounting method. FIG. 2 is a cross-sectional view of the circuit board after being mounted and sealed by the mixed mounting method of bare IC and SMD according to the present invention. The circuit board before sealing shown in FIG. 1 includes a circuit board 5, terminal electrodes 4 and 4 ′ provided on the circuit board 5, electrode pads 2 provided on the lower surface of the bare IC 1,
A eutectic solder 7 is provided as a bonding solder provided at a bonding portion between the bump electrode 3 provided on the electrode pad 2 and the electrode 9 of the SMD 6. A bump electrode 3 is formed on the terminal electrode 4 by a laser.
An electrode 9 of SMD 6 is joined by eutectic solder 7 on another terminal electrode 4 ′. The circuit board after sealing shown in FIG. 2 includes, in addition to the components shown in FIG. 1, a bare IC 1, an electrode pad 2 on the lower surface thereof, and a resin sealing layer 8 for sealing the bump electrodes 3. .

【0006】以下、ベアICとSMDを回路基板上に実
装する方法について説明する。回路基板5上には端子電
極4及び4’がメタルマスクを用いた既知の方法で積層
されている。SMD 6の電極9の接合部分に対して、
共晶はんだ7がメタルマスクを用いた既知の印刷方法で
供給される。本実施例においては接合材料として共晶は
んだ7を用いているが、他に鉛フリーはんだを用いるこ
ともできる。他方、ベアIC 1の端子電極の電極パッ
ド2上に、レーザ・アブレーション法により2種以上の
金属の合金からなる接合材料の供給を行いバンプ電極3
を形成する。
Hereinafter, a method for mounting a bare IC and an SMD on a circuit board will be described. Terminal electrodes 4 and 4 ′ are laminated on the circuit board 5 by a known method using a metal mask. For the joint portion of the electrode 9 of the SMD 6,
The eutectic solder 7 is supplied by a known printing method using a metal mask. In the present embodiment, the eutectic solder 7 is used as a joining material, but a lead-free solder can also be used. On the other hand, a bonding material composed of an alloy of two or more metals is supplied onto the electrode pads 2 of the terminal electrodes of the bare IC 1 by a laser ablation method to form bump electrodes 3.
To form

【0007】上記のバンプ電極3の作製工程の最適な実
施例としては、まず、SnとAgの合金(例えば、Sn
は96.5wt%、Agは3.5wt%)と、SnとB
iの合金(例えば、Snは42wt%、Biは58wt
%)とを9:1となるように、テフロンシート上で厚さ
が10μm乃至30μmに蒸着し、材料シートを作製す
る。ベアIC 1の電極パッド2とこの材料シートを約
0.1mmの間隔を保ち、材料シートのベアIC 1の
反対側の面に対して、レーザ出力0.15w、照射時間
0.1秒、スポット径50μmのエキシマレーザを照射
する。この照射により、材料シートに蒸着された合金が
溶発され、端子電極2にバンプ電極3を形成する。上記
材料の他に、SnとIn、SnとBi、SnとAgのグ
ループからなる金属群をベースにした合金、Sn−Ag
−Bi系合金(Snは83〜92wt%、Agは2.5
〜4.0wt%、Biは5〜18wt%)、Sn−Ag
−Bi−In−Cu系合金(Snは80〜92wt%、
Agは2.5〜4.0wt%、Biは5〜18wt%、
Inは0.1〜1.5wt%、Cuは0.1〜0.7w
t%)を用いることもできる。
[0007] As an optimal embodiment of the manufacturing process of the bump electrode 3, first, an alloy of Sn and Ag (for example, Sn
Is 96.5 wt%, Ag is 3.5 wt%), Sn and B
i alloy (for example, Sn is 42 wt%, Bi is 58 wt%)
%) On a Teflon sheet so as to have a thickness of 10 μm to 30 μm so that a material sheet is prepared. The electrode pad 2 of the bare IC 1 and the material sheet are kept at a distance of about 0.1 mm, and a laser output of 0.15 w, an irradiation time of 0.1 second, and a spot are applied to the surface of the material sheet opposite to the bare IC 1. An excimer laser having a diameter of 50 μm is irradiated. By this irradiation, the alloy deposited on the material sheet is ablated, and the bump electrode 3 is formed on the terminal electrode 2. In addition to the above materials, an alloy based on a metal group consisting of Sn and In, Sn and Bi, Sn and Ag, Sn-Ag
-Bi-based alloy (Sn: 83-92 wt%, Ag: 2.5
~ 4.0wt%, Bi is 5 ~ 18wt%), Sn-Ag
-Bi-In-Cu-based alloy (Sn is 80 to 92 wt%,
Ag is 2.5-4.0 wt%, Bi is 5-18 wt%,
In is 0.1 to 1.5 wt%, Cu is 0.1 to 0.7 w
t%) can also be used.

【0008】このバンプ電極3及びSMD 6のはんだ
付部に対し、フラックススプレーを行う。その後、SM
D 6及びベアIC 1を回路基板5上にマウントする。
SMD 6及びベアIC 1がマウントされた後、SMD
6とベアIC 1を含む部分に対し、好適な実施例では
ピーク温度250℃〜260℃の大気中で約1分間リフ
ロー半田付処理を行う。この処理により、SMD 6の
電極9の、回路基板5への電気的及び機械的接合を行
い、且つベアIC 1のバンプ電極3の、回路基板5上
の端子電極4への電気的及び機械的接合を行う。なお、
大気中でリフロー半田付処理を行う代わりに、窒素など
の不活性気体、又は水素などの還元気体中でリフロー半
田付処理を行うこともできる。バンプ電極3と端子電極
4が電気的及び機械的に接合された後、レーザ・アブレ
ーション法により、ベアIC 1を含む部分に封止材を
供給し、図2の樹脂封止層8に示すように全面樹脂封止
する。
[0008] Flux spraying is performed on the soldered portions of the bump electrode 3 and the SMD 6. After that, SM
D 6 and the bare IC 1 are mounted on the circuit board 5.
After the SMD 6 and the bare IC 1 are mounted, the SMD
In a preferred embodiment, a reflow soldering process is performed on the part including the bare IC 6 and the bare IC 1 in the air having a peak temperature of 250 ° C. to 260 ° C. for about 1 minute. By this processing, the electrode 9 of the SMD 6 is electrically and mechanically connected to the circuit board 5, and the bump electrode 3 of the bare IC 1 is electrically and mechanically connected to the terminal electrode 4 on the circuit board 5. Perform bonding. In addition,
Instead of performing the reflow soldering process in the air, the reflow soldering process may be performed in an inert gas such as nitrogen or a reducing gas such as hydrogen. After the bump electrode 3 and the terminal electrode 4 are electrically and mechanically joined, a sealing material is supplied to a portion including the bare IC 1 by a laser ablation method, and as shown in a resin sealing layer 8 in FIG. The entire surface is resin-sealed.

【0009】上記の樹脂封止層8の作製工程のレーザ・
アブレーション法による最適な実施例を述べる。先ず、
テフロンシートに0.5乃至1.0mm厚となるように
封止材としてのポリエチレンを塗りつけて材料シートを
作製する。次に、この材料シートをベアIC 1上で約
3mmの間隔を保って保持し、材料シートのベアIC1
に向いている面とは反対側の面から、レーザ出力200
mw、照射時間60秒、スポット径50μmのYAGレ
ーザ照射を行う。この照射により、材料シートに塗りつ
けられたポリエチレンが溶発され、ベアIC 1の全面
を樹脂封止する。上記テフロンシートに塗りつける材料
としては、ポリエチレンの他にポリプロピレン、ポリア
ミド又はポリカーボネイトを用いることもでき、これら
の場合にも同様な照射条件によりレーザアブレーション
による樹脂封止ができる。
In the above-described process of forming the resin sealing layer 8, the laser
An optimal embodiment by the ablation method will be described. First,
A Teflon sheet is coated with polyethylene as a sealing material to a thickness of 0.5 to 1.0 mm to produce a material sheet. Next, the material sheet is held on the bare IC 1 at an interval of about 3 mm, and the bare IC 1 of the material sheet is held.
From the side opposite to the side facing
YAG laser irradiation with mw, irradiation time of 60 seconds and spot diameter of 50 μm is performed. As a result of this irradiation, the polyethylene applied to the material sheet is ablated and the entire surface of the bare IC 1 is sealed with resin. As the material to be applied to the Teflon sheet, polypropylene, polyamide or polycarbonate can be used in addition to polyethylene. In these cases, resin sealing by laser ablation can be performed under the same irradiation conditions.

【0010】本発明では、以上の実施例に示したように
レーザ・アブレーション法を用いることにより、ベアI
C 1の電極パッド2に材料シートから接合材料を供給
しバンプ電極3を形成するのに要する時間が、3分以内
になる。さらに、リフロー半田付処理を行うことによっ
て電気的に接合されたベアIC 1を封止するための封
止材を供給し封止させるのに要する時間が、1分以内に
なる。これらの結果、1分程度の所要時間しか要さない
SMD 6の回路基板への実装と、3分程度の時間でバ
ンプ電極3を形成できかつ1分程度の時間でベアIC部
分を樹脂封止できるベアIC 1の回路基板5への実
装、の両方の実装を同一の工程ラインの流れの中で大き
な時間の過不足なしに並行して円滑に行うことができ
る。
[0010] In the present invention, as shown in the above embodiment, by using the laser ablation method, the bare I
The time required for supplying the bonding material from the material sheet to the electrode pad 2 of C1 and forming the bump electrode 3 is less than 3 minutes. Furthermore, the time required to supply and seal a sealing material for sealing the barely bonded bare IC 1 by performing the reflow soldering process is less than one minute. As a result, it is possible to mount the SMD 6 on the circuit board, which requires only about 1 minute, and to form the bump electrode 3 in about 3 minutes, and to seal the bare IC portion with the resin in about 1 minute. Both the mounting of the bare IC 1 and the mounting of the bare IC 1 on the circuit board 5 can be performed smoothly in parallel in the flow of the same process line without a large excess or shortage of time.

【0011】[0011]

【発明の効果】以上のように、半導体実装工程の中の、
ベアICの端子電極の電極パッドに接合材料の供給を行
ってバンプを形成する工程と、ベアICと回路基板を含
む部分に封止材を供給して全面樹脂封止する工程と、の
二工程に、レーザ・アブレーション法を利用することに
より、レーザ・アブレーション法に用いられる設備のみ
を新たに組み入れることで、SMDとベアICを同一の
工程ラインの中で並行して実装することが可能となる。
As described above, in the semiconductor mounting process,
Two steps of a step of supplying a bonding material to the electrode pad of the terminal electrode of the bare IC to form a bump, and a step of supplying a sealing material to a portion including the bare IC and the circuit board to resin-encapsulate the entire surface. In addition, by using the laser ablation method, it is possible to mount the SMD and bare IC in parallel in the same process line by newly incorporating only the equipment used for the laser ablation method. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるベアIC及びSMD混載実装方法
により混載実装し封止前の回路基板の断面図。
FIG. 1 is a cross-sectional view of a circuit board before being sealed and mounted by a bare IC and SMD mixed mounting method according to the present invention.

【図2】本発明によるベアIC及びSMD混載実装方法
により混載実装した後さらに封止した後の回路基板の断
面図。
FIG. 2 is a cross-sectional view of a circuit board after being mounted and sealed by a mixed mounting method of a bare IC and an SMD according to the present invention.

【符号の説明】 1 ベアIC 2 電極パッド 3 バンプ電極 4 端子電極 5 回路基板 6 SMD 7 共晶はんだ 8 樹脂封止層[Description of Signs] 1 Bare IC 2 Electrode pad 3 Bump electrode 4 Terminal electrode 5 Circuit board 6 SMD 7 Eutectic solder 8 Resin sealing layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ベアICとSMDを回路基板上に実装す
る半導体装置の実装方法であって、 SMDの電極に接合材料の供給を行う工程、 ベアICの端子電極の電極パッドにレーザ・アブレーシ
ョン法により2種以上の金属の合金からなる接合材料の
供給を行ってバンプを形成し前記バンプに対しフッラク
ススプレーを行う工程、 前記SMD及び前記ベアICを回路基板の端子電極上に
マウントする工程、 前記SMDと前記ベアICがマウントされた回路基板に
リフロー半田付処理を施して、前記SMDの電極の前記
回路基板への接合並びに前記バンプの前記回路基板の端
子電極への接合をする工程、及び前記バンプと前記回路
基板を含む部分にレーザ・アブレーション法により封止
材を供給して全面樹脂封止する工程、 を有する半導体装置のベアIC及びSMD混載実装方
法。
1. A mounting method of a semiconductor device for mounting a bare IC and an SMD on a circuit board, wherein a bonding material is supplied to an electrode of the SMD, and a laser ablation method is applied to an electrode pad of a terminal electrode of the bare IC. Supplying a bonding material composed of an alloy of two or more metals to form a bump and performing flux spray on the bump; mounting the SMD and the bare IC on a terminal electrode of a circuit board; Performing a reflow soldering process on the circuit board on which the SMD and the bare IC are mounted, joining the electrodes of the SMD to the circuit board, and joining the bumps to terminal electrodes of the circuit board; and Supplying a sealing material to a portion including the bump and the circuit board by a laser ablation method to perform resin sealing on the entire surface. Bear IC and SMD hybrid implementation.
【請求項2】 前記2種以上の金属の合金が、SnとI
n、SnとBi、SnとAgのグループから選択した金
属群をベースにした合金であり、Sn−Ag−Bi系合
金の場合Snが83〜92wt%、Agが2.5〜4.
0wt%、Biが5〜18wt%であり、Sn−Ag−
Bi−In−Cu系合金の場合Snが80〜92wt
%、Agが2.5〜4.0wt%、Biが5〜18wt
%、Inが0.1〜1.5wt%、Cuが0.1〜0.
7wt%である、 ことを特徴とする、請求項1に記載のベアIC及びSM
D混載実装方法。
2. An alloy of two or more metals, wherein Sn and I
n, Sn and Bi, and an alloy based on a metal group selected from the group consisting of Sn and Ag. In the case of a Sn-Ag-Bi alloy, Sn is 83 to 92 wt% and Ag is 2.5 to 4.
0 wt%, Bi is 5 to 18 wt%, and Sn-Ag-
In the case of Bi-In-Cu alloy, Sn is 80-92 wt.
%, Ag is 2.5 to 4.0 wt%, Bi is 5 to 18 wt%
%, 0.1 to 1.5 wt% of In, and 0.1 to 0.1 wt% of Cu.
The bare IC and the SM according to claim 1, wherein the content is 7 wt%.
D Mixed mounting method.
【請求項3】 前記封止材が、ポリエチレン、ポリプロ
ピエン、ポリアミド又はポリカーボネイトである、 ことを特徴とする、請求項1に記載のベアIC及びSM
D混載実装方法。
3. The bare IC and SM according to claim 1, wherein the sealing material is polyethylene, polypropylene, polyamide, or polycarbonate.
D Mixed mounting method.
【請求項4】 前記リフロー半田付処理を、不活性気体
中又は還元気体中で行う、 ことを特徴とする、請求項1に記載のベアIC及びSM
D混載実装方法。
4. The bare IC and SM according to claim 1, wherein the reflow soldering is performed in an inert gas or a reducing gas.
D Mixed mounting method.
JP19183498A 1997-08-28 1998-07-07 Bare ic and smd mixed mounting method Pending JPH11135934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19183498A JPH11135934A (en) 1997-08-28 1998-07-07 Bare ic and smd mixed mounting method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9-233057 1997-08-28
JP23305797 1997-08-28
JP19183498A JPH11135934A (en) 1997-08-28 1998-07-07 Bare ic and smd mixed mounting method

Publications (1)

Publication Number Publication Date
JPH11135934A true JPH11135934A (en) 1999-05-21

Family

ID=26506925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19183498A Pending JPH11135934A (en) 1997-08-28 1998-07-07 Bare ic and smd mixed mounting method

Country Status (1)

Country Link
JP (1) JPH11135934A (en)

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