JPH11135808A - Manufacture of surge protective element - Google Patents

Manufacture of surge protective element

Info

Publication number
JPH11135808A
JPH11135808A JP9298441A JP29844197A JPH11135808A JP H11135808 A JPH11135808 A JP H11135808A JP 9298441 A JP9298441 A JP 9298441A JP 29844197 A JP29844197 A JP 29844197A JP H11135808 A JPH11135808 A JP H11135808A
Authority
JP
Japan
Prior art keywords
region
substrate
impurity concentration
conductivity
surge protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9298441A
Other languages
Japanese (ja)
Other versions
JP3117005B2 (en
Inventor
Hiroshi Okamoto
洋 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP09298441A priority Critical patent/JP3117005B2/en
Priority to TW087110982A priority patent/TW373192B/en
Priority to KR1019980030881A priority patent/KR19990036583A/en
Publication of JPH11135808A publication Critical patent/JPH11135808A/en
Application granted granted Critical
Publication of JP3117005B2 publication Critical patent/JP3117005B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/12Overvoltage protection resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Thyristors (AREA)
  • Thermistors And Varistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a surge protective element whose breakover voltage is made low and whose capacitance is not increased as compared with conventional cases. SOLUTION: A first-conductivity region 11, whose impurity concentration is higher than that of a first-conductivity substrate 10 is formed through diffusion in a part on the first main face of the substrate. A first-conductivity layer 10a whose impurity concentration is lower than that of the region 11 is formed over the whole first main face of the semiconductor substrate 10, including the region 11. A second-conductivity region 12 is formed at a depth which joins the region 11 from the surface of the layer 10a. A second-conductivity region 13 is formed on the second main face of the semiconductor substrate 10 so as to face the region 12. A first-conductivity region 14 is formed inside the region 12. An electrode 16 which comes into ohmic contact with the region 12 and with the region 14 is formed, and an electrode 17 which comes into ohmic contact with the region 13 is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はサージに対して電子
機器を防護するサージ防護素子の製造方法に関する。更
に詳しくは導電型がnpnp又はpnpn構造を有する
サージ防護素子の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a surge protection element for protecting an electronic device against a surge. More specifically, the present invention relates to a method for manufacturing a surge protection element having a conductivity type of npnp or pnpn structure.

【0002】[0002]

【従来の技術】近年、電子機器がデジタル化し、その消
費電力が抑制されるようになると、電子機器の耐圧自体
も低下していく傾向になる。そのため電子機器のサージ
防護素子にはより低いサージ電圧で動作を開始して、電
子機器を防護するものが要求される。従来、この種のサ
ージ防護素子の動作を低電圧で開始させるために、サー
ジ防護素子の出発材料であるシリコンウェーハに関し
て、不純物濃度の高い、即ち抵抗率の低いウェーハが選
ばれていた。また別の手段として、図1(b)に示すよ
うにn型のシリコン基板1の第1主面の一部に不純物濃
度の高い同じn型の領域2を通常の拡散処理により形成
した後、基板1の両面である第1主面と第2主面にそれ
ぞれp型の領域3及び4を形成し、領域3内にn型の領
域5を更に形成し、この領域5及び領域3にオーミック
接触する電極6を形成する一方、第2主面の領域4にオ
ーミック接触する電極7を形成したサージ防護素子が提
案されている。このサージ防護素子では領域2を形成す
ることにより基板の不純物濃度を局所的に増大させて、
低いブレークオーバ電圧を実現していた。
2. Description of the Related Art In recent years, as electronic devices have been digitized and their power consumption has been suppressed, the withstand voltage itself of electronic devices tends to decrease. Therefore, a surge protection element of an electronic device is required to start operating at a lower surge voltage to protect the electronic device. Conventionally, in order to start the operation of this type of surge protection element at a low voltage, a silicon wafer that is a starting material of the surge protection element has been selected to have a high impurity concentration, that is, a wafer having a low resistivity. As another means, as shown in FIG. 1B, after forming the same n-type region 2 having a high impurity concentration on a part of the first main surface of the n-type silicon substrate 1 by a normal diffusion process, P-type regions 3 and 4 are respectively formed on the first main surface and the second main surface which are both surfaces of the substrate 1, an n-type region 5 is further formed in the region 3, and ohmic regions are formed on the regions 5 and 3. A surge protection element has been proposed in which the contacting electrode 6 is formed while the ohmic contacting electrode 7 is formed in the region 4 of the second main surface. In this surge protection element, the region 2 is formed to locally increase the impurity concentration of the substrate,
A low breakover voltage was realized.

【0003】[0003]

【発明が解決しようとする課題】しかし、前者のサージ
防護素子は、不純物濃度が高いウェーハを用いることに
より、そのブレークオーバ電圧を低くし得るものの、接
合容量が増大し、適用される回路において信号伝達が遅
延する不具合があった。また極めて低いブレークオーバ
電圧、例えば10V程度を実現しようとしても、それに
見合う不純物濃度のシリコンウェーハの製造が至難であ
り、仮に不純物が極めて高濃度のウェーハが製造できた
としても、このウェーハに対するベース拡散及びエミッ
タ拡散を実質的に行うことができない問題があった。n
pnp構造のサージ防護素子におけるp層に挟まれたn
層は、一般に然るべき電流容量や応答速度を確保する観
点からある程度薄くする必要がある。後者のサージ防護
素子においては、領域3と領域4に挟まれる層1aを薄
くするために領域3及び4を深く、即ち厚く形成する必
要があり、これに先んじて実施される領域2の形成のた
めの拡散は更に深く行わなければならず熱処理が困難に
なる欠点がある。またブレークオーバ電圧を決定する領
域2と領域3の接合は基板表面から深い位置にあるた
め、n拡散の領域2が通常の熱拡散法で形成される以
上、この接合の界面不純物濃度をあまり高くはできな
い。換言すればブレークオーバ電圧の制御し得る範囲が
狭く、これによりブレークオーバ電圧を極めて低くした
サージ防護素子を得ることができなかった。本発明の目
的は、従来と比べてブレークオーバ電圧を低くしかつ静
電容量を増大させないサージ防護素子の製造方法を提供
することにある。
However, in the former surge protection device, although the breakover voltage can be lowered by using a wafer having a high impurity concentration, the junction capacitance is increased, and the signal applied to the circuit is reduced. There was a problem that transmission was delayed. Further, even if an extremely low breakover voltage, for example, about 10 V, is to be realized, it is extremely difficult to manufacture a silicon wafer having an impurity concentration commensurate with it, and even if a wafer having an extremely high impurity concentration can be manufactured, the base diffusion for this wafer is difficult. In addition, there has been a problem that the emitter cannot be substantially diffused. n
n sandwiched between p layers in surge protection element of pnp structure
The layer generally needs to be thin to some extent from the viewpoint of securing appropriate current capacity and response speed. In the latter surge protection element, it is necessary to form the regions 3 and 4 deep, that is, thick, in order to reduce the thickness of the layer 1a sandwiched between the region 3 and the region 4. Prior to this, the formation of the region 2 is performed. Diffusion must be performed further deeply, which makes the heat treatment difficult. In addition, since the junction between the region 2 and the region 3 for determining the breakover voltage is at a deep position from the substrate surface, the interface impurity concentration of this junction is set to be too high as long as the n-diffusion region 2 is formed by the ordinary thermal diffusion method. Can not. In other words, the controllable range of the breakover voltage is narrow, so that a surge protection element with a very low breakover voltage cannot be obtained. An object of the present invention is to provide a method of manufacturing a surge protection element that can lower the breakover voltage and does not increase the capacitance as compared with the related art.

【0004】[0004]

【課題を解決するための手段】請求項1に係る発明は、
図1(a)に示すように、第1導電型の半導体基板10
の第1主面の一部にこの基板より不純物濃度が高い第1
導電型の第1領域11を形成し、この第1領域11を含
む半導体基板10の第1主面全体に第1領域11より不
純物濃度が低い第1導電型の層10aを形成し、この層
10aの表面から第1領域11と接合する深さに第2導
電型の第2領域12を形成し、半導体基板10の第2主
面に第2領域12に対向して第2導電型の第3領域13
を形成し、この第2領域12内に第1導電型の第4領域
14を形成し、第2領域12及び第4領域14にオーミ
ック接触する第1電極16を形成し、第3領域13にオ
ーミック接触する第2電極17を形成するサージ防護素
子の製造方法である。なお、図1では第1導電型をn、
第2導電型をpとしてnpnp構造のサージ防護素子を
例示したが、導電型のnをpに、またpをnに変えるこ
とにより、pnpn構造のサージ防護素子を同様に形成
することができる。
The invention according to claim 1 is
As shown in FIG. 1A, a semiconductor substrate 10 of a first conductivity type
Of the first principal surface having a higher impurity concentration than that of the substrate.
A first region 11 of a conductivity type is formed, and a first conductivity type layer 10 a having a lower impurity concentration than the first region 11 is formed over the entire first main surface of the semiconductor substrate 10 including the first region 11. A second region 12 of the second conductivity type is formed at a depth from the surface of the semiconductor substrate 10 to join the first region 11, and a second region 12 of the second conductivity type is formed on the second main surface of the semiconductor substrate 10 so as to face the second region 12. 3 areas 13
Is formed, a fourth region 14 of the first conductivity type is formed in the second region 12, a first electrode 16 in ohmic contact with the second region 12 and the fourth region 14 is formed, and a third region 13 is formed. This is a method for manufacturing a surge protection element that forms a second electrode 17 that makes ohmic contact. In FIG. 1, the first conductivity type is n,
Although the surge protection element of the npnp structure is illustrated assuming that the second conductivity type is p, the surge protection element of the pnpn structure can be similarly formed by changing n of the conductivity type to p and p to n.

【0005】[0005]

【発明の実施の形態】本発明は基本的に導電型がnpn
p又はpnpn構造の半導体からなる2端子のサージ防
護素子の製造方法である。本発明はnpnpn又はpn
pnp構造を有する双方向素子にも適用することができ
る。層10aはエピタキシャル成長により基板10と同
等の不純物濃度で形成するのが好ましい。層10aの厚
み及び領域11の不純物濃度プロファイルは、所望のブ
レークオーバ電圧及び領域12の厚みにより決められ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention basically has a conductivity type of npn.
This is a method for manufacturing a two-terminal surge protection element made of a semiconductor having a p or pnpn structure. The present invention relates to npnpn or pn
The present invention can also be applied to a bidirectional element having a pnp structure. The layer 10a is preferably formed by epitaxial growth with the same impurity concentration as the substrate 10. The thickness of the layer 10a and the impurity concentration profile of the region 11 are determined by a desired breakover voltage and the thickness of the region 12.

【0006】[0006]

【実施例】次に、本発明の実施例を図面に基づいて説明
する。 <実施例>図1(a)に示すように、n型のシリコン基
板10を用意し、目標とするブレークオーバ電圧に応じ
た濃度分布(デプスプロファイル)を有する領域11
を、基板10の第1主面からn型不純物(例えばリン)
を所定の条件にて拡散することにより形成する。次い
で、第1主面全体に、例えばエピタキシャル成長によ
り、導電型及び不純物濃度が基板10に等しいシリコン
層10aを形成する。
Next, an embodiment of the present invention will be described with reference to the drawings. <Embodiment> As shown in FIG. 1A, an n-type silicon substrate 10 is prepared, and a region 11 having a concentration distribution (depth profile) corresponding to a target breakover voltage is provided.
From the first main surface of the substrate 10 to an n-type impurity (for example, phosphorus).
Is formed by diffusing under predetermined conditions. Next, a silicon layer 10a having the same conductivity type and impurity concentration as the substrate 10 is formed on the entire first main surface by, for example, epitaxial growth.

【0007】次に、層10aの表面からp型不純物(例
えば硼素)を拡散し、領域11と接合Jaを有するよう
に、即ちシリコン層10aの厚み(深さ)を上回る領域
12を形成する。また第2主面よりp型不純物を拡散
し、領域12に対向する領域13を形成する。領域12
及び13は同時に、即ち一度の熱処理工程において形成
してもよい。Ja界面近傍の不純物濃度プロファイルは
素子のブレークオーバ電圧を決定する。続いて、領域1
2内にn型領域14を形成した後に、領域12及び14
にオーミック接触する電極15と、領域13にオーミッ
ク接触する電極16を形成する。これにより実施例のサ
ージ防護素子を得る。
Next, a p-type impurity (for example, boron) is diffused from the surface of the layer 10a to form a region 12 having a junction Ja with the region 11, that is, exceeding the thickness (depth) of the silicon layer 10a. . Further, a p-type impurity is diffused from the second main surface to form a region 13 facing region 12. Area 12
And 13 may be formed simultaneously, that is, in one heat treatment step. Impurity concentration profile of J a vicinity of an interface determines the breakover voltage of the device. Then, area 1
After forming the n-type region 14 in the region 2, the regions 12 and 14
And an electrode 16 that makes ohmic contact with the region 13 is formed. Thereby, the surge protection element of the embodiment is obtained.

【0008】<比較例>図1(b)に示すように、実施
例で用いた基板に対して、不純物濃度が等しく厚みがシ
リコン層10aの分だけ厚いシリコン基板1を用意す
る。基板の第1主面から、実施例における領域11を形
成する際と同一の熱処理条件にてn型不純物を拡散する
ことにより領域2を形成する。次いで、基板1の両面か
ら、実施例における領域12及び13を形成する際と同
一の熱処理条件にてp型不純物を拡散することにより領
域3及び4を形成する。領域2と領域3の接合Jbは、
実施例におけるJa同様、その界面近傍の不純物濃度プ
ロファイルが素子のブレークオーバ電圧を決定する。
<Comparative Example> As shown in FIG. 1B, a silicon substrate 1 having the same impurity concentration as the substrate used in the embodiment and having a thickness corresponding to the thickness of the silicon layer 10a is prepared. The region 2 is formed by diffusing an n-type impurity from the first main surface of the substrate under the same heat treatment conditions as when forming the region 11 in the embodiment. Next, regions 3 and 4 are formed from both surfaces of the substrate 1 by diffusing p-type impurities under the same heat treatment conditions as when forming the regions 12 and 13 in the embodiment. The junction J b of region 2 and region 3,
Similarly J a in example, the impurity concentration profile of the vicinity of the interface determines the breakover voltage of the device.

【0009】続いて、実施例における領域14を形成す
る際と同一の熱処理条件にて領域3内にn型領域5を形
成し、領域3及び5にオーミック接触する電極6と、領
域4にオーミック接触する電極7を形成する。これによ
り比較例のサージ防護素子を得る。
Subsequently, an n-type region 5 is formed in the region 3 under the same heat treatment conditions as when the region 14 in the embodiment is formed, and an electrode 6 in ohmic contact with the regions 3 and 5, and an ohmic contact in the region 4 are formed. An electrode 7 to be in contact is formed. Thereby, the surge protection element of the comparative example is obtained.

【0010】<比較観察>実施例における領域14、1
2、10b及び13は、npnp構造の主たる4層を構
成し、比較例においては領域3、5、1b及び4がこれ
に対応する。実施例と比較例において対応する領域同士
は、形成時の不純物拡散条件を同じくし、かつ拡散処理
の対象である基板(エピタキシャル層を含む)の厚み及
び不純物濃度が等しいことから、領域11或いは領域2
に関わる局所を除いた大部分においてそれぞれ厚み及び
不純物濃度プロファイルがそれぞれ等しい。一方、実施
例における領域11は比較例における領域2に比べ、拡
散条件を同一としたことにより不純物濃度プロファイル
は等しいが、エピタキシャル層の分だけ基板深部に位置
する。以上に基づきサージ防護素子のブレークオーバ電
圧を決定する接合、即ち実施例における領域11と12
の接合(Ja)と、比較例における領域2と3の接合
(Jb)とを比較すると、実施例の方がより界面の不純
物濃度が高く、従ってブレークオーバ電圧が低い。
<Comparative observation> Regions 14 and 1 in the embodiment
2, 10b and 13 constitute the four main layers of the npnp structure, and in the comparative example, the regions 3, 5, 1b and 4 correspond thereto. The regions corresponding to each other in the example and the comparative example have the same impurity diffusion conditions at the time of formation, and have the same thickness and impurity concentration of the substrate (including the epitaxial layer) to be subjected to the diffusion process. 2
The thickness and the impurity concentration profile are almost the same in most parts except for the local part related to the above. On the other hand, the region 11 in the example has the same impurity concentration profile as the region 2 in the comparative example due to the same diffusion conditions, but is located deeper in the substrate by the epitaxial layer. Based on the above, the junction for determining the breakover voltage of the surge protection element, that is, the regions 11 and 12 in the embodiment,
Comparing the junction (J a ) with the junction (J b ) between the regions 2 and 3 in the comparative example, the example has a higher impurity concentration at the interface, and therefore has a lower breakover voltage.

【0011】[0011]

【発明の効果】以上述べたように、本発明の製造方法に
よれば、ブレークオーバ電圧を制御するために設けた基
板内の局所的高濃度領域について、通常の不純物拡散技
術が可能ならしめる範囲内で当該領域の不純物濃度プロ
ファイルを調整できるのみならず、エピタキシャル成長
技術等の応用により当該領域の基板内に占める位置(基
板表面からの深さ)をも任意に調整し得ることから、低
いブレークオーバ電圧を有するサージ防護素子に関して
設計の自由度が向上し、具体的にはnpnp構造を構成
する主たる4層の厚み及び不純物濃度プロファイルを問
わず、低いブレークオーバ電圧の実現が可能となる。そ
の結果、更に具体的には、従来の前者のサージ防護素子
に比較して、低いブレークオーバ電圧を得るに当って、
高濃度基板を出発材料とする必要がなくなるため、製造
に際し不純物拡散における高温、長時間などの困難が回
避され得るとともに、機能的には静電容量が低く抑えら
れ、適用される回路において信号遅延などの不具合を生
じさせない。また従来の後者のサージ防護素子に比較し
て、例えば然るべき電流容量・応答性を得るためにnp
np構造におけるp層に挟まれたn層を薄く、即ち上下
のp層を厚く形成しても、基板内の局所的高濃度領域を
相応に深く位置させることにより、サージ防護素子のブ
レークオーバ電圧を決定する接合の界面不純物濃度を容
易に高くすることができ、従ってより低いブレークオー
バ電圧を容易に実現できる。
As described above, according to the manufacturing method of the present invention, a range in which a normal impurity diffusion technique can be used for a local high concentration region in a substrate provided for controlling a breakover voltage. In addition to being able to adjust the impurity concentration profile of the region within the substrate, it is also possible to arbitrarily adjust the position (depth from the substrate surface) of the region in the substrate by applying an epitaxial growth technique or the like. The degree of freedom in designing the surge protection element having a voltage is improved, and specifically, a low breakover voltage can be realized irrespective of the thickness and the impurity concentration profile of the four main layers constituting the npnp structure. As a result, more specifically, in obtaining a lower breakover voltage as compared with the former former surge protection device,
Since it is not necessary to use a high-concentration substrate as a starting material, it is possible to avoid difficulties such as a high temperature and a long time in the diffusion of impurities during manufacturing, and also, functionally, the capacitance is suppressed low, and signal delay in an applied circuit. Do not cause problems such as Also, for example, in order to obtain appropriate current capacity and response, np
Even if the n-layer sandwiched by the p-layers in the np structure is made thin, that is, the upper and lower p-layers are made thicker, the local high-concentration region in the substrate is located at a correspondingly deeper position, so that the break-over voltage of the surge protection element becomes higher. The interface impurity concentration of the junction which determines the above can easily be increased, and thus a lower breakover voltage can be easily realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a) 本発明実施例のサージ防護素子の製造
工程を工程順に示す断面図。 (b) 比較例のサージ防護素子の製造工程を工程順に
示す断面図。
FIG. 1A is a cross-sectional view showing a manufacturing step of a surge protection element according to an embodiment of the present invention in the order of steps. (B) Sectional drawing which shows the manufacturing process of the surge protective element of a comparative example in order of a process.

【符号の説明】[Explanation of symbols]

10 シリコン基板(半導体基板) 10a エピタキシャル層 11 第1領域 12 第2領域 13 第3領域 14 第4領域 16 第1電極 17 第2電極 Reference Signs List 10 silicon substrate (semiconductor substrate) 10a epitaxial layer 11 first region 12 second region 13 third region 14 fourth region 16 first electrode 17 second electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H02H 9/04 ──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H02H 9/04

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型の半導体基板(10)の第1主面
の一部に前記基板より不純物濃度が高い第1導電型の第
1領域(11)を形成し、 前記第1領域(11)を含む前記半導体基板(10)の第1主面
全体に前記第1領域(11)より不純物濃度が低い第1導電
型の層(10a)を形成し、 前記層(10a)の表面から前記第1領域(11)と接合を有す
る深さに第2導電型の第2領域(12)を形成し、 前記半導体基板(10)の第2主面に前記第2領域(12)に対
向して第2導電型の第3領域(13)を形成し、 前記第2領域(12)内に第1導電型の第4領域(14)を形成
し、 前記第2領域(12)及び第4領域(14)にオーミック接触す
る第1電極(16)を形成し、 前記第3領域(13)にオーミック接触する第2電極(17)を
形成するサージ防護素子の製造方法。
A first conductive type first region having an impurity concentration higher than that of the first conductive type semiconductor substrate formed on a part of a first main surface of the first conductive type semiconductor substrate; Forming a first conductivity type layer (10a) having a lower impurity concentration than the first region (11) on the entire first main surface of the semiconductor substrate (10) including (11); and a surface of the layer (10a). A second region (12) of the second conductivity type is formed at a depth having a junction with the first region (11), and the second region (12) is formed on a second main surface of the semiconductor substrate (10). A third region (13) of the second conductivity type is formed facing the first region, a fourth region (14) of the first conductivity type is formed in the second region (12), and the second region (12) and A method for manufacturing a surge protection device, comprising: forming a first electrode (16) in ohmic contact with a fourth region (14); and forming a second electrode (17) in ohmic contact with the third region (13).
JP09298441A 1997-10-30 1997-10-30 Method of manufacturing surge protection element Expired - Fee Related JP3117005B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP09298441A JP3117005B2 (en) 1997-10-30 1997-10-30 Method of manufacturing surge protection element
TW087110982A TW373192B (en) 1997-10-30 1998-07-07 Method for fabricating surge protection device
KR1019980030881A KR19990036583A (en) 1997-10-30 1998-07-30 Manufacturing method of surge protection element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09298441A JP3117005B2 (en) 1997-10-30 1997-10-30 Method of manufacturing surge protection element

Publications (2)

Publication Number Publication Date
JPH11135808A true JPH11135808A (en) 1999-05-21
JP3117005B2 JP3117005B2 (en) 2000-12-11

Family

ID=17859757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09298441A Expired - Fee Related JP3117005B2 (en) 1997-10-30 1997-10-30 Method of manufacturing surge protection element

Country Status (3)

Country Link
JP (1) JP3117005B2 (en)
KR (1) KR19990036583A (en)
TW (1) TW373192B (en)

Also Published As

Publication number Publication date
KR19990036583A (en) 1999-05-25
TW373192B (en) 1999-11-01
JP3117005B2 (en) 2000-12-11

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