JPH11135741A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize the thickness of LOCOS films which are respectively formed at a memory cell part and a peripheral circuit part. SOLUTION: At a semiconductor device provided with a region, where the intervals between LOCOS films 6 adjacent to each other are small such as a memory cell part A and a region where the intervals between the films 6 adjacent to each other are large such as a peripheral circuit part B, the thickness of the LOCOS films respectively formed at a memory cell part A' and the part B re nearly equal through thermal oxidation by a LOCOS method in the state of implanting N-type impurity ions, such as arsenic ions or phosphorous ions, into only the LOCOS film forming region of the part A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device and a method of manufacturing the same. The present invention relates to a technology for reducing power consumption.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to the drawings. First, as shown in FIG. 8, about 500
After a pad oxide film 52 having a thickness of Å and a polysilicon film 53 having a thickness of about 700 形成 are formed, a film thickness of about 1500 有 す る having an opening on an element isolation film formation region described later on the polysilicon film 53 is formed. Is formed.

Subsequently, as shown in FIG. 9, LOCOS (local oxidation) is performed using the silicon nitride film 54 as a mask.
An LOCOS oxide film 55 as an element isolation film is formed by the (silicon) method. The condition of LOCOS oxidation at this time is as follows.
A COS oxide film 55 is formed. Next, as shown in FIG. 10, after removing the silicon nitride film 54, the polysilicon film 53, and the pad oxide film 52, the substrate is thermally oxidized as shown in FIG. After forming the gate oxide film 56 on the region, the LOC
For example, boron ions (11B +) are implanted as one conductivity type and P-type impurities under the implantation conditions penetrating the OS oxide film 55, and are implanted below the LOCOS oxide film 55 and deep below the channel region. Thus, the ions implanted below the LOCOS oxide film 55 form a channel stopper layer 57 for preventing inversion.

Subsequently, as shown in FIG. 12, a polysilicon film is formed in order to form a MOS transistor on each channel region of the memory cell portion and the peripheral circuit portion, and then the polysilicon film is patterned to form a gate electrode. After the formation of the gate electrode 59, an opposite conductivity type, for example, phosphorus ion (31P +) as an N-type impurity is provided adjacent to the end of the gate electrode 59.
Alternatively, arsenic ions (73 As @ +) are implanted into the surface of the substrate to form source / drain diffusion layers 60 and 61.

After that, an annealing process for activating the impurity ions is performed. Further, in actual LSI manufacturing, an insulating film, a contact hole,
Steps such as formation of the electrode wiring are continued. Although not particularly described, in order to adjust each threshold voltage of each N-channel MOS transistor, boron ions (11B +) or the like are implanted under each channel region to adjust the threshold voltage of each transistor. Is well known.

[0006]

However, in a semiconductor device having a memory cell section and a peripheral circuit section as described above, the LOCOS oxide film 55 is formed as shown in FIG. Are different from each other, and the space F1 of the memory cell portion A is smaller than the space F2 of the peripheral circuit portion B. This is because there is a demand to increase the degree of integration by arranging as many as possible of the same structure (for example, an N-type transistor structure) in the memory cell portion A,
This is because there is a restriction that it is necessary to widen the separation region for separating the N region.

In a semiconductor device having a dense region between adjacent element isolation films such as the memory cell portion A and a rough region between adjacent element isolation films such as the peripheral circuit portion B as described above, When F is different, the degree of growth of the LOCOS oxide film 55 is also different, and the thickness of the LOCOS oxide film 55 formed in the memory cell portion A on the narrow side (T1 (for example, 3200 °) shown in FIG. 10) is equal to that of the peripheral circuit. The thickness of the LOCOS oxide film 55 formed in the portion B (T2 shown in FIG. 10)
(For example, 3400 °)). If the thickness of the LOCOS oxide film 55 is small, there is a problem that a leak under the LOCOS oxide film 55 is likely to occur.

Therefore, conventionally, the oxidation time and the oxidation temperature are set based on the thickness T1 of the LOCOS oxide film 55 formed in the memory cell portion A. Therefore, the peripheral circuit section B
The thickness T2 of the LOCOS oxide film 55 to be formed becomes too thick, which hinders flattening. Therefore, an object of the present invention is to make the thickness of the LOCOS oxide film uniform, thereby enabling flattening.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has a structure in which a region between adjacent element isolation films such as a memory cell portion is dense and an adjacent region such as a peripheral circuit portion is adjacent. In a semiconductor device having a rough region between element isolation films, thermal oxidation is performed by a LOCOS method in a state where N-type impurity ions such as arsenic ions or phosphorus ions are implanted only into an element isolation film formation region of the memory cell portion. In this case, the element isolation films formed in the memory cell portion and the peripheral circuit portion are formed to have substantially the same thickness.

The present invention also relates to a method of manufacturing a semiconductor device having a dense region between adjacent device isolation films such as a memory cell portion and a rough region between adjacent device isolation films such as a peripheral circuit portion. Forming a silicon nitride film having an opening on a device isolation film forming region on a pad oxide film on a semiconductor substrate, and forming a photoresist film so as to cover the peripheral circuit portion; Then, N-type impurity ions such as arsenic ions or phosphorus ions are implanted into the interface between the substrate surface layer and the pad oxide film using the silicon nitride film as a mask. Next, after removing the photoresist film,
The entire surface is thermally oxidized by the LOCOS method to form an element isolation film, whereby the element isolation film formed in the memory cell portion is accelerated and oxidized to form an element isolation film formed in the memory cell portion and the peripheral circuit portion, respectively. It is characterized in that it is formed so as to have substantially the same thickness.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. First, as shown in FIG. 1, a pad oxide film 2 having a thickness of about 500.degree. And a polysilicon film 3 having a thickness of about 700.degree.
Is formed on the polysilicon film 3, a silicon nitride film 4 having an opening of about 1500.degree.

Subsequently, as shown in FIG. 2, after a photoresist film 5 is formed so as to cover the peripheral circuit portion B, a reverse conductivity type, for example, N Arsenic ion (73As +) as a type impurity
For example, at an acceleration voltage of 110 KeV and an injection amount of 5 × 10 15 /
By implanting under the condition of cm 2, it is implanted into the interface between the pad oxide film 2 and the substrate 1 in the memory cell portion. That is, the implantation is performed so that the impurity concentration on the substrate surface becomes highest. Incidentally, phosphorus ions (31P +) may be implanted instead of arsenic ions (73As +).

Next, LOCOS (local oxidation of s)
An LOCOS oxide film 6 as an element isolation film is formed by the silicon (ilicon) method. The condition of LOCOS oxidation at this time is 9
Pyro-oxidation at 00 ° C for 380 minutes gives LOCO
An S oxide film 6 is formed. The growth of the LOCOS oxide film 6 formed in the memory cell portion A is accelerated by the arsenic ions (73 As +) implanted at the interface between the pad oxide film 2 and the substrate 1 in the memory cell portion A. FIG. 7 is a graph showing the relationship between the acceleration rate of the LOCOS oxide film and the temperature when arsenic ions (73 As +) are implanted. As shown in FIG. When the injection is performed under the conditions, the pyro-oxidation is performed at 900 ° C., thereby performing the 6% accelerated oxidation. Therefore, when the LOCOS oxide film 6 of the memory cell portion A needs 3200 Å, the LOCOS oxide film 6 of the
When the angle is set to 0 °, the angle is conventionally 3000 °, but in the present embodiment, the speed can be increased by 6% of 3000 °, and as a result, 3 °
180 ° is obtained, and the film thickness of the LOCOS oxide film 6 in the memory cell portion A and the film thickness of the LOCOS oxide film 6 in the peripheral circuit portion B can be made substantially equal.

The LO formed in the memory cell portion A as described above
By increasing the speed of oxidation of the COS oxide film 6, the thickness of the LOCOS oxide film 6 formed in the memory cell portion A and the thickness of the LOCOS oxide film 6 formed in the peripheral circuit portion B are substantially equal as shown in FIG. (T1 (for example, 3200 °)), which has conventionally been caused by the difference between the thickness of the LOCOS oxide film formed in the peripheral circuit portion and the thickness of the LOCOS oxide film formed in the memory cell portion. Steps can be reduced. Incidentally, P-type impurity ions such as boron ion (11B +) and boron difluoride ion (47BF +) may be implanted, but N-type impurity ions can obtain a higher speed-up effect. This is because N-type impurity ions such as arsenic ions (73As +) and phosphorus ions (31P +) are implanted into the interface between the substrate (Si) and the pad oxide film (SiO2), and are deposited on the Si surface during the subsequent thermal oxidation. This is because a large amount of impurities gather and the Si surface to be oxidized is always in an impurity-rich state, and the speed is likely to increase. This is because P-type impurity ions such as boron ions (11B +) and boron difluoride ions (47BF +) are easily diffused into the SiO2 film, and the Si surface is in a state where impurities are insufficient.

Subsequently, as shown in FIG. 5, after removing the silicon nitride film 4, the polysilicon film 3, and the pad oxide film 2, the substrate is thermally oxidized to cover the channel region other than the LOCOS oxide film 6. After forming the gate oxide film 7, the LO
For example, boron ions (11B +) are implanted as one conductivity type and P-type impurities under the implantation conditions penetrating the COS oxide film 6, and are implanted below the LOCOS oxide film 6 and below the channel region. Thus, the ions implanted below the LOCOS oxide film 6 form a channel stopper layer 8 for preventing inversion.

Subsequently, as shown in FIG.
In order to form a MOS transistor on each channel region of the peripheral circuit section B, a polysilicon film is formed on a substrate, and then the polysilicon film is patterned to form a gate electrode 10, and an end of the gate electrode 10 is formed. N-type impurities (for example, phosphorus ions (11P +
), Arsenic ions (73As +), etc.)
The drain diffusion layers 11 and 12 are formed.

After that, an annealing process for activating the impurity ions is performed. Further, in the actual LSI fabrication, an insulating film, a contact hole,
Steps such as formation of the electrode wiring are continued. Although not particularly described, in order to adjust each threshold voltage of each N-channel MOS transistor, boron ions (11B +) or the like are implanted under each channel region to adjust the threshold voltage of each transistor. Is well known.

As described above, according to the present invention, the LOCOS oxide film 6 formed in the memory cell section A is accelerated and oxidized to increase the LOCOS oxide film 6 formed in the memory cell section A and the peripheral circuit section B. The film thickness can be made almost equal, and flattening can be achieved. Also, LO
The COS oxidation time can be shortened compared to the conventional art, so that the working time can be shortened and the oxidation time is shortened, so that the bird's peak amount is reduced and miniaturization can be achieved.

Further, the present invention can be applied to a CMOS transistor.

[0020]

As described above, according to the present invention,
By accelerating oxidation of the LOCOS oxide film formed in the memory cell portion, the thickness of the LOCOS oxide film formed in the memory cell portion and the thickness of the LOCOS oxide film formed in the peripheral circuit portion can be made substantially equal. In addition, it is possible to reduce the level difference which has conventionally occurred due to the difference between the thickness of the LOCOS oxide film formed in the peripheral circuit portion and the thickness of the LOCOS oxide film formed in the memory cell portion.

Further, since the LOCOS oxidation time can be shortened as compared with the conventional case, the working time can be shortened, and by shortening the oxidation time, the amount of bird's peak can be reduced and miniaturization can be achieved.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a diagram showing the relationship between acceleration and temperature when LOCOS oxidation is performed by implanting arsenic ions.

FIG. 8 is a first sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 9 is a second cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 10 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 11 is a fourth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 12 is a fifth sectional view illustrating the method for manufacturing the conventional semiconductor device.

Claims (4)

[Claims] 1. A semiconductor device having a dense region between adjacent device isolation films such as a memory cell portion and a rough region between adjacent device isolation films such as a peripheral circuit portion, wherein: And a device isolation film formed in each of the peripheral circuit portions having substantially the same thickness. 2. A method of manufacturing a semiconductor device having a dense region between adjacent element isolation films such as a memory cell portion and a rough region between adjacent element isolation films such as a peripheral circuit portion, When element isolation films are formed in the memory cell portion and the peripheral circuit portion by the LOCOS method, impurity ions are implanted only into the element isolation film formation region of the memory cell portion to increase the number of element isolation films formed in the memory cell portion. A method for manufacturing a semiconductor device, comprising forming an element isolation film formed in each of a memory cell portion and a peripheral circuit portion by rapid oxidation so as to have substantially the same thickness. 3. A method of manufacturing a semiconductor device having a region between adjacent element isolation films such as a memory cell portion and a rough region between adjacent element isolation films such as a peripheral circuit portion. Forming a silicon nitride film having an opening on a device isolation film formation region on a pad oxide film on a substrate; and forming the silicon nitride film on the memory cell portion after forming a photoresist film so as to cover the peripheral circuit portion. Implanting impurity ions into the interface between the substrate surface layer and the pad oxide film using the film as a mask, and forming a device isolation film by thermally oxidizing the entire surface by the LOCOS method after removing the photoresist film. A device isolation film formed in the memory cell portion and the peripheral circuit portion are formed so that the film thicknesses of the device isolation films formed in the memory cell portion and the peripheral circuit portion are substantially equal. Manufacturing method of a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 2, wherein said impurity ions are N-type impurities such as phosphorus ions or arsenic ions.