JPH11135499A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is constituted to prevent dielectric breakdown caused by charge up during patterning of a first layer metallic wiring in its electrical stray state by RIE without being affected by restriction on pattern layout or on circuit characteristic, and a manufacture method. SOLUTION: In a manufacturing method of a semiconductor device, a discharge diffusion layer 7 is formed in an arbitrary position near a surface of a semiconductor board, and a first layer metallic wiring 5 is formed by patterning a first layer metallic wiring layer 1 by reactive ion etching after a part of the first layer metallic wiring layer 1 which is to be connected to only an electrode in its electrical stray state is connected also to the discharge diffusion layer 7 electrically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to reactive ion etching (RI).
E: Reactive Ion Etching) is suitable for preventing element destruction due to charge-up in a process.

[0002]

2. Description of the Related Art When a semiconductor device has a structure having a multilayer metal wiring made of a metal such as aluminum, etching for patterning the metal wiring of each layer including a first layer is performed by reactive ion etching (RIE). Reactive
Ion Etching).

FIG. 6 is an explanatory view schematically showing a structure of a semiconductor device in an RIE step in a conventional method of manufacturing a semiconductor device.

[0004] N ⁺ type diffusion layer 2 at a predetermined position on the semiconductor substrate surface P-type well 1, which is formed in the vicinity is formed, N ⁺
One end of a first-layer metal wiring 4 made of a metal such as aluminum is connected to the mold diffusion layer 2. The first-layer metal wiring 4 includes a gate electrode 3 made of polysilicon or the like at the other end.
Some are connected. There is also a first-layer metal wiring 5 connected only to the gate electrode 6 in an electrically floating state.

However, when the first-layer metal wiring 5 connected only to the floating gate electrode 6 is present during the RIE process, the charge of the first-layer metal wiring 5 and the floating gate electrode 6 connected to the same is present. The floating gate electrode 6
A high voltage is applied to the interlayer insulating film 9 existing between the gate electrode 3 and another gate electrode 3 or the substrate, and a dielectric breakdown failure occurs. FIG. 7 is an explanatory diagram schematically showing a structure of a conventional semiconductor device having a structure for preventing dielectric breakdown caused by charge-up in an RIE process.

Conventionally, in order to prevent dielectric breakdown of the interlayer insulating film due to charge-up of the first-layer metal wiring 5 and the floating gate electrode 6 connected thereto, as shown in FIG. By pattern-designing the first-layer metal wiring 5 connected to the gate electrode 6 so as to be connected to the diffusion layer 2 of the input protection circuit via the gate electrode 10,
Measures have been taken to discharge the charge that is charged up.

[0007]

However, a method for preventing charge-up by designing a pattern such that the first-layer metal wiring 5 connected to the floating gate electrode 6 is connected to the diffusion layer 2 of the input protection circuit is disclosed. Had the following problems. That is, restrictions on the pattern layout, such as when another wiring is formed above, below, or around the floating gate electrode 6 and the first layer metal wiring, or when the gate electrode 10 is connected to the diffusion layer 2 of the input protection circuit. Due to restrictions on circuit characteristics such as an increase in signal propagation delay time due to the insertion of the above, there are many cases where the above method cannot be performed, and it has been difficult to prevent complete charge-up.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce a dielectric breakdown caused by charge-up in patterning a first-layer metal wiring in an electrically floating state by RIE. An object of the present invention is to provide a semiconductor device having a configuration that can be prevented without being restricted by the above or circuit characteristics, and a method of manufacturing the same.

[0009]

According to a method of manufacturing a semiconductor device according to the present invention, a discharge diffusion layer is formed at an arbitrary position near the surface of a semiconductor substrate, and is connected only to an electrode in an electrically floating state. After electrically connecting a portion of the first metal wiring layer to be formed to the diffusion layer for discharge, the first metal wiring layer is patterned by reactive ion etching to form the first metal wiring layer.
This configuration is characterized in that a layer metal wiring is formed. With this configuration, dielectric breakdown due to charge-up when patterning the first layer metal wiring in an electrically floating state by RIE is reduced on a pattern layout or a circuit characteristic. A method for manufacturing a semiconductor device having a configuration that can be prevented without being restricted can be provided.

More specifically, a method of manufacturing a semiconductor device according to the present invention includes a first step of forming a discharge diffusion layer at an arbitrary position near the surface of a semiconductor substrate, and a first interlayer insulating film on the semiconductor substrate. A second step of forming a film; a third step of forming an electrode on the first interlayer insulating film; a fourth step of forming a second interlayer insulating film covering the electrode; The first metal wiring layer, which is to be connected only to the electrode in an electrically floating state, is electrically connected to the discharge diffusion layer at a predetermined position of the second interlayer insulating film. A fifth step of opening a contact hole, a sixth step of forming a first metal wiring layer on the second interlayer insulating film, and a fifth step of patterning the first metal wiring layer by reactive ion etching. And a seventh step of forming a single-layer metal wiring.

In the case where the connection between the first metal wiring and the diffusion layer for discharge has an effect on circuit characteristics,
It is preferable that the method further includes a sixth step of disconnecting the connection between the first-layer metal wiring and the discharge diffusion layer.

According to the semiconductor device of the present invention, the discharge diffusion layer formed at an arbitrary position near the semiconductor substrate surface, the first interlayer insulating film formed on the semiconductor substrate, and the first interlayer insulating film are formed. An electrode formed on the insulating film, a second interlayer insulating film formed over the electrode, and an electrode which is connected only to the electrode in an electrically floating state and electrically connected to the discharge diffusion layer. And a first-layer metal wiring connected to the first layer.
It is possible to provide a semiconductor device having a configuration capable of preventing dielectric breakdown due to charge-up when patterning a layer metal wiring by RIE without being restricted by pattern layout or circuit characteristics.

The first-layer metal wiring is preferably made of aluminum.

The discharge diffusion layer is preferably an N ⁺ -type diffusion layer formed in a P-type well formed near the surface of the semiconductor substrate.

[0015]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view of a semiconductor device according to the present invention.

The semiconductor device according to the present invention shown in FIG. 1 is configured as follows.

The N ⁺ -type diffusion layer 2 at a predetermined position on the semiconductor substrate surface P-type well 1, which is formed in the vicinity is formed, N ⁺
One end of a first-layer metal wiring 4 made of a metal such as aluminum is connected to the mold diffusion layer 2. The first-layer metal wiring 4 includes a gate electrode 3 made of polysilicon or the like at the other end.
Some are connected. There is also a first-layer metal wiring 5 connected only to the gate electrode 6 in an electrically floating state.

As described above, when performing the RIE process, the first layer metal wiring 5 connected only to the floating gate electrode 6 is formed.
Is present, a high voltage is applied to the interlayer insulating film existing between the floating gate electrode 6 and another gate electrode 3 or the substrate due to the charge-up of the first layer metal wiring 5 and the floating gate electrode 6 connected thereto. Is applied, and dielectric breakdown failure occurs.

Therefore, in the semiconductor device according to the present invention, the discharge diffusion layer 7 is formed at an arbitrary position in advance, and the first-layer metal wiring 5 is electrically connected to the discharge diffusion layer 7. Thereby, when performing RIE, the first layer metal wiring 5
Since the charge to the floating gate electrode 6 connected thereto is discharged to the discharge diffusion layer 7, it is possible to prevent dielectric breakdown failure of the surrounding interlayer insulating film. In the case of the semiconductor device according to the present invention, the discharge diffusion layer 7 may be formed at any convenient position for connecting the first-layer metal wiring.
The present invention can be implemented as long as an area for forming the discharge diffusion layer 7 can be ensured, so that there is no restriction on pattern layout or circuit characteristics.

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described.

2 to 4 are sectional structural views of the semiconductor device in respective manufacturing steps of the method for manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 2, N is placed at a predetermined position in a P-type well 1 formed near the surface of a semiconductor substrate.
^{The +} type diffusion layer 2 and the discharge diffusion layer 7 are formed at an arbitrary position. Here, since the discharge diffusion layer 7 is formed in the P-type well 1, the discharge diffusion layer 7 is an N ⁺ -type diffusion layer. The N ⁺ type diffusion layer 2
Although formed at a predetermined position in the structure of the semiconductor integrated circuit, the discharge diffusion layer 7 is convenient for connecting the first-layer metal wiring that is connected only to the gate electrode in an electrically floating state. Form at any position. Next, as shown in FIG. 3, a first layer gate electrode 6 made of polysilicon or the like is formed, and a second layer gate electrode 3 made of polysilicon or the like is formed via an interlayer insulating film.

Further, an interlayer insulating film is formed on the second-layer gate electrode 3, a contact hole is opened at a predetermined position in the interlayer insulating film, and a first-layer metal wiring layer 11 is formed on the entire surface. At this time, a contact hole is also opened in the interlayer insulating film on the discharge diffusion layer 7 so that the first metal wiring layer 11 is connected to the discharge diffusion layer 7 via the contact hole. Thereafter, the first metal wiring layer 11 is patterned into a predetermined shape by the RIE process to form the first metal wiring layers 4 and 5, whereby the semiconductor device according to the present invention shown in FIG. 1 is completed.

FIG. 5 is a plan view showing the structure of the semiconductor device according to the present invention.

As shown in FIG. 5, a discharge diffusion layer 7 is formed in advance at a position below the other end of the first-layer metal wiring 5 having one end connected to the floating gate electrode 6, and RIE is performed. In forming the first-layer metal wiring before the process, the first-layer metal wiring 5 is electrically connected to the discharge diffusion layer 7.
Therefore, even when the first layer metal wiring 5 and the floating gate electrode 6 are surrounded by another electrode wiring 8,
The method for manufacturing a semiconductor device according to the present invention is feasible,
It is possible to prevent dielectric breakdown failure of the surrounding interlayer insulating film due to charge-up of the first layer metal wiring 5 and the floating gate electrode 6. Further, even if the first-layer metal wiring 5 is connected to the discharge diffusion layer 7, the wiring resistance of the first-layer metal wiring 5 does not change. Therefore, even when the distance to the input protection circuit is large,
There is almost no effect on circuit characteristics such as an increase in signal propagation delay time.

If the circuit characteristics are affected if the first-layer metal wiring 5 and the discharge diffusion layer 7 are kept connected, the first-layer metal wiring 5 and the discharge diffusion layer 7 may be connected after the RIE process. It is preferable to disconnect the connection with the layer 7.

The conductivity type of the discharge diffusion layer 7 may be either P-type or N-type depending on the structure of the semiconductor device.
The material of the layer metal wiring may be a material other than aluminum.

[0029]

According to the method of manufacturing a semiconductor device according to the present invention, a discharge diffusion layer is formed at an arbitrary position near the surface of a semiconductor substrate, and is connected only to an electrode in an electrically floating state. Since the first metal wiring layer was electrically connected to the discharge diffusion layer, the first metal wiring layer was patterned by reactive ion etching to form the first metal wiring. A structure capable of preventing dielectric breakdown due to charge-up when patterning a first-layer metal wiring in an electrically floating state by RIE without being restricted by pattern layout or circuit characteristics. A method for manufacturing a semiconductor device can be provided.

According to the semiconductor device of the present invention, the first-layer metal wiring connected only to the electrode in an electrically floating state among the electrodes is also electrically connected to the discharge diffusion layer. RIE for the first layer metal wiring in an electrically floating state
Accordingly, it is possible to provide a semiconductor device having a configuration capable of preventing dielectric breakdown due to charge-up during patterning without being restricted by pattern layout or circuit characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to the present invention.

FIG. 2 is a sectional structural view of the semiconductor device in one manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional structural view of the semiconductor device in one manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional structural view of the semiconductor device in one manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a plan view showing the structure of a semiconductor device according to the present invention.

FIG. 6 is an explanatory view schematically showing a structure of a semiconductor device in an RIE step in a conventional method of manufacturing a semiconductor device.

FIG. 7 is an explanatory view schematically showing a structure of a conventional semiconductor device having a structure for preventing dielectric breakdown caused by charge-up in an RIE process.

[Explanation of symbols]

Reference Signs List 1 P-type well 2 N ⁺ -type diffusion layer 3, 10 Gate electrode 4 First-layer metal wiring 5 First-layer metal wiring connected to floating gate electrode 6 Floating gate electrode 7 Discharge diffusion layer 8 Other electrode wiring 9 Interlayer Insulating film 11 First layer metal wiring layer

Claims (8)

[Claims] 1. A discharge diffusion layer is formed at an arbitrary position near the surface of a semiconductor substrate, and a portion of a first metal wiring layer to be connected only to an electrode in an electrically floating state is formed by the discharge diffusion layer. After being electrically connected to the first metal wiring layer, the first metal wiring layer is patterned by reactive ion etching to form a first metal wiring layer.
A method for manufacturing a semiconductor device, comprising forming a layer metal wiring. 2. A first step of forming a discharge diffusion layer at an arbitrary position near the surface of a semiconductor substrate; a second step of forming a first interlayer insulating film on the semiconductor substrate; A third step of forming an electrode on the interlayer insulating film, a fourth step of forming a second interlayer insulating film covering the electrode, and connecting only to the electrode in the electrode in an electrically floating state Forming a contact hole at a predetermined position in the second interlayer insulating film so that a portion of the first metal wiring layer to be formed is also electrically connected to the discharge diffusion layer; A step of forming the first metal wiring layer on the second interlayer insulating film; and patterning the first metal wiring layer by reactive ion etching to form the first metal wiring. Forming a seventh step of forming a semiconductor device. Production method. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising an eighth step of cutting off a connection between said first metal wiring and said diffusion layer for discharge. A method for manufacturing a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said first-layer metal wiring is made of aluminum. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said discharge diffusion layer is formed in an N ⁺ -type well formed in a P-type well formed near a surface of said semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is a diffusion layer. 6. A discharge diffusion layer formed at an arbitrary position near the surface of the semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate, and formed on the first interlayer insulating film. And a second interlayer insulating film formed over the electrode, and connected only to the electrode in an electrically floating state among the electrodes, and also electrically connected to the discharge diffusion layer. A first-layer metal wiring. 7. The semiconductor device according to claim 6, wherein said first layer metal wiring is made of aluminum. 8. The semiconductor device according to claim 6, wherein the discharge diffusion layer is an N ⁺ type diffusion layer formed in a P type well formed near the surface of the semiconductor substrate. A semiconductor device, comprising: