JP2001358143A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of a gate insulating film caused by electric charges in a process of etching metal wiring layer and to prevent the generation of leakage current in a semiconductor device. SOLUTION: The semiconductor device is equipped with a semiconductor substrate 1, gate electrodes 3, an impurity diffusion region 4, at least a wiring layer 6 formed through the intermediary of an interlayer insulating film 5, containing relay pins connected electrically to the gate electrodes 3, and an uppermost wiring layer 8 formed through the intermediary of an interlayer insulating film 7, containing wiring patterns which are electrically connected to the relay pins respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a gate array, an embedded array, a standard cell and the like including a logic circuit portion designed using various cells in accordance with specifications of a supplier. Semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device such as a gate array, a wiring pattern of a transistor included in a cell is formed of several layers of metal laminated on a semiconductor substrate on which the transistor is formed via an interlayer insulating film. ing.
Conventionally, since the metal upper layer is used for wiring between cells,
The wiring in the cell was formed by the lower layer metal as much as possible. Such a conventional semiconductor device will be described with reference to FIG.

FIGS. 2A and 2B are views showing a part of a wiring pattern in a conventional semiconductor device, FIG. 2A is a plan view, and FIG.
FIG. 4A is a cross-sectional view taken along the line BB ′ of FIG. In FIG. 2A, the insulating film is omitted. A gate electrode 3 is formed on a semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. Next, the semiconductor substrates 1 on both sides of the gate electrode 3
Inside, an impurity diffusion region 4 serving as a source / drain is formed. These constitute the transistors Q1 and Q2.

[0004] A first interlayer insulating film 5 is formed on the semiconductor substrate 1 on which the transistor is formed, and an opening is provided in a predetermined portion of the first interlayer insulating film 5. Then, the first
A first wiring layer 6 is provided on the interlayer insulating film 5, and a desired wiring is patterned by etching. A part of the first wiring layer 6 is connected to the gate electrode 3 and the impurity diffusion region 4 through the opening of the first interlayer insulating film 5.

Next, a second interlayer insulating film 7 is formed on the semiconductor substrate 1 on which the first wiring layer 6 is formed, and an opening is provided in a predetermined portion of the second interlayer insulating film 7. continue,
A second wiring layer 8 is provided on the second interlayer insulating film 7;
A desired wiring is patterned by etching. Part of the second wiring layer 8 is connected to the first wiring layer 6 through an opening in the second interlayer insulating film 7.

Here, the first wiring layer 6 has three portions 6a.
~ 6c. The first part 6a is connected to the source or the drain of the transistor Q1, and the third part 6c is connected to the gate electrode of the transistor Q2. The second portion between the first portion 6a and the third portion 6c
Since the wiring by the portion 6b is provided, the first portion 6a and the third portion 6c cannot be directly connected, and they are connected via the second wiring layer 8.

[0007]

In recent years, the thickness of a gate insulating film has been reduced along with miniaturization of a transistor, and deterioration of the gate insulating film due to charge charging in a metal wiring layer etching process has been a problem. Has become. When the wiring to the gate electrode is formed of a lower metal layer as in the prior art, the third wiring of the first wiring layer 6 shown in FIG.
A long wiring like the portion 6c is connected to the gate electrode 3, but this portion is in a floating state until the second wiring layer 8 is formed, and a path for releasing charges in the etching process of the metal wiring layer is not provided. not exist. Therefore, when the first wiring layer 6 is etched to form a pattern of the third portion 6c, charges generated by the etching are transferred to the third portion 6c and the gate electrode 3 connected thereto.
Is accumulated in Such a phenomenon that charges are accumulated in a long wiring is called an antenna effect.

If the amount of electric charge accumulated in the gate electrode 3 increases due to the antenna effect, the insulation of the gate insulating film 2 is broken, and the gate insulating film is deteriorated, which causes a problem of causing a leak current. there were. Moreover,
In the current layout design method using automatic placement and wiring, it is difficult to control the wiring length for the process charge.

In view of the above, an object of the present invention is to provide a semiconductor device having a structure capable of preventing deterioration of a gate insulating film and generation of a leak current due to charge charging in a step of etching a metal wiring layer. That is.

[0010]

In order to solve the above problems, a semiconductor device according to the present invention comprises a semiconductor substrate, a plurality of gate electrodes formed on the semiconductor substrate via a gate insulating film, and An impurity diffusion region formed in the semiconductor substrate on both sides of the gate electrode and constituting a plurality of transistors; and at least one wiring layer formed on the semiconductor substrate on which the gate electrode is formed via an interlayer insulating film. hand,
A semiconductor substrate having at least one wiring layer and at least one wiring layer including a plurality of relay pins electrically connected to the plurality of gate electrodes, respectively, is formed via an interlayer insulating film. An uppermost wiring layer including a plurality of wiring patterns electrically connected to the plurality of relay pins, respectively.

Here, it is desirable that the plurality of gate electrodes be connected to the impurity diffusion region of any of the transistors via the plurality of relay pins and the plurality of wiring patterns. Further, it is desirable that the length of each side of the relay pin parallel to the main surface of the semiconductor substrate has a minimum value that can be opened in processing the interlayer insulating film in the manufacturing process.

According to the semiconductor device of the present invention having the above-described structure, the wiring of the gate electrode is performed by using the wiring pattern of the uppermost layer by connecting the relay pin to the gate electrode. In this case, the wiring pattern is always electrically connected to the impurity forming region or the like. Thus, the charge in the etching step of the metal wiring layer is released to a region other than the gate electrode, so that deterioration of the gate insulating film and generation of a leak current can be prevented.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B are diagrams showing a part of a wiring pattern in a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG.
It is sectional drawing in A '. In FIG. 1A, the insulating film is omitted.

A gate electrode 3 is formed on a semiconductor substrate 1 such as silicon with a gate insulating film 2 interposed therebetween. The gate insulating film 2 is formed of, for example, a silicon oxide film or a silicon nitride film. The gate electrode 3 is formed, for example, by adding impurities to polysilicon. Next, an impurity diffusion region 4 serving as a source / drain is formed in the semiconductor substrate 1 on both sides of the gate electrode 3. These constitute the transistors Q1 and Q2.

A first interlayer insulating film 5 is formed on semiconductor substrate 1 on which the transistor is formed, and an opening is provided in a predetermined portion of first interlayer insulating film 5. Then, the first
A first wiring layer 6 is provided on the interlayer insulating film 5, and a desired wiring is patterned by etching. Generally, metal such as aluminum is used for the wiring layer. A part of the first wiring layer 6 is connected to the gate electrode 3 and the impurity diffusion region 4 through the opening of the first interlayer insulating film 5.

The first wiring layer 6 includes four portions 6a to 6d
Contains. The first portion 6a is connected to the gate electrode of the transistor Q1, and the second portion 6b is connected to the source or drain of the transistor Q1.
6d is connected to the gate electrode of the transistor Q2. Here, the first portion 6a and the fourth portion 6d connected to the gate electrodes of the transistors Q1 and Q2 respectively serve as relay pins for connecting the gate electrode of the transistor to the uppermost wiring. . Since these relay pins are not used for wiring in the first wiring layer 6, they need only have a minimum necessary area. Specifically, it is desirable that the length of each side of the relay pin parallel to the main surface of the semiconductor substrate has a minimum value that can be opened in processing the interlayer insulating film in the manufacturing process. Accordingly, the gate insulating film is hardly affected by the above-described antenna effect, and the gate insulating film is not broken down by the electric charge charged to the relay pin in the etching step of the first wiring layer 6.

Next, a second interlayer insulating film 7 is formed on the semiconductor substrate 1 on which the first wiring layer 6 is formed, and an opening is provided in a predetermined portion of the second interlayer insulating film 7. continue,
Second wiring layer 8 as the uppermost layer on second interlayer insulating film 7
Is provided, and a desired wiring is patterned by etching. The second wiring layer 8 includes a first portion 8a connected to the gate electrode of the transistor Q1 via the first wiring layer 6, and a source / drain and a transistor of the transistor Q1 via the first wiring layer 6. A second portion 8b connected to the gate electrode of Q2. Here, the first portion 8a and the second portion 8b which are electrically connected to the gate electrodes of the transistors Q1 and Q2, respectively, are wiring patterns for electrically connecting the gate electrodes of the transistors to other regions. It is. In the present invention, since the wiring pattern is formed on the uppermost layer, when the wiring pattern is connected to the gate electrode of the transistor, it is always connected to the source or drain of any of the transistors. Therefore, in the etching step of the second wiring layer 8, even if the electric charge is charged in the wiring pattern, the electric charge can escape to the semiconductor substrate or the ground potential via the source or the drain of any of the transistors. In addition, the dielectric breakdown of the gate insulating film does not occur.

In the above embodiment, the case where the number of wiring layers is two has been described, but the present invention is not limited to this.
The present invention can be applied to a semiconductor device having general multilayer wiring. Generally, when there are N wiring layers (N is an integer of 2 or more), relay pins electrically connected to the gate electrode are provided in the first to (N-1) th wiring layers. The wiring pattern electrically connected to the relay pin may be provided in the N-th wiring layer, which is the uppermost layer.

[0019]

As described above, according to the present invention, the wiring of the gate electrode is performed using the wiring pattern of the uppermost layer by connecting the relay pin to the gate electrode. The wiring pattern is always electrically connected to the impurity forming region or the like. Thus, the charge in the etching step of the metal wiring layer is released to a region other than the gate electrode, so that deterioration of the gate insulating film and generation of a leak current can be prevented.

[Brief description of the drawings]

FIG. 1 is a view showing a part of a wiring pattern in a semiconductor device according to an embodiment of the present invention, FIG.
FIG. 2B is a cross-sectional view taken along line AA ′ of FIG.

FIGS. 2A and 2B are diagrams showing a part of a wiring pattern in a conventional semiconductor device, wherein FIG. 2A is a plan view and FIG.
It is sectional drawing in -B '.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 gate insulating film 3 gate electrode 4 impurity diffusion region 5 first interlayer insulating film 6 first wiring layer 7 second interlayer insulating film 8 second wiring layer Q1, Q2 transistor

Claims (3)

[Claims] 1. A semiconductor substrate; a plurality of gate electrodes formed on the semiconductor substrate via a gate insulating film; and a plurality of transistors formed in the semiconductor substrate on both sides of each gate electrode. An impurity diffusion region; and at least one wiring layer formed on the semiconductor substrate on which the gate electrode is formed via an interlayer insulating film,
A plurality of relay pins electrically connected to the plurality of gate electrodes, the at least one wiring layer, and a semiconductor substrate on which the at least one wiring layer is formed via an interlayer insulating film A top wiring layer formed, the top wiring layer including a plurality of wiring patterns electrically connected to the plurality of relay pins, respectively. . 2. The semiconductor according to claim 1, wherein the plurality of gate electrodes are connected to an impurity diffusion region of any one of the transistors via the plurality of relay pins and the plurality of wiring patterns. apparatus. 3. The semiconductor device according to claim 1, wherein the length of each side of the relay pin parallel to the main surface of the semiconductor substrate is a minimum value that can be opened in processing the interlayer insulating film in a manufacturing process. 3. The semiconductor device according to 2.