JPH11134882A - Nonvolatile multi-value memory and method of writing data therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the write conditions in a nonvolatile multi-value memory. SOLUTION: During writing a multiplexer circuit 46 changes the selection according to input data D0 and D1 when a write enable signal WRIEN 2 is inputted. When the data D0, D1 are '0, 0', a multiplexer 45 feeds an array ground ARYGND to bit lines to result in that the write condition of selected memory cell 60 does not hold. When the data D0, D1 are other than '0, 0', the multiplexer 46 selects an input/output line 30 to write data corresponding to the input analog amt. in the memory cell 60.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile memory device using an EEPROM or the like capable of storing multi-value information and a writing method thereof.

[0002]

2. Description of the Related Art EEPR with floating gate
2. Description of the Related Art In a nonvolatile memory such as an OM, it has been conventionally performed to control the amount of charge injected into a floating gate to change its threshold level and store an analog amount in a memory cell.

For example, in Japanese Patent Application Laid-Open No. 09-69295, when writing multi-valued information according to input data in a nonvolatile multi-valued memory cell, the multi-valued information is efficiently written. The nonvolatile memory is divided into first and second memory arrays each including a plurality of memory cells, and first and second read / write circuits for controlling reading and writing of each memory array are provided. First, data to be written is latched by the first read / write circuit. Thereafter, the first read / write circuit simultaneously writes the latched data in the first memory array. At the same time, the next write data is latched by the second read / write circuit. Then, the second read / write circuit simultaneously writes the latched data in the second memory array, and simultaneously causes the first read / write circuit to latch the next data.

As described above, in the first and second read / write circuits, since the data latch operation and the write operation are performed alternately, the write operation has been efficiently executed without making any idle time.

[0005]

SUMMARY OF THE INVENTION First and second prior art examples
The memory cell is further divided into a plurality of blocks in a predetermined unit. In one memory cell where writing is performed, actual data writing is not performed in all of the plurality of blocks, and writing is performed by actually injecting charges according to multi-valued information into the floating gate of the memory cell. In some blocks, the data is erased from the memory cell by not injecting electric charge into the floating gate, so that “0, 0” (data D
There is also a block in which data of (0, D1) is written.
In the block in which the data of "0, 0" is written, the write is stopped in which the voltage is applied to the source, drain and control gate of the memory cell so that no charge is injected into the floating gate. However, in a memory cell array where writing is performed,
A voltage is applied to the electrodes of any of the memory cells from the same read / write circuit. Therefore, for example, there is a problem that the output control voltage of the read / write circuit fluctuates and charges are erroneously injected into a memory cell in which data “0, 0” is written. Therefore, there is a problem that when data is written to the nonvolatile memory cell, the writing accuracy is reduced.

[0006]

According to the present invention, there are provided first and second nonvolatile memory cells each capable of storing multi-valued information.
A memory cell array, a write circuit for writing multilevel information to one of the first and second memory cell arrays, and a latch for latching data to be written to the other memory cell while the write circuit is operating And a control circuit for controlling a state of a memory cell to which writing is not performed so as to be independent of a state at the time of writing.

Further, the control circuit connects a bit line of a memory cell in the memory cell array to which writing is not performed to an array ground obtained from an independent voltage source. Further, the writing circuit alternately writes multi-valued information to the first and second memory cell arrays.

Still further, in a nonvolatile multilevel memory device provided with first and second memory cells comprising a plurality of nonvolatile memory cells capable of storing multilevel information, one of the first and second memory cell arrays is provided. It is characterized in that multi-valued information is written to a memory cell array, data to be written to the other memory cell is latched during a write operation, and a state of a memory cell to which writing is not performed is controlled to a state independent of writing. I do.

According to the present invention, when one memory cell array is performing a write operation, the other memory cell array does not perform a write operation and latches data to be written next. Since the memory cell array where writing is not performed is in a state independent of the time of writing, the memory cell array is in a stable state, and it is prevented that charges are erroneously written.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention including a read / write circuit of a memory cell. FIG.
In the figure, reference numeral 20 denotes a 2-bit data register which is constituted by a D flip-flop and fetches and holds 2-bit input data, and 21 denotes a reference voltage Vref of V1 to V4 (V1
<V2 <V3 <V4) A resistance dividing circuit that divides the voltage into four voltages, a decoder 22 that decodes the contents of the data register 20 and selectively outputs any one of V1 to V4 according to the contents. 23 inputs the analog voltage Vdec output from the decoder 22 to the non-inverting terminal +,
A comparator 24 inputs the voltage Vm read from the memory cell 60 of the ROM 6 to the inverting terminal and compares the two voltages. The comparator 24 is a period comparator 2 when the timing clock RWCK4 is at the H level.
The latch circuit 25 outputs the output of the comparator 3 as it is, latches the output of the comparator when it falls to the L level, and sends out the output latched during the L level.
Is an output buffer for outputting the contents of further,
The resistance divider circuit 21 and the decoder 22 constitute a second DA converter.

The memory cell 60 of the EEPROM 6 is a split gate type cell having a floating gate FG, and performs writing by injecting electric charge into the floating gate FG to perform writing.
The erase is performed by extracting the charge injected into G. Each memory cell 60 has its drain D connected to bit lines BL1, BL2,..., Its source S connected to source lines SL1, SL2,..., And its control gate CG connected to word lines WL1, WL2,.
It is connected to the. Each bit line BL1, BL2,.
Are connected to the inverting terminal of the comparator 23 by selecting one of the lines by the X address decoder 100 that decodes the upper 4 bits of the X address ADRX [8: 6]. The source lines SL1, SL2,... Are connected to Y address decoders 200 and 250 for decoding an 11-bit Y address [10: 0], respectively. Various bias voltages are supplied from the second bias generation circuit 400. The bias voltage includes a high voltage bias Vhv1 for writing and a high voltage bias Vhv2 for erasing.
It is included.

The address decoders 100, 200, 2
50 has RWCK3 and RWCK as timing signals.
4, WBE is input. The terms drain and source here are based on the operating state at the time of reading. Three kinds of bias voltages VBH, VBLH, VBLL (VBH
>VBLH> VBLL) are output from the first bias generation circuit 500, and the supply lines for these bias voltages are respectively connected to the P-channel MOS transistors 2 as switches.
6, N channel MOS transistor 27, N channel M
An OS transistor 28 is inserted. An analog switch 29 that is turned on only at the time of writing is connected to the output side of these transistors. The output of the analog switch 29 is connected to an input / output line 30 to the X address decoder 100. The output C of the latch circuit 24 is connected to one end of the gate of the P-channel MOS transistor 26.
The output of the AND gate 31 for inputting the OMP is applied,
Outputs of AND gates 32 and 33 are applied to N-channel MOS transistors 27 and 28, respectively. A
The ND gates 32 and 33 have an AND gate 31 at one end.
Is input in common, a signal obtained by inverting the output upper bit D1 of the data register 20 by the inverter 34 is input to the other end of the AND gate 32, and the other end of the data register 20 is The output upper bit D1 is input as it is.

In order to read out the analog amount written in the memory cell 60 as a voltage, a read bias generating circuit 35 constituted by a resistance dividing circuit is provided, and the voltage dividing point P is turned on only at the time of comparison. N-channel MO
Via the S transistor 36, the X address decoder 10
0 is connected to the input / output line 30. An N-channel MOS transistor 37 that is turned on by a control signal WBE is inserted between the input / output line 30 and the ground to supply a ground potential to the bit lines BL1, BL2,.

The read / write circuit shown in FIG. 1 manages eight memory cells as one block in the X address direction, and each block includes a block for detecting that its own block is selected. Selector 600
Is arranged. Block No. shown in FIG. In the block of 0, the block selector 600 is configured by an AND gate that detects that the lower 6 bits of the X address ADRX [5: 0] are all “0”.

In FIG. 1, reference numeral 38 denotes an NA for inputting the data transfer clock RWCK2, the latch enable signal LATEN, and the output BSEL of the block selector 600.
An ND gate 39 is a NAND gate for inputting the timing clock RWCK3, the read enable signal REAEN2 and the output COMP, and 40 is a block selector 600
, A NAND gate for inputting the outputs of the two NAND gates 38 and 39, a AND gate 42 for inputting the timing clock RWCK3 and the write enable signal WREN2, and a reference numeral 43 for Read enable signal REAEN2 and write enable signal WR
An OR gate 44 for inputting IEN2 and an AN 44 for inputting the timing clock RWCK4 and the output of the OR gate 43
A D gate, the output of the NAND gate 41 is applied to the clock terminal of a D flip-flop constituting the data register 20, the output of the NAND gate 40 is applied as an on / off control signal of the output buffer 25, and the AND gate 4
2 is applied as an on / off control signal for the analog switch 29, and the output of the AND gate 44 is applied to the N-channel MO.
The voltage is applied to the gate of the S transistor 36.

Reference numeral 46 denotes input data D1 and D0 from the data register 20 and a read enable signal RE.
Depending on the values of AEN2 and write enable signal WREN2, input / output line 30 or array ground AR
A multiplexer circuit for selecting any one of YGND. Hereinafter, a write operation and a read operation of the read / write circuit of FIG. 1 will be described with reference to timing charts of FIGS. 7 and 8. The bias condition in each operation state of the memory cell 60 is as shown in FIG.

First, prior to a write operation, a latch mode for latching data in the data register 20 is entered. In this mode, 2-bit digital data D1,
D0 is sent to the input line 45, and the addresses ADRX and ADR of the EEPROM 6 to which data is to be written.
Y is sent from the address generation circuit 10, and the signal LATEN indicating the latch mode goes high. The lower 6 bits ADRX [5: 0] of the output X address
Has its own block NO. When the sampling time RWCK2 rises, the output of the NAND gate 38 becomes L level, and the output of the NAND gate 41 also becomes L level. Therefore, a clock is applied to the clock terminal CK of the D flip-flop constituting the data register 20, and the input data D1 and D0 are taken into the data register 20.

When the capture is completed, the signal WBE goes high, the N-channel MOS transistor 37 is turned on, and the input / output line 30 is set to the ground potential 0V. In the X address decoder 100, since the bit line selected by the X address ADRX [8: 6] is connected to the input / output line 30, the bit line BL becomes 0V.
On the other hand, a high voltage bias Vhv2 for erasing is applied to the selected word line WL by the Y address decoder 250, and the Y address decoder 20 is applied to the source line SL.
Since 0 to 0 V is applied, the selected memory cell is in the erased state. That is, the charge to the floating gate FG of the memory cell 60 is drawn.

At this time, the read enable signal REAEN
2 and the write enable signal WRITEN2 are not generated, so the multiplexer circuit 46 selects the input / output line 30. As described above, since the input / output line 30 is at the ground voltage of 0V, the selected bit line BL is at 0V. After such an erasure, an actual write mode is entered.

In the write mode, as shown in FIG. 7C, the signal WREN2 is at the H level, so that while the clock RWCK3 is at the H level as shown in FIG. Further, since the latch circuit 24 is initialized to the H level, the output of the AND gate 31 also goes to the H level. Therefore,
When the analog switch 29 is turned on, the P-channel M
The OS transistor 26 turns off. Also, the signal WRIE
The multiplexer circuit 46 is selected by N2,
When both the data D0 and D1 are “0”, the array ground ARYGND is selected, and when the data D0 and D1 are other than the above conditions, the input / output line 30 is selected.

First, data D0 and D1 are both "0".
The case where it is not explained. Now, the upper bit D of the input data
If 1 is "0", the output of the AND gate 32 becomes H level, so that the N-channel MOS transistor 27 is turned on, and the bias voltage VBLH is changed to the analog switch 29 and the input / output line 30 as shown in FIG. , The multiplexer circuit 46 and the X address decoder 100 to the selected bit line BL. Conversely, if the upper bit D1 of the input data is “1”, the AND gate 33
Becomes an H level, the N-channel MOS transistor 28 is turned on, and the bias voltage VBLL is applied to the analog switch 29, the input / output line 30, and the multiplexer circuit 4.
6 and the selected bit line BL via the X address decoder 100.

While the clock RWCK3 is at the H level,
Since the high voltage Vhv1 is supplied to the source line SL selected by the Y address decoder 200 ((c) in FIG. 7) and VB2 is supplied to the word line WL selected by the Y address decoder 250 ((g) in FIG. 7), FIG. Are satisfied, and writing to the memory cell 60 is executed. That is, injection of charges into the floating gate FG of the memory cell 60 is started.

Next, the clock RWCK3 falls,
When the clock RWCK4 becomes H level as shown in FIG.
When the output of the AND gate 42 is at L level, the AND gate 44
Becomes an H level, the analog switch 29 is turned off, the N-channel MOS transistor 36 is turned on,
The voltage dividing point P of the read bias generation circuit 35 is connected to the input / output line 30. The potential at the voltage dividing point P is N channel MO
When the S transistor 36 is off, the voltage VREFM is set slightly higher than V4. Further, in this state, VB1 is applied to the selected word line WL by the Y address decoder 250, and 0V is applied to the source line SL from the Y address decoder 200, so that the selected memory cell 60 is read. State. Therefore, a voltage Vm corresponding to the charge injected into the floating gate FG of the selected memory cell is obtained on the input / output line 30, and this voltage Vm is
Is compared with the output voltage Vdec.

In the decoder 22, one of the four voltages V1 to V4 from the resistance dividing circuit 21 is selected in accordance with the data latched in the data register 20, and the non-inverting terminal of the comparator 23 is selected. Is output to Here, the relationship between the data D1 and D0 and the partial pressure values V1 to V4 is shown in FIG. As a result of the comparison, if Vdec> Vm,
The output of the comparator 23 maintains the H level, and the write operation based on the clock RWCK3 and the clock RWCK
4 is repeated. By repeating the write operation, the amount of charge injected into the floating gate FG increases, and the read voltage Vm increases as shown in FIG. Then, when Vdec ≦ Vm, as shown in FIG. 7, the output of the comparator 23 is inverted to L level, and the output COMP of the latch circuit 24 also becomes L level. Therefore, the output of AND gate 31 is inverted from H level to L level, and P channel MOS transistor 2
6 is turned on, and the outputs of the AND gates 32 and 33 are L
Level, and the two N-channel MOS transistors 27 and 28 are turned off. Therefore, next, the clock RWCK
When 3 goes high, the bias voltage VBH is supplied to the bit line BL of the memory cell via the analog switch 29 (see FIG. 7). That is,
The write bias condition shown in FIG. 10 is broken, and the write operation stops. As described above, in the write mode, the quaternary analog amount corresponding to the 2-bit input digital data is stored in the selected memory cell 60.
In FIG. 1, writing can be performed in a short time by switching the bias voltage value supplied to the drain according to the data to be written.

When the data D0 and D1 are "0,0", the multiplexer circuit 46 is connected to the array ground ARY.
Select GND. In this case, there is no data to be written to the memory cell 60, that is, no charge is injected into the floating gate of the memory cell 60. Therefore, in the circuit of FIG. 1, in the case of "0, 0", the operation of injecting charges into the memory cell is not performed. Therefore, the source line is connected to the array ground ARYGND, and the selected memory cell 60 is not in the write state, but in the same state as the write stop state. The array ground ARYGND is provided from a bias source independent of the first bias generation circuit 500 and the second bias generation circuit 400. The level is Vhv1 of the write stop condition of the bias condition in FIG.
Is the same level as The array ground ARYGND is supplied to the multiplexer circuit 46 at the timing shown in FIG. 7 and is directly input to the X address decoder 100.
In the case of the data D0 and D1, the write condition of the memory cell 60 is not satisfied, and no write is performed. At the read timing, no charge is applied to the memory cell 60, and the read voltage remains at the voltage V1 or lower. Therefore, even though the memory cell array is in the write state, it is possible to inhibit the write state of only some of the memory cells in the signals REAEN and WREN and the values of the data D0 and D1. Become. The array ground ARY
Since the GND is used, the write stop state is stabilized, and the charge is prevented from being erroneously injected.

Next, regarding the operation in the read mode,
This will be described with reference to FIG. In this case, since the read enable signal REAEN is supplied to the multiplexer circuit 46, the multiplexer circuit 46
Select In the read mode, first, the signal XSET
When (C in FIG. 8) becomes H level, the initial value all “1” is set in the data register 20 (FIG. 8).
E) The decoder 22 outputs the analog voltage V4 corresponding to all "1" as shown in FIG. Then, when the clock RWCK4 becomes H level as shown in FIG. 8, the bias condition for the memory cell 60 becomes exactly the same as that at the time of the read operation in the write mode, and the bias condition for the memory cell 60 corresponds to the charge injected into the floating gate of the selected memory cell. Is obtained at the inverting terminal of the comparator 23, and this voltage Vm is compared with the voltage V4 from the decoder 22. As a result of the comparison, if Vm> V4, the comparator 23
Since the output COMP of the latch circuit 24 goes low, the output of the NAND gate 39 goes high. At this time, the output of the NAND gate 38 is fixed at the high level. , And all "1" s are kept in the data register 20 without performing the latch operation thereafter.

On the other hand, if the result of the comparison is Vm ≦ V4, the output COMP of the comparator 23 and the latch circuit 24 goes to the H level, and when the clock RWCK3 goes to the H level as shown in FIG. Goes low, the clock signal is output from the NAND gate 41 to the data register 20, and the data supplied to the data input line 45 is latched in the data register 20. The data input line 45 receives “1” from the down counter 801 shown in FIG.
Since data "D1, D0" of "0", "01", and "00" are sequentially output each time the clock RWCK4 falls, data "10" follows data "11" as shown in FIG. Is latched in the data register 20. Then, the output Vdec of the decoder 22 drops to the voltage V3 as shown in FIG. 8, and when the clock RWCK4 goes to the H level again, the voltage Vm corresponding to the analog amount read from the memory cell is compared with the voltage V3. You. If Vm> V3, the comparator 23 and the latch circuit 24
Is inverted to the L level, and "10" is held in the data register 20 without performing the latch operation thereafter. When Vm ≦ V3, the comparator 23
Since the output COMP of the latch circuit 24 maintains the H level, the next data "01" is latched in the data register 20, and the comparator 23 compares the voltages V2 and Vm.
From this comparison, if Vm> V2, data register 2
The content of 0 is fixed to “01”, and if Vm ≦ V2, the last data “00” is latched by the data latch 20;
The voltages Vm and V1 are compared. Since the voltage V1 is set to approximately 0 V, Vm> V1 in the last comparison, and the content of the data register 10 is fixed to "00".

As described above, the voltage Vm corresponding to the analog amount read from the memory cell is stored in the data register 2
0, resistance dividing circuit 21, decoder 22, comparator 23, N
The signal is AD-converted by the AND gate 39 and the NAND gate 41 and transferred to the outside via the output buffer 25. FIG. 11 shows a specific example of the multiplexer circuit 46.
0 is a NOR gate to which input data D0 and D1 are input, and 451 is a read enable signal REAEN2 and N
An OR gate 45 to which the output of the OR gate 450 is input;
Reference numeral 2 denotes NAND gates 452 and 45 to which the write enable signal WRITEN2 and the output of the OR gate 451 are input.
Reference numeral 3 denotes an AND gate 455 to which an output obtained by inverting the output of the NAND gate 452 by the inverter 454 and the array ground ARYGND, and a NAND gate 45
2 is a multiplexer section including a transmission gate 456 to which the output 2 and the input / output line 30 are input.

In FIG. 11, a write enable signal W
When RIEN2 is not applied and “0”, the output of the NAND gate 452 becomes “1”, the transmission gate 456 becomes conductive, and the input / output line 30 is selected. That is, the input / output line 30 is always selected at the time of reading and erasing. On the other hand, when the signal WIEN2 is applied and is “1”, the output of the NOR gate 450 changes the output of the NAND gate 452. Input data D0
When D1 and D1 are "1, 1", the output of the NOR gate 450 is "1". Further, since the signal REAEN is “0”, the OR gate 451 becomes “1” and the NAND gate 451 becomes “1”.
The output of the gate 452 becomes "0". Therefore, the transmission gate 456 becomes non-conductive, and
The D gate 455 is activated, and the array ground AR
YGND is selected. When the input data D0 and D1 are other than “0, 0”, the NOR gate 450 becomes “1” and the NAND gate 452 becomes “1”, so that the input / output line 30 is selected.

In the read / write circuit described above, 2-bit digital data is converted into a quaternary analog amount and written into one memory cell.
Actual digital data output from the PCM encoder 2 is 4 bits. Therefore, in this example, FIG.
As shown in FIG. 7, upper two bits of the input 4-bit digital data are stored in the right memory cell array 6R, and lower two bits are stored in the left memory cell array 6L. Of course, the memory for both arrays is
This is performed by the above-described read / write circuit 300, and the 2-bit digital data is converted into quaternary analog quantities, and then stored in each memory cell in multi-valued manner.

In FIG. 2, reference numeral 800 denotes a control circuit connected to a microcomputer (not shown), an ADPCM encoder, and an ADPCM decoder, and a down counter 80 for outputting a down-count value for AD conversion at the time of reading.
1 and an address generation circuit 10, and a 9-bit X
Address ADRX, 11-bit Y address ADRY,
In addition to transmitting 4-bit data, it outputs the various clock signals and control signals shown in FIG. 1, and further takes in digital data corresponding to the analog amount read from the memory cell array and sends it to the ADPCM decoder 7. do.

The right memory cell array 6R includes:
A block selector group 600 RU, a read / write circuit group 300 RU, an X address decoder group 100 RU, and a sub-decoder 700 RU are arranged on the upper side, and the block selector group 600 RL,
A read / write circuit group 300RL, an X address decoder group 100RL, and a sub-decoder 700RL are arranged. As for the left memory cell array 6L, similarly to the right cell array, the block selector groups 600L are vertically arranged.
U, read / write circuit group 300LU, X address decoder group 100LU, sub-decoder 700LU, block selector group 600LL, read / write circuit group 300
LL, X address decoder group 100LL, and sub-decoder 700LL are arranged.

Since the above-described circuit configurations for the right memory cell array 6R and the left memory cell array 6L are all the same and the input address signals are also the same, these memory cells perform exactly the same operation. Note that Y
The address decoders 200 and 250 and the second bias generation circuit 400 have the same configuration as that shown in FIG. Here, FIG. 3 shows the details of the left memory cell array 6L and its peripheral circuits.

In FIG. 3, the memory cell array 6L is divided and managed in 32 blocks each above and below, and a block selector BS, a read / write circuit R / W, and an X address decoder X-ADEC are arranged for each of these blocks. Have been. Therefore, the block selector group 600LU,
Each of 600LL includes 32 block selectors BS, each of the read / write circuit groups 300LU and 300LL includes 32 read / write circuits R / W, and each of the X address decoder groups 100LU and 100LL includes 32 X address decoders X-X. ADEC. The read / write circuit R / W of each block shown in FIG. 3 has exactly the same configuration as the read / write circuit 300 shown in FIG. 1, and the X address decoder X-ADEC is also exactly the same as the X address decoder 100 shown in FIG. It is a structure of. However, since the block selector BS detects that its own block has been selected, its own block NO. In this configuration, a different address is input for each block so that the H level is output only when the X address ADRX [5: 0] indicating the address is input.

The operation in the data write mode will be described below with reference to FIG. First, since the addresses transmitted from the address generation circuit 10 are sequentially updated, the lower 6 bits of the X address ADRX [5: 0] change as shown in FIG. 5A, and the block NO in the upper block selector group 600LU . 0 to NO. The select output BSEL sequentially becomes H level toward 31. This period is shown in FIG.
As shown in c and d, the upper read / write circuit group 300L
Since the latch enable signal LATEN and the write enable signal WREN2 to U become H level and L level, respectively, the block NO. 0 to NO. Toward the data register 20 in each read / write circuit R / W
Then, data is sequentially latched by the pulse RWCK2. Further, as the X address ADRX [5: 0] is updated, the lower block selector group 600
In LL, block NO. 32 to NO. 63, the select output goes high sequentially. During this period, the latch enable signal LATEN goes high as shown in FIG. 5E, so that in the lower read / write circuit group 300LL, the block NO. 32 to NO. Data is sequentially latched by the pulse RWCK2 in the data register 20 in each read / write circuit R / W toward 63.
During this period, the upper read / write circuit group 3
00LU to the write enable signal WRITE2
Since the level becomes the H level as shown in FIG. 5D, the write operation is executed simultaneously in each block.

The upper block NO. 0 to NO. When data is written to the block 31, the data written to a certain block 2
If the bit input data is "0, 0", writing to that block is not performed. In each block, X
The address decoder X-ADEC selects one of the bit lines BL based on the upper 8 bits of the X address ADRX [8: 6], and the Y address decoders 200, 250
Are any one of the source line SL and the word line W
Since L is selected, writing is simultaneously performed on the upper 32 selected memory cells as a result.

After writing, the address ADRX [5:
0] again returns to “0” and sequentially updates the address, so that the next 32 input sampling data are sequentially latched in the data register 20 of each block of the upper read / write circuit group 300LU. In the period during which such a latch operation is performed, in the lower read / write circuit group 300LL, the write enable signal WITEN2 is at the H level, so that data can be simultaneously written to 32 selected memory cells in all blocks. Be executed. The lower block NO. 32 to NO. When writing data to the block 63, if the 2-bit input data to be written to a certain block is “0, 0”, the writing to that block is not performed. Therefore, even in the write block group, the write can be inhibited by the value of the input data, and the write conditions for the memory cells can be reduced.

Next, the operation in the read mode will be described with reference to FIG. First, the sub-decoder 700LU
Is the X address ADRX as shown by the solid line in FIG.
A NAND gate 701 for inputting [4: 2], a NAND gate for inputting an address ADRX [5] and an output of the NAND gate 701, a signal REAEN which is always at the H level during the read mode, and an output of the NAND gate 702 are input. The read enable signal R shown in FIG.
And an AND gate 703 that outputs EAEN2. The sub-decoder 700LL is different from the sub-decoder 700LU only in that an inverted signal thereof is input instead of the address ADRX [5] as shown by a dotted line.
Unlike this, the other parts have exactly the same configuration.

Therefore, in the read mode, the address ADRX [5: 0] is updated as shown in FIG. 6A, and when the address becomes "60", all the bit outputs of ADRX [5: 2] become H level. Therefore, the sub-decoder 700L
In U, the output of the NAND gate 701 becomes L level, so that the outputs REAEN2 of the NAND gate 702 and the AND gate 703 become H level as shown in FIG. Therefore, the upper read / write circuit group 700
The read operation is started simultaneously from the 32 memory cells in the LU. This read operation is longer than one sampling period (a period in which the address is updated by 1), and in this case, it takes about three sampling periods, and ends before the address returns to “0”.

By the way, the period when the NAND gate 701 is at the H level continues until the address changes from "60" to "63", and when the address returns to "0", the output goes to the L level. However, the address is "0"
Since ADRX [5] is always at the L level from to, the output of NAND gate 702 is at the H level, and output REAEN2 of sub-decoder 700LU continuously maintains the H level as shown in FIG. . When the address ADRX [5: 0] changes from “0” to “31”, the block NO. 0 to NO. Since the 31 block selectors BS sequentially output the H level, the output buffer 34 is opened in each read / write circuit R / W, and the contents of the data register 20 are sequentially output.

On the other hand, in the sub-decoder 700LL, when the address ADRX [5: 0] becomes "28", the inverted output of the address ADRX [5] and each bit output of ADRX [4: 2] all become H level. , And the output of NAND gate 701 attains an H level, so that outputs REAEN2 of NAND gate 702 and AND gate 703 are output.
Rises to the H level as shown in FIG. Therefore, the read operation is simultaneously started from the 32 memory cells in the lower read / write circuit group 300LL. And NAN
The output of the D gate 701 keeps the H level until the address becomes “31”, and goes to the L level when the address becomes “32”.
Since the inverted output of RX [5] is always at the L level, during this period, the output RE of the lower read / write circuit group 300LL is output.
AEN2 continuously maintains the H level as shown in FIG. During the period when the address changes from "32" to "63", the block NO. 32 to NO. Since the 63 block selectors BS sequentially output the H level, the output buffer 34 is opened in each read / write circuit R / W, and the contents of the data register 20 are sequentially output.

As described above, by pre-reading the contents of the data register 20 four sampling periods before the timing at which data output is to be started, it is possible to prevent an unnecessary idle time in the read mode. As described above, the left memory cell array 6L has been described with reference to FIG. 3, but as described above, exactly the same operation is performed in the right memory cell array 6R.

[0043]

According to the present invention, the circuit configuration can be simplified and the circuit scale can be reduced while maintaining the reliability of data retention. In particular, in the write mode, the same conditions as those for the memory cells that do not perform writing are applied to the memory cells that do not perform charge injection, so that the writing accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a read / write circuit according to the present invention.

FIG. 2 is a block diagram showing a pair of left and right memory cell arrays and peripheral circuits according to the present invention.

FIG. 3 is a block diagram showing a left memory cell array and its peripheral circuits according to the present invention.

FIG. 4 is a circuit diagram showing a specific configuration of a sub-decoder according to the present invention.

FIG. 5 is a timing chart showing an operation in a latch mode and a write mode of the read / write circuit group according to the present invention.

FIG. 6 is a timing chart showing an operation in a read mode of the read / write circuit group according to the present invention.

FIG. 7 is a timing chart showing a write mode operation of the read / write circuit according to the present invention.

FIG. 8 is a timing chart showing a read mode operation of the read / write circuit according to the present invention.

FIG. 9 is a diagram showing a relationship between input digital data and a corresponding analog voltage in the present invention.

FIG. 10 is a diagram showing a bias condition of a memory cell in the present invention.

FIG. 11 is a specific circuit example of a multiplexer circuit 46;

[Explanation of symbols]

6R Right memory cell array 6L Left memory cell array 7 ADPCM decoder 8 First DA converter 9 Microcomputer 10 Address generation circuit 20 Data register 21 Resistance divider circuit 22 Decoder 23 Comparator 24 Latch circuit 25 Output buffer 26 P-channel MOS transistor 27, 28, 36, 37 N-channel MOS transistor 29 analog switch 45 multiplexer circuit 60 memory cell 100 X address decoder 100LU, 100LL, 100RU, 100RL X
Address decoder group 200 Y address decoder (for SL) 250 Y address decoder (for WL) 300 LU, 300 LL, 300 RU, 300 RL Read / write circuit group 400 Second bias generation circuit 500 First bias generation circuit 600 Block selector 600 LU, 600 LL, 600 RU , 600RL Block selector group 700LU, 700LL, 700RU, 700RL Sub-decoder 800 Control circuit 801 Down counter

Claims (4)

[Claims] A first memory cell array including a plurality of nonvolatile memory cells capable of storing multi-value information; and writing of multi-value information to one of the first and second memory cell arrays. A write circuit, a latch circuit for latching data to be written to the other memory cell while the write circuit is operating, and a control circuit for controlling a state of a memory cell where writing is not performed to a state independent of writing. A non-volatile multi-valued memory device comprising: 2. The control circuit according to claim 1, wherein the control circuit connects a bit line of a memory cell to which writing is not performed in the memory cell array to an array ground obtained from an independent voltage source. Non-volatile multi-level memory device. 3. The writing circuit according to claim 1, wherein the first and second write circuits are configured to be connected to each other.
3. The nonvolatile multi-level memory device according to claim 1, wherein multi-level information is alternately written to the memory cell array. 4. A nonvolatile multi-level memory device including first and second memory cells each including a plurality of nonvolatile memory cells capable of storing multi-level information, wherein one of the first and second memory cell arrays is a memory. Multi-valued information is written to a cell array, data to be written to the other memory cell is latched during a write operation, and the state of a memory cell to which writing is not performed is controlled to be independent from the state at the time of writing. A writing method for a nonvolatile multilevel memory device.