JPH11134185A - Micro computer device provided with rewritable non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize hardwares to be reguired and to simplify an operation in the case of rewriting flash EPROM of large capacity. SOLUTION: The operation program of an electronic cache register 1 and a rewriting IPL program are stored in flash EPROM 2 and they are managed with the block of a prescribed size as a unit. The content of EPROM 14 inserted into a socket 15 is transferred and it can be rewritten at every block. EPROM 14 has the same data block unit as the block of flash EPROM 2 and management data is stored in respective blocks. An IPL(initial program loader) program transfers program data to the pertinent block of flash EPROM 2 based on management data. Even if EPROM 14 has small capacity, the whose can be rewritten by plural pieces of data and only the block can be rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device having a rewritable semiconductor memory in which an operation program is stored.

[0002]

2. Description of the Related Art Conventionally, microcomputer devices such as an electronic cash register and a printer device include a flash EPR which is an electrically rewritable nonvolatile semiconductor memory.
An OM, a ferroelectric memory, and the like are used to store programs and data in advance. A ROM, which is a general read-only memory, needs to store programs and data in a manufacturing process, and cannot change stored contents after manufacturing. EPROMs, which are erasable and programmable read-only memories, must be irradiated with ultraviolet light to erase once written data or programs. Electrically erasable EEPR
In the OM, since the EPROM uses one transistor for each memory cell, the OM uses two transistors for each memory cell, so it is difficult to increase the capacity. A flash EPROM or a ferroelectric memory can form a memory cell with one transistor and can be electrically erased and written, so that it can be used as a part of a main memory of a microcomputer device or for data storage. It is widely used as a file.

In a microcomputer device having a rewritable non-volatile semiconductor memory as a part of a main memory, an IPL (Inline) which is a processing program for a rewritable operation is used.
Iterative Program Loader), an execution program and data to be rewritten are stored in a rewritable nonvolatile semiconductor memory. In order to rewrite a program or data stored in a rewritable nonvolatile semiconductor memory, it is necessary to transfer a program or data to be rewritten from the outside by some method. In a microcomputer device having a communication function, a program or data is read into a RAM or the like via a communication line, and a rewriting operation program is also read to perform rewriting.
If the storage medium is detachable as in a personal computer, the program or data to be rewritten can be mounted in a state where the program or data is stored in the storage medium and read into the RAM for rewriting. In an electronic cash register, a printer, or the like, a connection member such as an IC socket to which a nonvolatile semiconductor memory such as an EPROM having the same capacity as a rewritable nonvolatile semiconductor memory to be rewritten is detachably provided. By inserting a nonvolatile semiconductor memory in which a processing program for rewriting operation of a rewritable nonvolatile semiconductor memory and an execution program to be rewritten are stored in advance into a connection member, the rewriting stored in the nonvolatile semiconductor memory is performed. Flash EP according to the operation program
Erasing the stored contents of an electrically rewritable nonvolatile semiconductor memory such as a ROM, and a writing operation by transferring an execution program to be rewritten are performed.

[0004] Such rewriting is necessary when the execution program written in the rewritable nonvolatile semiconductor memory is upgraded due to a defect or a specification change. When the non-volatile semiconductor memory is inserted into a connection member such as an IC socket, it is connected to a data bus of a microcomputer device. When the nonvolatile semiconductor memory is connected, the control means such as the CPU
It is possible to erase the contents stored in rewritable nonvolatile semiconductor memory such as PROM, and directly transfer and write the execution program stored in nonvolatile semiconductor memory to rewritable nonvolatile semiconductor memory. Becomes

A prior art using a rewritable nonvolatile semiconductor memory such as a flash EPROM as a memory card as a medium for external storage is disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 07644. In this prior art, a memory card including a flash EPROM, which is an electrically rewritable nonvolatile semiconductor memory, as a storage element,
A recording management method for storing the management information together with the data is performed. When writing data to a memory card, an identification code such as a serial number is sequentially stored as a use code in an identification area of the management area. Since the identification area of the management area corresponding to the data area where data has not been written is the same as the initial state, it is possible to easily determine whether the data area is recorded or unrecorded by sequentially searching this identification area. Can be. As a result, it is not necessary to manage the last recording address of the data in the management area, and the data can be effectively managed without rewriting the contents of the management area.

[0006]

Problems to be Solved by the Invention
In the prior art of No. 4, there is no mention as to where the program of the operation of the controller for managing the recording of the flash EPROM is stored and whether or not the contents can be rewritten.

Conventionally, a non-volatile semiconductor memory capable of accessing the same memory capacity as a rewritable non-volatile semiconductor memory has been inserted into an IC socket as a connecting member, and the entire contents of the non-volatile semiconductor memory have been transferred. The stored contents of the possible nonvolatile semiconductor memory are rewritten.
However, rewritable nonvolatile semiconductor memories such as flash EPROMs have increased in capacity in recent years, and their packages have been miniaturized because the pitch between pins is small due to surface mounting. On the other hand, the package of the nonvolatile memory element used by being inserted into the IC socket is a standard dual-in-line package (DIP) or the like. The outer shape of the package is larger. Therefore, in order to achieve the same memory capacity as a rewritable nonvolatile semiconductor memory, a plurality of sockets are required, and a large mounting space is required in the microcomputer device. And raising costs. Connect the IC socket etc.
When only a plurality of nonvolatile semiconductor memories are used, it is necessary to perform a rewriting operation while replacing a plurality of nonvolatile semiconductor memories. Such work requires operator's operation and is inconvenient. In addition, when attaching or detaching the nonvolatile semiconductor memory, it is necessary to shut off the power supply of the microcomputer device. If the power is not turned off, an abnormal voltage will be applied when attaching / detaching, and the nonvolatile semiconductor memory may be damaged,
The microcomputer device may be damaged. Furthermore, it is not always necessary to rewrite the entire rewritable nonvolatile semiconductor memory, and it is often necessary to partially rewrite only a portion related to a version upgrade due to a specification change or a program defect. When the entire large-capacity rewritable nonvolatile semiconductor memory is erased and rewritten, the entire part including the part that does not need to be rewritten is stored in the non-volatile semiconductor memory in order to rewrite a small part. , An IC socket or the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcontroller having a rewritable nonvolatile semiconductor memory which can use a relatively small capacity nonvolatile semiconductor memory even if the capacity of the rewritable nonvolatile semiconductor memory becomes large. To provide a computer device.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a microcomputer device which stores an execution program for an original operation of the device and a processing program for writing the execution program in a rewritable nonvolatile semiconductor memory and executes the microcomputer. In addition, the address space of the rewritable nonvolatile semiconductor memory is managed by being divided into blocks each having a predetermined size, and a program to be updated is stored in one or more blocks.
A connection member capable of mounting a nonvolatile semiconductor memory stored together with information of a corresponding block, wherein the execution program is a rewritable nonvolatile memory according to the block information stored in the nonvolatile semiconductor memory mounted on the connection member; A microcomputer device comprising a rewritable nonvolatile semiconductor memory characterized by rewriting a program stored in a volatile semiconductor memory.

According to the present invention, a rewritable nonvolatile semiconductor memory provided in a microcomputer device comprises:
It has an address space that is divided and managed for each block of a predetermined size. The information of the corresponding block is also stored in the nonvolatile semiconductor memory for rewriting the contents of one or more blocks of the rewritable nonvolatile semiconductor memory. When the nonvolatile semiconductor memory is mounted on the connection member, the processing program for writing the execution program stored in the rewritable nonvolatile semiconductor memory is stored in the rewritable nonvolatile semiconductor memory according to the information of the block. Rewrite the program Since only the blocks that need to be rewritten need to be rewritten, even in a nonvolatile semiconductor memory having a small capacity compared to the capacity of the rewritable nonvolatile semiconductor memory, the stored contents can be transferred and rewritten. In the case where a single non-volatile semiconductor memory cannot be accommodated, a plurality of non-volatile semiconductor memories are sequentially connected to a connection member, and a corresponding block is rewritten according to each block information. The member can cope with large-capacity rewriting.

In the present invention, the block information includes a designation of a block to be rewritten and a designation of a last block of the designated blocks, and the processing program includes a last block designated by a rewriting block. And automatically terminates when they match.

According to the present invention, as information of a rewrite block stored in the nonvolatile semiconductor memory mounted on the connection member, designation of a block indicating a corresponding block in the rewritable nonvolatile semiconductor memory And the designation of the last block among the designated blocks, so that rewriting is performed by transferring each block, and when the last block is reached, the end of rewriting can be automatically determined.

Further, the present invention is characterized in that there is provided end display means for notifying the completion of writing to the rewritable nonvolatile semiconductor memory when the processing program is automatically ended.

According to the present invention, when it is automatically determined that the rewriting has been completed, the fact is notified by the end display means, so that the operator can easily know the end of the rewriting.

In the present invention, the last block is designated by the last block of the entire program to be updated and the last block of the program stored in the nonvolatile semiconductor memory in the mounted state. The processing program automatically notifies the replacement timing of the plurality of nonvolatile semiconductor memories and the termination time of the processing program when rewriting of the final block and the entire final block is completed. It is characterized by.

According to the present invention, when a block to be rewritten of a rewritable nonvolatile semiconductor memory is stored separately in a plurality of nonvolatile semiconductor memories and rewriting is performed,
In each nonvolatile semiconductor memory, the last block of the entire program to be updated and the last block of the program stored in the mounted nonvolatile semiconductor memory are stored as designation of the last block. Can be automatically notified of the replacement time after the end of rewriting using the nonvolatile semiconductor memory attached to the device and the end of the entire rewriting.

Further, according to the present invention, there is provided a power supply means capable of controlling the power supply, and the processing program is configured to stop the power supply from the power supply means after the rewriting is completed or when the nonvolatile semiconductor memory is replaced. It is characterized by controlling.

According to the present invention, when it is necessary to mount the non-volatile semiconductor memory on the connecting member, the power supply from the power supply is stopped. The microcomputer can be safely attached and detached without damaging the microcomputer. When the power is turned on, the initialization operation is easily performed.

Further, in the present invention, there is provided an insulating means which can be controlled so as to electrically insulate the mounting member, wherein the processing program controls the insulating means at the end or at the time of replacement, and Are controlled so as to be electrically insulated from each other.

According to the present invention, the processing program controls the insulating means to electrically insulate the connecting members at the end of rewriting or at the time of replacement. It is possible to eliminate the possibility that the program may run away due to electrical damage or abnormal input.

Further, in the present invention, the size of a block that divides the address space of the rewritable nonvolatile semiconductor memory is an integral multiple of the size of the block when erasing stored contents.

According to the present invention, the rewritable nonvolatile semiconductor memory is managed in units of an integral multiple of the block size when erasing the stored contents.
Only the necessary portions can be efficiently rewritten.

Further, in the present invention, the rewritable nonvolatile semiconductor memory is a flash EPROM.

According to the present invention, since a flash EPROM is used as a rewritable nonvolatile semiconductor memory, erasing and rewriting in block units can be easily performed while the flash EPROM is mounted on a microcomputer device.

[0025]

FIG. 1 shows a schematic electrical configuration of an electronic cash register 1 according to an embodiment of the present invention.
Programs for various operations as the electronic cash register 1
Flash E, a rewritable nonvolatile semiconductor memory
It is stored in PROM2. Flash EPROM2
Stores an IPL program which is a processing program for rewriting the flash EPROM 2 itself, as well as an execution program which is executed by the CPU 3 and performs various functions as the electronic cash register 1. CPU3
Executes the execution program stored in the flash EPROM 2 while using the RAM 4 as a work area or the like. The contents stored in the RAM 4 are lost when the power of the electronic cash register 1 is turned off, and a backup by a battery is necessary to save the contents. Flash E
The stored contents of the PROM 2 are stored as they are even when the power is turned off and turned off, so that backup by a battery is unnecessary.

The changeover switch 5 controls the changeover control circuit 6, and the CPU 3 operates as the electronic cash register 1 using the flash EPROM 2 and the flash EROM2.
The state of rewriting the PROM 2 itself is switched. KE
A keyboard Y7 is used as an input device. The keyboard Y7 is provided with keys for feeding paper on the journal side of the printer, feeding paper on the receipt side of the printer, and various function keys. The light emitting diode of the LED 8 is used as a status display. The buzzer 9 is sounded when there is an abnormality, and is used for displaying a state.
The DIP switch 10 is used as an input device for performing processing settings such as communication speed and communication data format at the time of communication.
The printer 11 is used as a print output device such as a receipt or journal at the time of registration. The RS232 interface 12 is used as data communication means with a personal computer or the like, and transmits and receives data. The communication of the rewriting data of the flash EPROM 2 is also performed by the RS23.
2 interface 12 can be used. In this case, the contents of the program to be rewritten are stored in the RAM 4, and the flash EPROM 2 is rewritten based on the contents. The liquid crystal display of the LCD 13 displays guidance on transactions and various settings, displays a registration process, displays an error, displays an end when rewriting the flash EPROM 2, displays an error, and the like, and is used as an output display device.

In order to rewrite the flash EPROM 2, the EPROM 1, which is a nonvolatile semiconductor memory, is mainly used.
4 is inserted into a socket 15 which is a connecting member. EP
The ROM 14 may have a smaller capacity than the flash EPROM 2. The EPROM 14 is an ultraviolet erasing type, and requires a relatively high program voltage for writing. Once the data has been written, the data is not easily rewritten, so the reliability is high. The socket 15 is connected to the data bus 1 together with the flash EPROM 2 and the RAM 4.
6 is connected to a data input / output terminal of the CPU 3.
The RS232 interface 12 is connected to an external personal computer or the like via an RS232 communication line 12a.

FIG. 2 shows a memory map related to the electronic cash register 1 of FIG. FIG. 2A shows the address space of the CPU 3, from address C0000h to DFFFF.
The address 2a of the flash EPROM 2 having a capacity of 16 megabits in a space of 2 megabytes up to the address Fh
Place. The IPL program and the operation program which are processing programs of the electronic cash register 1 are stored in the address 2a. According to the operation program, data transmission / reception via an RS232 interface 12 with another information processing apparatus such as an electronic cash register or a personal computer, editing of received data, calculation processing of registration, LC
Display output process to D13, print process to printer 11,
The input processing of the KEY 7 and the control of turning on / off the LED 8 are executed. Note that the last "h" in the address indicates that the address is in hexadecimal.

From address E0000h to EFFFFF
In a 1 megabyte address space up to address h, a socket 15 for an EPROM 14 having a capacity of 8 megabits.
Is arranged. The address F0000h and subsequent addresses are reserved portions of the electronic cash register 1 as a system.

As shown in FIGS. 2B and 2C, one address from address E0000h to address EFFFFFFh is stored.
The megabyte address 15a contains the first EPROM 14
a and the second EPROM 14b can be mounted. The first EPROM 14a has, for example, a flash E
An IPL program and an operation program of the apparatus stored in the PROM 2 are stored. Second EPROM 14b
Stores the subsequent part of the IPL program and the operation program.

FIG. 3 shows the internal block configurations of the flash EPROM 2 and EPROM 14 of FIG. 1, respectively. The flash EPROM 2 shown in FIG.
A megabit element is used, and the inside is divided into rewrite / erase blocks in units of 64 kilobytes. There are 32 such blocks, and 32 blocks from “C0” to “DF” are defined as block numbers.
In this embodiment, in order to simplify the IPL program,
Each block of the flash EPROM 2 is represented by the hexadecimal number of the upper 8 bits of the real address of the CPU 3.

FIG. 3A shows the first EPROM 14 shown in FIG.
2 shows the internal configuration of “a”. In this embodiment, an 8-megabit EPROM 14 is used. Unlike the flash EPROM 2, the EPROM 14 does not have a unit of a rewrite block, and is collectively erased by ultraviolet irradiation. First
Of the program stored in the flash EPROM 2 of the program stored in the flash EPROM 2 correspond to the blocks of “C0” to “CF” which are the first half blocks.
Update data for rewriting the L program and the operation program is stored. FIG. 3C shows the second EPRO.
4 shows the internal configuration of M14b. In the present embodiment, the second half “D” stored in the flash EPROM 2
The updated data subsequent to the IPL program and the operation program corresponding to the blocks from “0” to “DF” are stored.

The IPL program has the address 15 of the socket 15 from the address E00000h to the address EFFFFFFh.
a, the IPL program and the operation program data stored in the first EPROM 14a are sequentially read, and transferred to the corresponding blocks and addresses of the flash EPROM 2 for electrical rewriting. Further, the continuation of the IPL program and the operation program data stored in the second EPROM 14b are sequentially read out,
The data is transferred to the corresponding block and address of the flash EPROM 2 and electrically rewritten. It is assumed that the IPL program is relocatable so that it can operate even if it exists at the address 2a of the flash EPROM 2 or at the address 15a of the socket 15 or both. .

FIG. 4 shows the flash EPROMs 2 and E
3 shows a format configuration of management data 21 for each block 20 in units of 64 kilobytes of the PROM 14. The management data 21 occupies the last 16-byte area of each block 20. Block address (BLOCK ADDRES)
S) is an address in each block 20, "XX"
The portion expressed by means the upper 8 bits of the address space of the CPU 3. In this embodiment, since the block number (BLOCK NO.) Is represented by the upper 8 bits of the address space of the CPU 3, for example, when the block number is “C0”, XX = C0. The management data 21 of this C0 block includes C0FFF0h to C0FFFFh
It is provided at the address. The management data 21 is PROGRAM
VERSION part 22, BLOCK NO. DAT
A23, ROM BLOCK MAX DATA24,
PROGRAM END BLOCK MAX DAT
A25, SYSTEM reservation 26 and CHECK SU
It consists of M correction DATA27.

PROGRAM VERSION part 22
Is composed of 8 bytes from address XXFFFF0h to address XXFFFF7h. Differences in operation programs of various applications (depending on the type of business and destination) of the electronic cash register 1 and the program version by change / update It is provided for the purpose of managing differences and the like.
BLOCK NO. The DATA 23 is composed of 2 bytes from the address XXFFF8h to the address XXFFFF9h, and stores the number of each block. In the present embodiment, one of the block numbers from “C0” to “DF” is stored. ROM BLOCK MAX D
ATA24 is XXFFFBh from address XXFFFAh
It consists of 2 bytes up to the address, and the EPROM
The 14 largest block numbers are stored in all blocks. In the present embodiment, "CF" is stored in each block of the first EPROM 14a, and the largest block number stored in the EPROM 14 is stored.

PROGRAM END BLOCK M
AX DATA25 starts from address XXFFFCh to XXF
It is composed of 2 bytes up to the address of FFDh, and the maximum block number in one rewrite is all EPROMs.
It is stored commonly to all blocks 14a and 14b.
In the present embodiment, “DF” is stored. SYSTEM
Reservation 26 is reserved in the system for the future and XXF
It is composed of one byte at the address of FFEh. CHECK S
The UM correction DATA 27 is composed of one byte at the address XXFFFFh. Dummy data is stored in the CHECK SUM correction DATA 27 so that the total sum of the data of the block 20 becomes a specified value, that is, 01h in this embodiment. You. Flash EPROM2 and EPR
A specified value can be defined in order to confirm whether or not writing is normally performed in the OM 14.

FIG. 5 shows a structure for automatically stopping the power supply provided in the electronic cash register 1 of FIG. Power supply (POWE
R SUPLY) circuit 30 is a commercial AC input (AC
INPUT) is rectified and stabilized to supply a DC voltage of, for example, + 24V. The power supply circuit 30 can stop the supply of the DC output voltage in response to a power down (POWER DOWN) signal from the CPU 3. The supply control (POWER DOWN & RESET) circuit 31
Voltage D for operating a logic circuit such as CPU 3 from +24 V
C + 5V is supplied, and a reset signal (RESET) is generated when the power supply voltage rises to + 24V. When the rewriting of the rewritable flash EPROM 2 is completed, the IPL program issues a power stop signal from the CPU 3 to the power circuit 3.
0 to automatically turn off the power of the electronic cash register 1. The operator who is the rewriting operator is an EPROM
When the power supply switch is turned on again after the power supply switch is turned on again, the supply control circuit 31 raises DC + 5V and simultaneously derives a reset signal. The CPU 3 initializes the updated operation program in response to the reset signal. When a plurality of EPROMs 14 are sequentially replaced and rewritten, the power switch is turned on with the first EPROM 14 inserted in the socket 15 and the power supply voltage is automatically cut off at the next replacement time. E
By replacing the PROM 14, writing can be continued sequentially. The writing operator can continue the rewriting by attaching / detaching the EPROM 14 to / from the socket 15 with a simple operation without being bothered by shutting down the power supply or performing operations corresponding to the initialization of the operation program.

FIG. 6 shows another embodiment of the present invention.
2 shows a configuration related to the switching control circuit 6 of FIG. The IPL program outputs a power stop signal at the stage when the writing by one EPROM 14 is completed, and supplies the power stop signal to the bus switch (BUS SWITCH) circuit 36 and the power switch (SWITCH) circuit 37 of the switching control circuit 6, respectively. The bus switch circuit 36 includes switches and gates for electrically insulating or conducting addresses (ADDRESS), data (DATA), and various control signals from the CPU 3. The IPL program consists of multiple E
When rewriting using the PROM 14, the first EP
When the writing by the ROM 14 is completed, a power supply stop signal is generated from the output port of the CPU 3 and the gates (GAT) of the bus switch circuit 36 and the power switch circuit 37 are generated.
E) The terminal is made inactive, and the socket 15 side of the bus switch circuit 36 is made electrically insulated.

The power switch circuit 37 can cut off or conduct the power supply voltage Vcc applied to the EPROM 14 inserted into the socket 15. The IPL program outputs a power stop signal at the stage when writing is completed, and makes the socket 15 side of the power switch circuit 37 electrically insulated. The socket 15 is an IC socket into which a 32-pin DIP can be inserted, for example, and can be changed according to the specifications of the nonvolatile semiconductor memory to be used. Further, since the pin arrangement of the EPROM 14 of the ultraviolet erasing type is standardized, the socket 15 for 32 pins is
An EPROM mounted on a 28-pin DIP can also be inserted. In the present embodiment, a plurality of EPs
The large-capacity flash EPROM 2 can be rewritten by using the ROM 14,
Since it is only necessary to be able to rewrite some blocks of the ROM 2, the socket 15 can be changed to a socket that requires less space, such as 28 pins.

FIG. 7 shows a case where the flash EPROM 2 is rewritten only in a specific block.
3 shows an internal block configuration of M2 and EPROM 14.
The flash EPROM 2 shown in FIG. 7A uses a 16-megabit element, and its internal address 2a is 6 bits.
It has a rewrite / erase block in units of 4 kilobytes, and is divided into 32 blocks 20 as described above. FIG.
(A) shows the block numbers “C0”, “C”
Assuming that it is necessary to rewrite "4", "C5", and "D1", the blocks are shown with diagonal lines. A first EPROM that stores the contents of a block to be rewritten
The contents of the EPROM 14a include blocks “C0”,
Four blocks 20 of “C4”, “C5”, and “D1” are stored in order. The first EPROM 14a has a storage capacity of 8 megabits and can store 16 blocks of 64 kilobytes, so the remaining 14 blocks are unused (NOT USED).
In the four blocks 20 of the first EPROM 14a, as management data 21 as shown in FIG.
K NO. DATA23 is “C0”,
"C4", "C5", "D1", ROM BLO
CK MAX DATA24 and PROGRAM E
The portions of the ND BLOCK MAX DATA 25 are each "D1".

FIGS. 8 and 9 show a flash EPROM 2 according to an IPL program according to an embodiment of the present invention.
The following shows the operation procedure when rewriting the data. The operation is started from step s0. In step s1, it is determined whether or not the changeover switch 5 is ON. If it is ON, the EPROM 14 is inserted into the socket 15 in step s2,
Rewrite. In step s3, power supply (POWER)
Turn on the switch. In step s4,
The LED 8 indicating power-on is turned on. In step s5, the power supply circuit 30 and the supply control circuit 31 rise, and the CPU 3 initializes the circuit and the program (PROGRAM) by the reset signal.

At step s 6, the IPL program is executed, and the fact is displayed on LCD 13. Steps
7, the PROGRAM END BLOCK MAX DAT from the EPROM 14 inserted into the socket 15
A24 is read from the addresses XXFFFCh and XXFFFDh as shown in FIG. 4 and stored at a predetermined address in the RAM 4. In step s8, the ROM BLOCK MAX DATA 24 stored at the addresses XXFFFAh and XXFFFBh and being the largest block number stored in the EPROM 14 is stored.
Is read and stored at a predetermined address in the RAM 4.

At step s9, the address XXFFF8
h and XXFFF9h, and the block number BLOCK NO. DATA is read and stored at a predetermined address in the RAM 4. Step s1
At 0, the block 20 specified by the block number is erased. The flash EPROM 2 has a function of erasing the designated block 20 according to a command given from the CPU 3. In step s11, the CPU 3 checks the status of the erasure completion with respect to the flash EPROM 2 to check whether the erasure is completed. If it is confirmed that the erasure has been completed, the program data stored in the EPROM 14 is read, transferred, and written for the block 20 in the flash EPROM 2 in step s12.
In step s13, the status in the flash EPROM 2 is read, and it is checked whether the writing is completed. When the writing is completed, in step s14,
The contents of the block 20 written from the flash EPROM 2 are read, compared with the original data stored in the EPROM 14, and a VERY CHECK is performed to confirm whether or not the contents are the same. Step s15
Then, the data match is confirmed, and in step s15, the CHE
Calculate CK SUM. CHECK SUM is 1
All data included in one block 20 are added ignoring overflow, and it is determined whether or not the data matches a specified value. If written correctly, CHECK SUM
Due to the correction DATA 27, the added value should always match the specified value.

When it is determined in step s17 that the added values (SUM) match, in step s18, the fact that the rewriting of the block 20 has been normally completed is displayed on the LCD 13. In step s19, the block number read in step s9 and stored in the RAM 4 is compared with the last block number read in step s7 and stored in the RAM 4, and if they do not match, step s20
To read the program number in step s8
Is compared with the maximum block number of the EPROM 14 stored in the EPROM 14. If they do not match, the EPRO
Since there is a block in M14 further storing program data to be rewritten, step s21
Then, the next block 20 is read from the EPROM 14 with the block address increased by 64 kilobytes (KB). In step s22, the management data 21 of the last 16 bytes is read and stored at a predetermined address in the RAM 4, and the process returns to step s9.

At step s20, the block number is
If it is determined that the number matches the maximum block number of the PROM 14, one EPROM 14a is determined in step s23.
Is output to the LCD 13 to indicate that the rewriting has been completed, and a display requesting replacement of the next EPROM 14b is made. Next, in step s24, a power supply stop signal is output from the CPU 3, and the supply of the power supply voltage + 24V from the power supply circuit 30 in FIG. 3 is stopped. As a result, the supply of the operation power supply +5 V from the power supply control circuit 31 is also stopped, and the LED 8 is also turned off. In step s25, the rewriting operator sets the LE
When D8 is turned off, the EPROM 14 is removed from the socket 15, and the process returns to step s2 to insert the next EPROM 14.

If it is determined in step s19 that the block number matches the maximum block number of the program to be rewritten, in step s27, the flash EP
LCD indicates that rewriting to ROM2 has been completed normally.
A power supply cutoff signal is supplied from the CPU 3 to the power supply circuit 30, the supply of the power supply voltage is stopped again, and the LED 8 is also turned off. When the LED 8 is turned off, the rewriting operator
The changeover switch 5 is turned off to set one EPROM 1
The rewriting by 4 is completed.

In step s1, the changeover switch 5 is turned on.
If not, the EPROM 14 is removed from the socket 15 in step s30, and the process proceeds to step s31.
Then, the power is turned on while a specific key of the key 7 is depressed. In step s32, the circuit and the program are initialized. In step s33, a master reset process for the operation program is performed.
Ends the rewriting procedure.

In another embodiment of the present invention shown in FIG.
Instead of stopping the power supply in step s24, only the socket 15 is electrically insulated by the bus switch circuit 36 and the power switch circuit 37 in the switching control circuit 6, and the EPROM 14 is removed from the socket 15. If replacement is required, a new EPROM 14 is
Insert into 5. In this embodiment, in step s28,
Turn off the power.

[0049]

As described above, according to the present invention, the address space of a rewritable nonvolatile semiconductor memory is managed in block units, and the contents of a block to be rewritten are stored in a connection member in a state of being stored in the nonvolatile memory. Insertion and rewriting are performed, so that a plurality of non-volatile memories are sequentially mounted on a single mounting member to rewrite the entire block of a large-capacity writable non-volatile semiconductor memory, or one or a plurality of blocks. Can be rewritten with a single non-volatile semiconductor memory, and can be rewritten with a single mounting member, so that rewriting can be performed with minimum hardware. Since the capacity of the nonvolatile semiconductor memory is not necessarily required to be equal to the capacity of the entire rewritable nonvolatile semiconductor memory, the size of the detachable member does not need to be too large, and the mounting space on the board of the microcomputer device is reduced. Thus, costs can be reduced.

Further, according to the present invention, the processing program can automatically recognize the end of rewriting of one or more blocks of the rewritable nonvolatile semiconductor memory by the nonvolatile semiconductor memory inserted into the connection member. ,
It is not necessary for the operator performing the rewriting operation to perform a special input operation, and the rewriting operation can be simplified.

Further, according to the present invention, the display is made at the end of the rewriting, so that the rewriting operator can be notified easily and can confirm the end.

Further, according to the present invention, the processing program determines the replacement time and the end time when rewriting a large capacity rewritable nonvolatile semiconductor memory by sequentially inserting a plurality of nonvolatile semiconductor memories into the connection member. Since the determination is made automatically, the rewriting operator does not need to perform a special key operation or the like, and can perform the rewriting with a simple operation.

Further, according to the present invention, since the power supply is cut off at the time of replacement of the nonvolatile semiconductor memory or at the time of the end of the rewriting, if the rewriting operator turns on the power again, the program is turned on by the power-on reset function. Can also be initialized.

Further, according to the present invention, the connection member is electrically cut off at the time of replacement of the nonvolatile semiconductor memory or at the end of rewriting. Therefore, when replacing a plurality of nonvolatile semiconductor memories, the operator turns off the power supply. It is not necessary to perform an operation of shutting off, and a large-capacity rewritable nonvolatile semiconductor memory can be easily rewritten by continuously inserting the nonvolatile semiconductor memory.

Further, according to the present invention, only the blocks that need to be rewritten can be rewritten, the time required for rewriting can be reduced, and the number of nonvolatile semiconductor memories can be reduced to minimize the time and effort for replacement.

According to the present invention, the flash EPRO
M is used as a rewritable non-volatile semiconductor memory, and a block that divides the address space is an integral multiple of the size to be collectively erased, so that the block can be efficiently erased and rewritten.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of an embodiment of the present invention.

FIG. 2 is a view showing an address map of the electronic cash register 1 of FIG. 1;

FIG. 3 is a diagram showing a block configuration in a flash EPROM 2 and EPROMs 14a and 14b in the embodiment of FIG. 1;

FIG. 4 is a diagram showing contents of management data 21 in each block 20 of FIG.

FIG. 5 is a block diagram showing a configuration for automatically stopping power supply in the embodiment of FIG. 1;

FIG. 6 is a block diagram showing a configuration in which the switching control circuit 6 electrically insulates the socket 15 as another embodiment of the present invention.

FIG. 7 is a diagram showing a block configuration when partially rewriting the flash EPROM 2 in the embodiment of FIG. 1;

FIG. 8 is a flowchart showing an operation procedure for rewriting in the embodiment of FIG. 1;

FIG. 9 is a flowchart showing an operation procedure for performing rewriting in the embodiment of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Electronic cash register 2 Flash EPROM 2a, 15a Address 3 CPU 4 RAM 5 Changeover switch 6 Changeover control circuit 7 KEY 8 LED 9 Buzzer 10 DIP switch 12 RS232 interface 13 LCD 14 EPROM 14a First EPROM 14b Second EPROM 15 Socket 20 Block 21 management data 23 BLOCK NO. DATA 24 ROM BLOCK MAX DATA 25 PROGRAM END BLOCK MAX
DATA 30 Power supply circuit 31 Supply control circuit 36 Bus switch circuit 37 Power supply switch circuit

Claims (8)

[Claims] 1. A microcomputer device for storing and executing in a rewritable nonvolatile semiconductor memory an execution program for an original operation of the device and a processing program for writing the execution program, comprising a rewritable nonvolatile semiconductor memory. The address space of semiconductor memory is
A connection member capable of mounting a nonvolatile semiconductor memory in which one or more blocks of a program to be updated and managed together with information of a corresponding block are managed by being divided into blocks of a predetermined size and updated. A rewritable nonvolatile semiconductor memory characterized by rewriting a program stored in a rewritable nonvolatile semiconductor memory according to information of a block stored in the nonvolatile semiconductor memory attached to the connection member. A microcomputer device provided. 2. The information of the block includes a designation of a block to be rewritten and a designation of a last block among the designated blocks. The processing program compares the block to be rewritten with the designated last block. 2. The microcomputer device comprising a rewritable nonvolatile semiconductor memory according to claim 1, wherein the operation is automatically terminated when a match occurs. 3. The rewritable nonvolatile semiconductor memory according to claim 2, further comprising end display means for notifying completion of writing to said rewritable nonvolatile semiconductor memory when said processing program automatically ends. A microcomputer device comprising: 4. The specification of the last block includes the last block of the entire program to be updated and the last block of the program stored in the nonvolatile semiconductor memory in the mounted state. The processing program automatically notifies the replacement timing of the plurality of nonvolatile semiconductor memories and the termination timing of the processing program when the rewriting of the final block and the entire final block is completed. A microcomputer device comprising the rewritable nonvolatile semiconductor memory according to claim 2 or 3. 5. A power supply unit capable of controlling power supply, wherein the processing program controls so as to stop power supply from the power supply unit after rewriting is completed or at the time of replacement of the nonvolatile semiconductor memory. A microcomputer device comprising the rewritable nonvolatile semiconductor memory according to claim 3 or 4. 6. An insulating means which can be controlled so as to electrically insulate the mounting member, wherein the processing program is executed at the end or at the time of replacement.
6. A microcomputer device comprising a rewritable nonvolatile semiconductor memory according to claim 3, wherein said microcomputer controls said insulating means to electrically insulate said connecting member. 7. The size of a block that divides the address space of the rewritable nonvolatile semiconductor memory is an integral multiple of the size of a block when erasing stored contents. 7. A microcomputer device comprising the rewritable nonvolatile semiconductor memory according to any one of 6. 8. The microcomputer device according to claim 1, wherein said rewritable nonvolatile semiconductor memory is a flash EPROM.