JP2011108161A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce man-hours involved in switching a flash memory in an information processor with the flash memory mounted thereon. <P>SOLUTION: The information processor 1 includes a flash memory 2, a storing part 3 and a control part 4. The storing part 3 stores information 5 and 6 about a flash memory regarding each of a plurality of flash memories including the mounted flash memory 2. The control part 4 controls an access to the mounted flash memory 2 on the basis of the information 5 about the mounted flash memory 2 in the information 5 and 6 about the flash memories stored in the storing part 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus.

  Conventionally, as an information processing device equipped with a flash memory, a program required for rewriting the flash memory on the recording medium side (a pointer to rewrite data, each sector configuration information of the flash memory, data rewrite range instruction data), rewrite data In addition, there is known an apparatus that provides a sector data backup area including data that does not need to be rewritten during a rewrite operation. This information processing apparatus backs up rewrite-free data on a recording medium when erasing a sector in a rewriting process, and performs a restoration process using data from the recording medium after interruption even when the power is turned off ( For example, see Patent Document 1.)

JP 2003-308253 A

  However, the conventional information processing apparatus has the following problems. For example, the flash memory may be replaced with another flash memory having a different manufacturer or specification due to a cause such as the end of manufacture of the flash memory. In that case, the architecture of the internal sector configuration and the access command to the flash memory may differ between the original flash memory and the alternative flash memory. If the architecture is different, it is necessary to update the software that controls the flash memory to one that supports the alternative flash memory, which requires enormous man-hours to develop, test, and update the software that controls the alternative flash memory. There is a problem.

  An object of the present invention is to provide an information processing apparatus capable of reducing the man-hour associated with replacement of a flash memory.

  This information processing apparatus includes a flash memory, a storage unit, and a control unit. The storage unit stores information on the flash memory for each of the plurality of flash memories including the mounted flash memory. The control unit controls access to the mounted flash memory based on information about the mounted flash memory among the information about the flash memory stored in the storage unit.

  According to this information processing apparatus, it is possible to reduce the man-hour associated with the replacement of the flash memory.

1 is a block diagram illustrating an information processing apparatus according to a first embodiment. FIG. 10 is a block diagram illustrating a main part of an information processing apparatus according to a second embodiment. FIG. 10 is a block diagram illustrating details of the information processing apparatus according to the second embodiment. It is a figure which shows an example of the sector structure of flash memory. It is a figure which shows an example of the command which controls flash memory. It is a figure which shows an example of the storage information of the flash memory information storage part concerning Example 2. FIG. FIG. 10 is a sequence diagram illustrating a processing procedure of the information processing apparatus according to the second embodiment. FIG. 10 is a sequence diagram illustrating a processing procedure of the information processing apparatus according to the second embodiment. 10 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment. 10 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment. 10 is a flowchart illustrating an operation of the information processing apparatus according to the second embodiment.

  Exemplary embodiments of the information processing apparatus will be described below in detail with reference to the accompanying drawings. The information processing apparatus includes information on the flash memory for a plurality of flash memories including the mounted flash memory. The information processing apparatus controls access to the flash memory based on the information about the installed flash memory among the information about the plurality of flash memories.

Example 1
FIG. 1 is a block diagram of the information processing apparatus according to the first embodiment. As illustrated in FIG. 1, the information processing apparatus 1 includes a flash memory 2, a storage unit 3, and a control unit 4. The storage unit 3 stores information 5 and 6 related to the flash memory for each of a plurality of flash memories including the mounted flash memory 2. The control unit 4 controls access to the mounted flash memory 2 based on the information 5 about the mounted flash memory 2 out of the information 5 and 6 about the flash memory stored in the storage unit 3. I do. In the example shown in FIG. 1, two pieces of information about the flash memory are shown in the storage unit 3, but information about three or more flash memories may be stored in the storage unit 3.

  According to the first embodiment, since information 5 and 6 relating to a plurality of flash memories are stored in the storage unit 3, the mounted flash memory 2 is replaced with a flash memory in which information is stored in the storage unit 3. be able to. In that case, the control unit 4 can acquire information corresponding to the newly mounted flash memory from the storage unit 3. Therefore, it is not necessary to develop, test, or update software for controlling the newly installed flash memory, so that the man-hour associated with the replacement of the flash memory can be reduced.

(Example 2)
As an example of the information processing apparatus according to the first embodiment, for example, an apparatus including a programmable device can be cited. In the second embodiment, an information processing apparatus including a programmable device will be described.

FIG. 2 is a block diagram of a main part of the information processing apparatus according to the second embodiment. As illustrated in FIG. 2, the information processing apparatus 11 includes a flash memory 12, a storage unit 13, and a control unit 14. The storage unit 13 includes a rewritable nonvolatile memory. An example of a rewritable nonvolatile memory is, for example, an EEPROM (Electrically Erasable and Programmable Read Only Memory, electrically erasable and programmable read-only memory). The rewritable nonvolatile memory of the storage unit 13 stores information 15 and 16 relating to the flash memory for each of the plurality of flash memories including the mounted flash memory 12. The information processing apparatus 11 includes an acquisition unit 17, a storage unit 18, a programmable device 19, and an MPU (Micro Processing Unit, microprocessor) 20.

  The flash memory 12 stores configuration data 21 as information defining the logical specifications of the programmable device 19. The flash memory 12 stores an initial program loader 22 that is executed when the information processing apparatus 11 is activated. The acquisition unit 17 acquires information 15 regarding the mounted flash memory 12 from the storage unit 13. The acquisition unit 17 expands the information 23 about the sector of the flash memory and the information 24 about the command for controlling the flash memory, which are included in the information acquired from the storage unit 13, and stores them in the storage unit 18. The storage unit 18 stores information 23 relating to sectors of the flash memory and information 24 relating to commands for controlling the flash memory as information for controlling access to the flash memory 12.

  The control unit 14 controls access to the flash memory 12 based on the information 23 related to the sectors of the flash memory and the information 24 related to commands for controlling the flash memory, which are stored in the storage unit 18. The control unit 14 reads the configuration data 21 from the flash memory 12 and sets the programmable device 19 based on the configuration data 21 (configuration). The control unit 14 accesses the flash memory 12 based on the loading instruction from the MPU 20. The control unit 14 reads the initial program loader 22 from the flash memory 12 and loads the initial program loader 22 into the MPU 20.

  The MPU 20 instructs the control unit 14 to load the initial program loader 22. The MPU 20 executes software 25. A terminal (not shown) is connected to the MPU 20. In response to an instruction from the terminal, information 15 and 16 related to the flash memory can be read or erased from the storage unit 13 or information related to the flash memory can be written.

  FIG. 3 is a block diagram illustrating details of the information processing apparatus according to the second embodiment. As shown in FIG. 3, for example, an FPGA (Field Programmable Gate Array) 31 is used as an example of the programmable device 19 in FIG. 2. As the control unit 14 in FIG. 2, a flash access control unit 32 and a configuration control unit 33 are provided. As the acquisition unit 17 in FIG. 2, an initial load control unit 34 is provided. As the storage unit 18 in FIG. 2, a sector configuration table 35 and a command table 36 are provided. Further, an address decoding unit 37, a storage unit interface unit 38, and a flash interface unit 39 are provided. A flash memory information storage unit 40 is provided as the storage unit 13 of FIG. The flash access control unit 32, the configuration control unit 33, the initial load control unit 34, the sector configuration table 35, the command table 36, the address decoding unit 37, the storage unit interface unit 38, and the flash interface unit 39 are, for example, flashed on a single board. The memory control hardware 41 is provided. The flash memory control hardware 41 includes, for example, a programmable logic device (PLD: Programmable Logic Device). For example, a terminal 43 is connected to the MPU 20 via an e-support 42.

  The rewritable nonvolatile memory of the flash memory information storage unit 40 stores information regarding a plurality of flash memories. The initial load control unit 34 acquires information related to the mounted flash memory 12 from the flash memory information storage unit 40. The initial load control unit 34 stores the information acquired from the flash memory information storage unit 40 in the sector configuration table 35 and the command table 36. The sector configuration table 35 stores information regarding the sectors of the mounted flash memory 12. The command table 36 stores information related to commands for controlling the mounted flash memory 12.

  The flash access control unit 32 controls access to the flash memory 12 based on the information stored in the sector configuration table 35 and the information stored in the command table 36. The flash access control unit 32 reads the configuration data of the FPGA 31 from the flash memory 12. The flash access control unit 32 accesses the flash memory 12 based on a loading instruction from the MPU 20. The flash access control unit 32 reads the initial program loader from the flash memory 12 via the flash interface unit 39 and loads the initial program loader 22 into the MPU 20. The configuration control unit 33 sets the FPGA 31 based on the configuration data.

  The address decoding unit 37 decodes the address data. The storage unit interface unit 38 is an interface that connects the flash memory control hardware 41 and the flash memory information storage unit 40. The flash interface unit 39 is an interface that connects the flash memory control hardware 41 and the flash memory 12. The flash memory 12 and the MPU 20 are as described with reference to FIG.

FIG. 4 is a diagram illustrating an example of the sector configuration of the flash memory. As shown in the chart 51 in FIG. 4, the sector configuration of the flash memory may differ depending on the manufacturer, model number, and the like. In the example shown in FIG. 4, the flash memory manufactured by company A, the flash memory manufactured by company B, and the flash memory manufactured by company C all have a capacity of, for example, 8.192 Mbytes, but the capacity of each internal sector is different. ing. For example, in the flash memory manufactured by company A, the capacity of each sector with sector numbers 0 to 7 and sector numbers 134 to 141 is 8 Kbytes, and the capacity of each sector with sector numbers 8 to 133 is It is 64K bytes. In the flash memory manufactured by company B, the capacity of each sector with sector numbers 0 to 7 is 8 Kbytes, and the capacity of each sector with sector numbers 8 to 134 is 64 Kbytes. In the flash memory manufactured by company C, the capacity of each sector with sector numbers 0 to 127 is 64 Kbytes.

FIG. 5 is a diagram illustrating an example of a command for controlling the flash memory. As shown in the chart 52 of FIG. 5, the command for controlling the flash memory may differ depending on the manufacturer, model number, and the like. For example, when erasing a sector from a flash memory manufactured by company A, as sector erase commands, data AA at address AAA, data 55 at address 555, data 80 at address AAA, data AA at address AAA, address 555 Then, commands are issued in the order of data 55 and data 30 at address SA. SA represents the head address of the sector. On the other hand, for example, when erasing a sector from the flash memory manufactured by company B, as sector erase commands, data AA at address 555, data 55 at address BBB, data 80 at address 555, data 80 at address 555 Commands are issued in the order of data AA, data 55 at address BBB, and data 30 at address SA. Descriptions of the sector erase command for the flash memory manufactured by company C, the data write command for the flash memory manufactured by each company, and the command (read mode return command) for shifting from the other mode to the read mode are omitted (FIG. 5). See).

Example of Information Stored in Flash Memory Information Storage Unit FIG. 6 is a diagram illustrating an example of information stored in the flash memory information storage unit. As shown in FIG. 6, the storage information 53 includes a manufacturer ID and a device ID as basic information. The manufacturer of the flash memory and the model number of the device can be identified by the manufacturer ID and the device ID. In the illustrated example, the storage information 53 includes information on the number of consecutive sectors having the same capacity as the sector capacity following the basic information. The illustrated example is information on the flash memory manufactured by Company A. As sector configuration information, 8 sectors with a capacity of 8 Kbytes continue, 126 sectors with a capacity of 64 Kbytes continue, and a sector with a capacity of 8 Kbytes again. Represents 8 consecutive.

  Following the sector configuration information, for example, commands shown in FIG. 5 are stored in the order of an erase command, a write command, and a read mode return command. The storage order of the erase command, the write command, and the read mode return command may be another order. Immediately before the erase command, an information boundary identifier indicating the start of the erase command is inserted. For example, 0xEEEE1 is inserted as an information boundary identifier indicating the start of the erase command. Immediately before the write command, an information boundary identifier indicating the start of the write command is inserted. For example, 0xEEEE2 is inserted as an information boundary identifier indicating the start of a write command. Immediately before the read mode return command, an information boundary identifier indicating the start of the read mode return command is inserted. For example, 0xEEEE3 is inserted as an information boundary identifier indicating the start of the read mode return command.

  An information boundary identifier indicating the end of information related to one flash memory is inserted at the end of information related to one flash memory. For example, END is inserted as an information boundary identifier indicating the end of information related to one flash memory. Each information boundary identifier is not limited to the example described above. In the illustrated example, the manufacturer and device ID, the address and data of each command, and each information boundary identifier are stored in a 16-bit width area, for example, but other bit widths may be used. Furthermore, the configuration of the storage information 53 is not limited to the configuration shown in FIG.

-Operation | movement of information processing apparatus Operation | movement of the information processing apparatus 11 is demonstrated referring FIG. First, the operation immediately after the power is turned on will be described. When the information processing apparatus 11 is powered on, the initial load control unit 34 asserts the address signal a1, the select signal s1, and the read signal r1 to the storage unit interface unit 38. The storage unit interface unit 38 recognizes that the initial load control unit 34 reads data from the flash memory information storage unit 40 in response to the assertion of the address signal a1, the select signal s1, and the read signal r1. Then, the storage unit interface unit 38 asserts the address signal a2, the select signal s2, and the read signal r2 to the flash memory information storage unit 40.

  The storage unit interface unit 38 acquires information on the sector configuration of the mounted flash memory 12 from the flash memory information storage unit 40 via the data signal line d2. When the initial load control unit 34 asserts the address signal a3 and the write signal w3 to the sector configuration table 35, information on the sector configuration of the mounted flash memory 12 is obtained via the data bus d1. Stored in

  Similarly, the storage unit interface unit 38 acquires information on commands for controlling the mounted flash memory 12 from the flash memory information storage unit 40. When the initial load control unit 34 asserts the address signal a4 and the write signal w4 to the command table 36, information regarding the command for controlling the mounted flash memory 12 is stored in the command table 36 via the data bus d1. Stored.

  Next, the flash access control unit 32 asserts the address signal a3 and the read signal r3 to the sector configuration table 35. Thereby, the flash access control unit 32 acquires information on the sector configuration of the flash memory 12 from the sector configuration table 35 via the data bus d1. Further, the flash access control unit 32 asserts the address signal a4 and the read signal r4 to the command table 36. As a result, the flash access control unit 32 acquires information regarding a command for controlling the flash memory 12 from the command table 36 via the data bus d1.

  Next, the flash access control unit 32 asserts the address signal a <b> 5 to the flash memory 12. Further, the flash access control unit 32 asserts a read signal r6 to the flash interface unit 39. In response to the assertion of the read signal r6, the flash interface unit 39 asserts the select signal s5 and the read signal r5 to the flash memory 12. Thereby, the flash access control unit 32 acquires configuration data of the FPGA 31 from the flash memory 12 via the data bus d5.

  The flash access control unit 32 passes the configuration data of the FPGA 31 to the data bus d7. Further, the flash access control unit 32 asserts the configuration control signal c <b> 1 to the configuration control unit 33. In response to the assertion of the configuration control signal c1, the configuration control unit 33 asserts the configuration control signal c2 to the FPGA 31. Thereby, the configuration data of the FPGA 31 is transferred from the data bus d7 to the FPGA 31. The FPGA 31 is set based on the configuration data.

  Next, the MPU 20 (software 25) asserts the address signal a8 and the read signal r8 to the address decoding unit 37. Upon receiving the assertion of the address signal a8 and the read signal r8, the address decoding unit 37 asserts the address signal a7, the select signal s7, and the read signal r7 to the flash access control unit 32. The flash access control unit 32 acquires the initial program loader from the flash memory 12 via the data bus d5 in the same manner as when the configuration data of the FPGA 31 is acquired from the flash memory 12. The initial program loader is transferred to the data bus d8 between the address decoding unit 37 and the MPU 20 via the data bus d7 between the flash access control unit 32 and the address decoding unit 37. Thereby, the loading operation of the initial program loader is completed in the MPU 20.

  Next, an operation for updating the configuration data of the FPGA 31 will be described. When updating the configuration data of the FPGA 31, the MPU 20 asserts the address signal a8 and the write signal w8 to the address decoding unit 37, and passes the new configuration data to the address decoding unit 37 via the data bus d8. In response to the assertion of the address signal a8 and the write signal w8, the address decoding unit 37 asserts the address signal a7 and the write signal w7 to the flash access control unit 32. The address decoding unit 37 passes new configuration data to the flash access control unit 32 via the data bus d7.

  The flash access control unit 32 asserts an address signal a5 to the flash memory 12, and passes new configuration data to the flash memory 12 via the data bus d5. Further, the flash access control unit 32 asserts a write signal w6 to the flash interface unit 39. Upon receiving the assertion of the write signal w6, the flash interface unit 39 asserts the select signal s5 and the write signal w5 to the flash memory 12. Thereby, new configuration data is written into the flash memory 12.

  Next, an operation of operating the terminal 43 to write information regarding the flash memory in the flash memory information storage unit 40 will be described. When writing information related to the flash memory in the flash memory information storage unit 40, the MPU 20 first asserts the address signal a8 and the write signal w8 to the address decoding unit 37, and the address decoding unit 37 via the data bus d8. Information about the flash memory to be written to. Upon receiving the assertion of the address signal a8 and the write signal w8, the address decoding unit 37 recognizes that it is a write instruction to the flash memory information storage unit 40.

  Then, the address decoding unit 37 asserts the address signal a9, the select signal s9, and the write signal w9 to the storage unit interface unit 38, and passes information related to the flash memory to the storage unit interface unit 38 via the data bus d7. In response to the assertion of the address signal a9, the select signal s9, and the write signal w9, the storage unit interface unit 38 asserts the address signal a2, the select signal s2, and the write signal w2 to the flash memory information storage unit 40. The storage unit interface unit 38 passes information related to the flash memory to the flash memory information storage unit 40 via the data signal line d2. As a result, information about the flash memory is written into the flash memory information storage unit 40.

  Next, an operation of operating the terminal 43 to read information on the flash memory from the flash memory information storage unit 40 will be described. When reading information about the flash memory from the flash memory information storage unit 40, the MPU 20 first asserts the address signal a 8 and the read signal r 8 to the address decoding unit 37. Upon receiving the assertion of the address signal a8 and the read signal r8, the address decoding unit 37 recognizes that it is a read instruction from the flash memory information storage unit 40.

  The address decoding unit 37 asserts the address signal a9, the select signal s9, and the read signal r9 to the storage unit interface unit 38. In response to the assertion of the address signal a9, the select signal s9, and the read signal r9, the storage unit interface unit 38 asserts the address signal a2, the select signal s2, and the read signal r2 to the flash memory information storage unit 40. Thereby, information about the flash memory is sent from the flash memory information storage unit 40 to the terminal 43 via the data signal line d2, the data bus d7, the data bus d8, and the MPU 20.

FIG. 7 is a sequence diagram illustrating a processing procedure when the information processing apparatus according to the second embodiment is started up. In the sequence diagram shown in FIG. 7, in the flash memory, the area for storing the FPGA configuration data is the flash memory (for configuration), and the area for storing the initial program loader is the flash memory (for IPL).

  As shown in FIG. 7, when the information processing apparatus is powered on (step S1), first, the flash memory control hardware acquires information about the installed flash memory from the flash memory information storage unit. (Step S2). Then, the flash memory control hardware internally holds information related to the flash memory (step S3). Next, the flash memory control hardware issues a read mode return command corresponding to the flash memory (for configuration) based on the information about the flash memory (step S4). Then, the flash memory control hardware loads the FPGA configuration data from the flash memory (for configuration) and provides the configuration data to the FPGA (step S5). Thereby, the setting (configuration) of the FPGA is performed (step S6).

  Next, the MPU instructs the flash memory control hardware to load the initial program loader (step S7). The flash memory control hardware issues a read mode return command corresponding to the flash memory (for IPL) based on the information about the flash memory (step S8). Then, the flash memory control hardware loads the initial program loader from the flash memory (for IPL) and provides the initial program loader to the MPU (step S9). Thereby, bootup processing is performed in the MPU (step S10), and the information processing apparatus transitions to the operation state (step S11).

FIG. 8 is a sequence diagram illustrating a processing procedure when updating the configuration data of the information processing apparatus according to the second embodiment. In the sequence diagram shown in FIG. 8, in the flash memory, an area for storing FPGA configuration data is a flash memory (for configuration), and an area for storing an initial program loader is a flash memory (for IPL).

  As shown in FIG. 8, when the process of updating the FPGA configuration data is started, first, the software instructs the flash memory control hardware to erase the flash memory (for configuration) (step S21). ). The flash memory control hardware issues an erase command corresponding to the flash memory (for configuration) based on the information about the flash memory held inside (step S22). Thereby, the FPGA configuration data is erased from the flash memory (for configuration) (step S23). When the erasure of the corresponding sector is completed, the flash memory (for configuration) returns an erasure completion notification to the flash memory control hardware (step S24). The flash memory control hardware returns an erasure completion notification to the software (step S25).

  Next, the software loads new configuration data from another device such as an external storage device (step S26). Then, the software instructs the flash memory control hardware to write (update) new configuration data (step S27). The flash memory control hardware issues a write command corresponding to the flash memory (for configuration) based on the information about the flash memory held inside, and new configuration data is stored in the flash memory (for configuration). Transfer (step S28). Thereby, new configuration data is written to the flash memory (for configuration), and the configuration data is updated (step S29). When the writing of new configuration data is completed, the flash memory (for configuration) returns a write completion notification to the flash memory control hardware (step S30). The flash memory control hardware returns a write completion notification to the software (step S31).

  Next, the software instructs the flash memory control hardware to reconfigure the FPGA (step S32). The flash memory control hardware issues a read mode return command corresponding to the flash memory (for configuration) based on the information about the flash memory (step S33). Then, the flash memory control hardware loads FPGA configuration data from the flash memory (for configuration), and provides the configuration data to the FPGA (step S34). Thereby, resetting (reconfiguration) of the FPGA is performed (step S35), and the information processing apparatus transitions to the operation state (step S36).

Operation of Initial Load Control Unit and Flash Access Control Unit FIGS. 9 to 11 are flowcharts illustrating the operation of the information processing apparatus according to the second embodiment. When the information processing apparatus is powered on (step S41), the information processing apparatus first obtains information about the installed flash memory from the flash memory information storage section by the initial load control section (step S42). Next, the information processing apparatus generates a sector configuration table and a command table based on information about the mounted flash memory by the initial load control unit (steps S43 and S44). Either the sector configuration table or the command table may be generated first. The operation so far is controlled by the initial load control unit. Subsequent operations are controlled by the flash access controller.

  Next, the information processing apparatus uses the flash access control unit to interpret the instruction content from the software (MPU), and waits until an erase instruction, a write instruction, or a read instruction is accepted (steps S45, S53, and S54). When the erasure instruction is accepted (step S45: Yes), the information processing apparatus acquires an erasure command from the command table by the flash access control unit, and issues the head command of the erasure command to the flash memory (step S46).

  For example, when the installed flash memory is a flash memory manufactured by Company A (see FIG. 5), AAA is stored in the area of the head address of the erase command in the command table. AA is stored in the area of the next address in the command table. Thereafter, 555, 55, AAA, 80, AAA, AA, 555, 55, SA, and 30 are stored each time the command table address advances by one. Therefore, the information processing apparatus increments the address of the command table (step S47) and stores it in the area of the address until 30 which is the last command of the erase command is issued (step S48: No). A command is issued (step S46).

  When all the erase commands have been issued (step S48: Yes), the information processing apparatus confirms the status information in the flash memory by the flash access control unit (step S49), and erases the sector being erased. Is completed (step S50: No). When the erasure of the sector being erased is completed (step S50: Yes), the information processing apparatus increments the address of the sector configuration table until the erasure of all the sectors in the designated erase range is completed (step S52: No). (Step S51), the erase operation after Step S46 is repeated. In each address area of the sector configuration table, the capacity of each sector is stored, for example, as HEX converted data. When the erasure of all the sectors in the erasure designated range is completed (step S52: Yes), the process is terminated.

  On the other hand, when the write instruction is accepted (step S45: No, step S53: Yes), as shown in FIG. 10, the information processing apparatus acquires a write command from the command table by the flash access control unit, The first command of the write command is issued to the memory (step S61).

  For example, when the installed flash memory is a flash memory manufactured by company A (see FIG. 5), AAA is stored in the area of the head address of the write command in the command table. AA is stored in the area of the next address in the command table. Thereafter, every time the address of the command table advances, 555, 55, AAA, AA, PA (program address) and PD (program data) are stored. Therefore, the information processing apparatus increments the address of the command table (step S62) until the PD (program data), which is the last command of the write command, is issued (step S63: No). The command stored in is issued (step S61).

  When all the commands of the write command have been issued (step S63: Yes), the information processing apparatus writes data to the flash memory by the flash access control unit (step S64). Then, the information processing apparatus waits for the completion of data writing (Step S66: No) while confirming the status information in the flash memory by the flash access control unit (Step S65). When the data writing is completed (step S66: Yes), the information processing apparatus repeats the writing operation after step S64 until the writing of the writing designated range is completed (step S67: No). When the writing of the writing designated range is completed (step S67: Yes), the process is terminated.

  On the other hand, when a read instruction is accepted (step S45: No, step S53: No, step S54: Yes), the information processing apparatus acquires a read command from the command table by the flash access control unit as shown in FIG. Then, the head command of the read command is issued to the flash memory (step S71).

  For example, when the installed flash memory is a flash memory manufactured by Company A (see FIG. 5), arbitrary data is stored in the area of the head address of the read command in the command table. F0 is stored in the area of the next address in the command table. Accordingly, the information processing apparatus increments the address of the command table (step S72) and stores it in the address area until F0, which is the last command of the read command, is issued (step S73: No). A command is issued (step S71).

  When all of the read commands are issued (step S73: Yes), the information processing apparatus reads data from the designated start address of the flash memory by the flash access control unit (step S74). Then, the information processing apparatus repeats the data reading operation until the reading designated range is completely read (step S75: No). When the reading of the reading designated range is completed (step S75: Yes), the process ends.

  According to the second embodiment, the same effect as the first embodiment can be obtained. In addition, it is possible to reduce development costs, test costs, and software update costs in the field associated with changes to the software that controls the flash memory. In addition, any type of flash memory can be mounted on the board as long as it is a pin-compatible flash memory. Therefore, the flash memory can be procured not only from a specific manufacturer but also from various manufacturers. Conventionally, the flash memory is stocked in the factory in preparation for a failure after shipment from the factory. However, since the flash memory can be procured from various manufacturers, it is not necessary to stock the flash memory. Accordingly, the cost for storing the flash memory, the number of work steps, the space for the warehouse, etc. are not required, and the cost can be reduced. Note that a flash memory for storing programmable device configuration data and a flash memory for storing an initial program loader may be provided separately.

  The following additional notes are disclosed with respect to the first and second embodiments.

(Supplementary Note 1) In an information processing apparatus equipped with a flash memory, for each of a plurality of flash memories including the installed flash memory, a storage unit for storing information related to the flash memory, and information stored in the storage unit An information processing apparatus comprising: a control unit configured to control access to the mounted flash memory based on information on the mounted flash memory.

(Supplementary note 2) The information processing apparatus according to supplementary note 1, wherein the information relating to the flash memory includes information relating to a sector of the flash memory and information relating to a command for controlling the flash memory.

(Supplementary Note 3) The control unit controls data erasing operation, writing operation, and reading operation for the mounted flash memory based on information on the sector of the flash memory and information on a command for controlling the flash memory. The information processing apparatus according to attachment 2, wherein:

(Supplementary Note 4) A storage unit for storing information for controlling access to the flash memory, and information related to the mounted flash memory is acquired from the storage unit when the apparatus is activated, and the flash included in the acquired information The information processing apparatus according to appendix 3, further comprising: an acquisition unit that stores information on a sector of the memory and information on a command for controlling the flash memory in the storage unit.

(Additional remark 5) The said memory | storage part is provided with the rewritable non-volatile memory which stores the information regarding the said flash memory, The information processing apparatus of Additional remark 4 characterized by the above-mentioned.

(Supplementary note 6) The information processing apparatus according to any one of supplementary notes 1 to 5, wherein the flash memory stores information defining a logical specification of a programmable device.

(Supplementary note 7) The information processing apparatus according to any one of supplementary notes 1 to 6, wherein the flash memory stores an initial program loader that is executed when the apparatus is activated.

DESCRIPTION OF SYMBOLS 1,11 Information processing apparatus 2,12 Flash memory 3,13,40 Storage part 4,14,32,33 Control part 5,6,15,16 Information about flash memory 17,34 Acquisition part 18,35,36 Storage part 19, 31 Programmable devices 21 Information defining logical specifications of programmable devices 22 Initial program loader 23 Information on sectors of flash memory 24 Information on commands for controlling flash memory

Claims (5)

In information processing devices equipped with flash memory,
For each of a plurality of flash memories including a mounted flash memory, a storage unit that stores information about the flash memory;
A control unit that controls access to the mounted flash memory based on information about the mounted flash memory of the information stored in the storage unit;
An information processing apparatus comprising: The information processing apparatus according to claim 1, wherein the information about the flash memory includes information about a sector of the flash memory and information about a command for controlling the flash memory. The control unit controls an erasing operation, a writing operation, and a reading operation of data with respect to the mounted flash memory based on information on a sector of the flash memory and information on a command for controlling the flash memory. The information processing apparatus according to claim 2. A storage unit for storing information for controlling access to the flash memory;
When the apparatus is started, information on the installed flash memory is acquired from the storage unit, and information on a sector of the flash memory and information on a command for controlling the flash memory included in the acquired information are stored in the storage unit An acquisition unit to
The information processing apparatus according to claim 3, further comprising:   The information processing apparatus according to claim 4, wherein the storage unit includes a rewritable nonvolatile memory that stores information about the flash memory.

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