JPH11122235A - Frame synchronization detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronization detection circuit suppresive in the increase of circuit scale by simplify the circuit configuration and capable of dealing with the data of a different frame format. SOLUTION: Synchronization detection object data are serially given to a memory 10. A memory control section 11 extracts a data code from the memory 10 through an address and provides an output to a code pattern output circuit 12. The code pattern output circuit 12 integrates the data code by using a shift register and provides an output of the data code pattern to a frame synchronization code comparator circuit 14. The frame synchronization code comparator circuit 14 compares an output of the code pattern output circuit 12 with an output of a frame synchronization code generating circuit 13 and provides an output of a timing signal when they are coincident. Then frame synchronization is discriminated even for data of a frame format where an insertion position of the extracted synchronization code is different by changing an output address of the memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a frame synchronization detection circuit used when demodulating telemetry data transmitted from, for example, a satellite in a ground apparatus.

[0002]

2. Description of the Related Art Telemetry data is a kind of multiplexed data including image data obtained by several types of image sensors. As shown in FIG. 4, frame data (data superimposed on a frame, data superimposed on a frame, The same applies hereinafter). The processing unit may be, for example, a frame data group representing image data for one screen. In this case, a frame data group for one screen may be called a major frame, and a plurality of frame data constituting one major frame may be called a minor frame. Major frames or individual minor frames (for convenience, these may be simply referred to as frames)
, A frame synchronization code FS is inserted.

In the ground equipment, first, a frame synchronization detecting circuit detects bit synchronization and frame synchronization of received telemetry data based on the frame synchronization code FS. After the synchronization is detected, the timing signal and the processed image data are demodulated and reproduced by the telemetry demodulation circuit and output to an external device such as a computer.

[0004]

The transmission data, for example, image data included in the telemetry data has a sensor-specific frame format. As described above, since the frame synchronization code is continuously inserted into a specific area in a frame, conventionally, it has been necessary to establish frame synchronization for each sensor. In order for the frame synchronization determination circuit to correspond to each of the different types of sensors, it is necessary to extract the frame synchronization code FS from an arbitrary area of each frame. However, if the frame synchronization code FS is to be extracted from an arbitrary area in the frame, a shift register for holding data for a continuous frame synchronization code and a shift register for holding data for at least another frame are required. This necessitates simplification of the circuit configuration for detecting frame synchronization.

Further, as shown in FIG. 2, one minor frame is further divided into a plurality of frames, and a frame synchronization code which is continuous in a specific area in the frame is inserted into each divided frame to transmit telemetry data. There are cases. In this case, the frame synchronization is performed by using a plurality of frame synchronization codes (FS1 to FS in the illustrated example) from each divided frame.
4) is extracted and arranged, and this arrangement is performed by comparing this arrangement pattern with a previously prepared synchronization code pattern. However, in such a method, a shift register for holding data in each minor frame is required, and the configuration of the frame synchronization detection circuit becomes large.

[0006] Such a problem occurs commonly in transmission data in which one frame is composed of a plurality of subframes and a frame synchronization code is inserted in each subframe, in addition to the telemetry data. Was rare.

Accordingly, an object of the present invention is to suppress an increase in circuit size when detecting a frame synchronization code from subframe data into which the frame synchronization code is inserted and performing frame synchronization, An object of the present invention is to provide an improved frame synchronization detecting circuit which can flexibly cope with target data of a format.

[0008]

In order to solve the above-mentioned problems, the present invention comprises a plurality of sub-frames, each of which constitutes one frame, and in which each frame has a frame synchronization code inserted therein, for example, telemetry data. In a frame synchronization detection circuit for detecting synchronization, a memory in which a data storage area can be specified by an address, for example, a random access memory, and a memory control unit that stores and extracts the transmission data in the memory through the address, A code pattern output circuit for arranging the target data extracted in time series by the memory control unit and outputting the data as a data code pattern of the frame; a data code pattern output from the code pattern output circuit and a predetermined synchronization code And a code comparison circuit for comparing with a pattern. Based on the comparison result in the code comparing circuit and performs synchronization detection of the target data.

The memory has, for example, the same number of data areas as the number of sub-frames constituting one frame, and is configured such that the addresses of each data area are continuous. Each capacity has the same size.

The code pattern output section includes the same number of shift registers as the data area.
It is configured to output a data code pattern corresponding to the relative position of the sub-frame in the frame. In this case, the shift register is configured to hold the target data for the discontinuous frame synchronization code. As a result, discontinuous frame synchronization codes can be extracted, and the circuit configuration can be simplified.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to synchronous detection of telemetry data will be described below with reference to the drawings. FIG. 1 is a block diagram of the frame synchronization detection circuit according to the present embodiment. The frame synchronization determination circuit includes a memory 10, a memory control unit 11, a code pattern output circuit 12, a frame synchronization code generation circuit 13,
The frame synchronization code comparison circuit 14 is included.

The memory 10 is a 1-bit data bus RAM
(Random access memory), for example, 2
00 (h), that is, four data areas 10a to 10d having a capacity of 512 bits. First data area 10
a to the fourth data area 10d are set to 0
(H) to 1FF (h), 200 (h) to 3FF (h),
400 (h) -5FF (h), 600 (h) -7FF
(H). The data to each of the data areas 10a to 10d can be continuously transferred by the memory control unit 11 through the address.

The number of code pattern output circuits 12 is equal to the number of data areas, in this example, four shift registers 12a to 12a.
2d, and outputs a data code pattern to the frame synchronization code comparison circuit 14 while shifting data bit by bit based on a signal sent from the memory control unit 11. Each of the shift registers 12a to 12d holds a data code corresponding to a discontinuous frame synchronization code.

The frame synchronization code generation circuit 13 previously holds synchronization code patterns used for determining whether or not synchronization has been established. These synchronization code patterns are synchronized with the code pattern output circuit 12 to perform frame synchronization. The data is output to the code comparison circuit 14.

In this embodiment, as shown in FIG. 2, the telemetry data to be subjected to synchronization detection comprises 256 words (one word is 8 bits) and constitutes one frame.
Each frame is composed of four subframes (one subframe has 64 words). “FS1”, which is obtained by dividing the frame synchronization code of one frame into four,
“FS2”, “FS3”, and “FS4” are the head portions of each subframe, that is, w0, w64, w128, and w19.
2 and are stored in the respective data areas 10a to 10d through the memory control unit 11.

Next, the operation of the frame synchronization detection circuit will be described. The memory control unit 11 inputs the telemetry data serially, and stores addresses 0 to 0 of the first data area 10a.
Data for 200 (h) is sequentially accumulated in the area designated by 1FF (h). Then, when the 201 (h) -th data is input, the data accumulated at the address 0 (h) is transferred to the shift register 12a and the second data area 10b.
To the area of address 200 (h).

Similarly, 4 to address 0 to 3FF (h)
00 (h) data is stored in the memory 10,
When the (h) -th data is input to the memory 10, the data stored at the address 0 (h) is transferred to the shift register 12a and the address 200 (h) of the second data area 10b.
And the data at the address 200 (h) is transferred to the shift register 12b and the address 400 in the third data area 10c.
(H).

By these operations, finally, the memory 10
The data of one frame is accumulated from the address 0 to 7FF (h) of the memory 10, and at this time, the addresses 200 (h) to 207 of the memory 10 are stored in the shift register 12a, the shift register 12b, and the shift register 12c, respectively.
(H), 400 (h) to 407 (h), and the same data code as the data stored in 600 (h) to 607 (h) is held. Further, when the data of the next frame is input to the memory 10, the shift register 2
d is also sequentially output to the memory 10.
Is equivalent to four 512-bit shift registers.

The data codes output from the code pattern output circuit 12 to the frame synchronization code comparison circuit 14 are w0, w64, w12, as shown in FIG.
8, w192 can be handled as a continuous data pattern.

The frame synchronization code comparison circuit 14 compares the output of the code pattern output circuit 12 with the output of the frame synchronization code generation circuit 13 and, when the code patterns match, outputs a synchronization match timing signal to an external device. Output.

As described above, in the frame synchronization detecting circuit according to the present embodiment, a memory (random access memory) 10 having an area for one frame, and a memory control for controlling data storage and reading of the memory 10 are provided. Since it is sufficient to have the unit 11, it is possible to detect the synchronization of telemetry data with an extremely simple circuit configuration as compared with a conventional circuit having a shift register for one frame length or the like.

Also, since the frame synchronization code output from the frame synchronization code generation circuit 14 and the data code pattern read from the memory 10 can be changed by software processing, data of different frame formats by different types of sensors can be handled.

[0023]

As is clear from the above description, according to the frame synchronization detecting circuit of the present invention, it is not necessary to have a shift register for the frame length of the target data, so that an increase in the circuit scale can be suppressed. become able to. Further, it becomes possible to flexibly cope with target data of different frame formats.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronization determination circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of data input to a frame synchronization determination circuit according to the embodiment.

FIG. 3 is a diagram showing an example of output data of a code pattern output circuit.

FIG. 4 is an explanatory diagram of telemetry data.

[Explanation of symbols]

Reference Signs List 10 memory (random access memory) 10a to 10d data area 11 memory control unit 12 code pattern output circuit 12a to 12d shift register 13 frame synchronization code generation circuit 14 frame synchronization code comparison circuit FS frame synchronization code w0, w64, w128, w192 Code indicating position in frame

Claims (7)

[Claims] A frame synchronization detecting circuit for detecting the synchronization of target data in which one frame is composed of a plurality of subframes and a frame synchronization code is inserted in each subframe, wherein a data storage area can be specified by an address. A memory control unit that stores and extracts the transmission data in the memory through the address; and a code that arranges the target data extracted by the memory control unit in time series and outputs the data as a data code pattern of the frame. A pattern output circuit; and a code comparison circuit that compares a data code pattern output from the code pattern output circuit with a predetermined synchronization code pattern. The target data is generated based on a comparison result of the code comparison circuit. Frame synchronization detection characterized by performing frame synchronization detection Road. 2. The frame synchronization detecting circuit according to claim 1, wherein the memory has the same number of data areas as the number of sub-frames constituting one frame, and the addresses of each data area are continuous. 3. The code pattern output unit includes the same number of shift registers as the data area, and outputs a data code pattern corresponding to a relative position of a subframe in one frame. The frame synchronization detection circuit according to the above. 4. The frame synchronization detecting circuit according to claim 3, wherein said shift register is configured to hold target data for discontinuous frame synchronization codes. 5. The frame synchronization detecting circuit according to claim 3, wherein the capacities of the individual data areas are the same. 6. The frame synchronization detecting circuit according to claim 1, wherein said memory is a random access memory. 7. The frame synchronization detecting circuit according to claim 1, wherein said transmission data is telemetry data including a frame data group organized in processing units.