JPH11122045A - Fet mixer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a radio-frequency transmission(RF) signal of high output and high frequency by using a local oscillation(LO) signal of high output and low frequency by connecting 1st and 2nd FET gates in parallel by a transmission line as a delay circuit. SOLUTION: An LO signal inputted to an LO port 110 is passed via a transmission line 106 and inputted to a gate 102a of a 1st FET 102 and a gate 104a of a 2nd FET 104 not through the transmission line 106. The transmission line 106 has an electric length which is equivalent to 1/2 wavelength at the LO signal frequency of the input of the LO port 110, and the 1st LO signal to the 1st FET 102 is delayed by a time equivalent to 1/2 wavelength behind the 2nd LO signal to the 2nd FET 104. The 1st FET 102 mixes the 1st LO signal and a 1st IF signal, the 2nd FET 104 mixes the 2nd LO signal, and a 2nd IF signal to generate 1st and 2nd RF signals, and a power composition unit 108 cancels out of-phase frequency components and put in-phase components together. Then the resulting signal is taken as an RF signal out of an RF port 114 provided at the connection point D of the power composition unit 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the use of an FET (field effect transistor) to control the frequency of each of a local oscillation signal (LO signal) and an input signal (for example, an IF signal as an intermediate frequency). The present invention relates to a mixer circuit (FET mixer circuit) that generates a frequency component of a sum or a difference (for example, an RF signal as a radio frequency).

A mixer circuit that generates a frequency component having the sum of the respective frequencies of the LO signal and the IF signal is called an up-converter, and a mixer that generates a frequency component having a difference value between the respective frequencies. The circuit is called a down converter, and in particular, the present invention relates to an FET mixer circuit suitable for an up converter.

[0003]

2. Description of the Related Art A conventional FET mixer circuit is disclosed in, for example, Reference 1 (T. Hirota et al., 1984).
IEEE MTT Vol. MTT-32 (7) p
p. 679-683, July 1984).

Prior to describing the present invention, this conventional FET mixer circuit will be described with reference to FIG. That is, the FET mixer circuit 10 basically includes one F
An ET (field effect transistor) 12, a gate bias voltage application circuit 22, a high frequency cutoff circuit 20 for applying a gate bias voltage, a drain bias voltage application circuit 30, and a drain bias voltage application High frequency cutoff circuit 28, LO port (local frequency oscillation port) 32, IF port (intermediate frequency oscillation port) 34, RF port (radio frequency oscillation port) 36
And

[0005] The conventional FET mixer circuit has
It has the following circuit configuration. The gate 12 a of the FET 12 is connected to the LO port 32 to which the LO signal is input via the LO signal input matching circuit 14. A low-pass IF signal input matching circuit (IF filter) 18 is connected to a connection point b between the LO port 32 and the LO signal input matching circuit 14. The IF filter 18 is connected to the IF port 3 via a capacitor 38a.
4 is connected. Also, this IF filter 18 and
The connection middle point a of the capacitor 38a is connected to the gate bias voltage application circuit 2 for applying a direct current (DC) gate bias voltage via the high frequency cutoff circuit 20 described above.
2 are connected.

Furthermore, the drain 12b of the FET 12
Are the RF signal output matching circuit 16 and the capacitor 38b
Is connected to the RF port 36 through a series circuit of.
A connection point c between the RF signal output matching circuit 16 and the capacitor 38b is connected to the ground (earth terminal) 40 via a series circuit of the RF blocking filter 26, the high frequency cutoff circuit 28, and the capacitor 38c. And
The drain bias voltage applying circuit 3 is connected to the intermediate point d between the RF blocking filter 26 and the high frequency blocking circuit 28.
0 is connected. The source 12c of the FET 12
Is connected to the ground 40.

Here, in the conventional FET mixer circuit 10, an ultra-high frequency LO signal input to the LO port 32 is a signal oscillated by a millimeter wave oscillator (not shown) and an amplifier (not shown). Or by using a multiplier (not shown) to increase the frequency.
When the LO signal is input to the LO port 32, the LO signal is input to the gate 12a of the FET 12 whose source is grounded via the LO signal input matching circuit 14.

From the IF port 34, an IF signal (intermediate frequency) of a relatively low frequency (for example, 1 to 5 GHz) is supplied to the gate 12a of the FET 12 through the connection point b.
Is input to

And a gate bias voltage application circuit 2
2, a gate bias voltage is applied to the gate 12a of the FET 12 through the high-frequency cutoff circuit 20,
From the drain bias voltage application circuit 30, the FET 12
A drain bias voltage is applied to the drain 12b, and the position of the operating point of the FET 12 is adjusted.

Therefore, the LO signal and the IF signal input to the gate 12a of the FET 12 are mixed in the FET 12, respectively, and their respective frequencies are added, that is, the frequency of the LO signal (hereinafter referred to as L).
O frequency) and IF signal frequency (hereinafter, IF frequency)
Are summed to obtain an RF signal having the value of the sum of these frequencies. That is, the FET mixer circuit 10
The LO signal and the IF signal are mixed into an RF signal in a state where the reflection coefficient on the input side of the LO signal is modulated due to the input of the LO signal of an ultra-high frequency due to the nonlinear characteristic of the ET 12. The RF signal is output from the RF port 36.

The RF blocking filter 26 effectively prevents input of an RF signal to the high-frequency cutoff circuit 28 and the drain bias voltage application circuit 30 while applying a direct current (DC) to the drain 12 b of the FET 12. A certain drain bias voltage can be applied.

[0012]

However, in the conventional FET mixer circuit, the LO signal having an extremely high frequency and the IF signal having a relatively low frequency are directly converted into one F signal.
Mixing using ET. Therefore, for example, 5
In order to generate an LO signal of about 0 GHz with a millimeter wave oscillator, there is a problem that the output of the LO signal is reduced due to the performance of the millimeter wave oscillator. For example, frequency 30G
In a millimeter-wave oscillator that generates an LO signal in Hz,
The output was about 0 dBm, but the frequency was 60 GHz.
In the millimeter wave oscillator that generates the LO signal of
The output is reduced to about dBm.

Therefore, when an IF signal having a frequency of, for example, about 1 to 5 GHz is to be mixed using an LO signal having an extremely high frequency of about 50 GHz, an amplifier is provided between the millimeter wave oscillator and the LO port. Thus, it is necessary to increase the output of the low-output LO signal to, for example, about 0 dBm.

On the other hand, L of a relatively low frequency of less than 30 GHz
The O signal is generally referred to as a quasi-millimeter wave particularly among millimeter waves. However, if such a quasi-millimeter wave LO signal is used, even if a general millimeter-wave oscillator is used, it can be generated as a relatively high-output LO signal. Can be. However, since the frequency of the LO signal (quasi-millimeter wave) is insufficient, it is necessary to increase the frequency of the LO signal (quasi-millimeter wave) by providing a multiplier between the millimeter wave oscillator and the LO port. there were.

Therefore, in any case, it is necessary to provide a space or a wiring for providing an amplifier or a multiplier near the LO port in the FET mixer circuit, and the FET mixer circuit becomes large-scale (large area). Or the degree of freedom in designing the FET mixer circuit is excessively limited.

[0016] For this reason, the oscillator is oscillated using a general oscillator and has a high output, for example, about 20 to 30 GHz.
Even if the LO signal has a relatively low frequency, it can be mixed with the IF signal without providing a multiplier, and is small in scale and has a high degree of freedom in designing the FET mixer circuit.
The advent of an ET mixer circuit has been desired.

[0017]

According to the mixer circuit using the FET (field effect transistor) of the first embodiment of the present invention, as the FET used in the mixer circuit, the first FET whose source is grounded is used. And a source-grounded second FET. A transmission line having a gate of the first FET connected to one end and a gate of the second FET connected to the other end, the transmission line having an LO port connected to one end; The transmission line has an electrical length substantially corresponding to a half wavelength with respect to the frequency of the LO signal input from the LO port, and furthermore, the transmission line of the first FET in the transmission line. An IF port is connected to a position having substantially the same electrical length from the gate and the gate of the second FET.

Further, a gate bias voltage applying circuit is connected to the gate of the first FET and the gate of the second FET, and the drain of the first FET and the drain of the second FET are connected. Is connected to a drain bias voltage application circuit.

The drain of the first FET and the second
Is connected using a power combiner, and an RF port is provided at a position where the electrical length is substantially equal from the drain of the first FET and the drain of the second FET in the power combiner. Connected.

When the FET mixer circuit (first embodiment) is configured in this manner, the drain of the first FET and the drain of the second FET in a parallel relationship in the power combiner due to the effect of the transmission line. The connection point becomes a virtual short-circuit point for the LO signal. That is, the fundamental waves of the LO signal are transmitted through the transmission line at the time when they are input to the power combiner from the drain of the first FET and the drain of the second FET, respectively.
Since the respective phases are in opposite phase relation, they can be canceled out in terms of phase.

On the other hand, the second harmonic having twice the frequency of the fundamental wave of the LO signal generated in each of the first FET and the second FET is supplied to the drain of the first FET and the second FET. Since the phases are in-phase at the time when they are input to the power combiner from the drains of the two, the phases do not cancel each other.

Therefore, the first FET and the second F
In each of the ETs, the L input from the LO port
Although the frequency of the O signal is relatively low, the second harmonic of the LO signal is used as a high frequency LO signal (about twice the frequency of the LO signal input from the LO port) while maintaining a high output. Can be. That is, such LO
Since the second harmonic of the signal and the IF signal are mixed in each of the first FET and the second FET, a high-output signal can be extracted from the RF port as an RF signal.

The transmission line is inexpensive, and the use of the transmission line substantially reduces the frequency of the LO signal to １ ／.
It is also preferable in that it is easy to design an electrical length corresponding to the wavelength.

Further, according to the mixer circuit using the FET (field effect transistor) of the second embodiment of the present invention, as the FET used in the mixer circuit, the first FET whose source is grounded and the source grounded FET are used. The second F
It has ET. Further, the transmission line includes a transmission line in which a gate of the first FET is connected to one end and a gate of the second FET is connected to the other end, and the transmission line has an LO port connected to one end. This transmission line has an electrical length substantially corresponding to a half wavelength of the frequency of the LO signal input from the LO port.

A gate bias voltage application circuit is connected to the gate of the first FET and the gate of the second FET, and the gate of the first FET and the drain of the second FET are connected to each other. In this case, the IF port and the circuit for applying the drain bias voltage are connected.
From the F port to the drain of the first FET and the second FE
The electrical length of the T to the drain is substantially equal.

Further, the drain of the first FET and the second
Is connected using a power combiner, and an RF port is provided at a position where the electrical length is substantially equal from the drain of the first FET and the drain of the second FET in the power combiner. Connected.

When the FET mixer circuit (second embodiment) is configured in this manner, the drain of the first FET in a parallel relationship is connected to the drain of the first FET due to the effect of the transmission line, similarly to the FET mixer circuit of the first embodiment. The connection point of the power combiner with the drain of the second FET becomes a virtual short-circuit point for the LO signal, and the fundamental waves of the LO signal cancel each other out (canceled). Meanwhile, the first FE
The second harmonic having twice the frequency of the fundamental of the LO signal generated by the T and the second FET, respectively, is the first F
Since the phases are in phase with each other when they are input to the power combiner from the drain of the ET and the drain of the second FET, respectively, they are used as high output, high frequency LO signals without canceling out in phase. can do.

Further, according to the FET mixer circuit of the second embodiment, the IF port is provided on the drain side of the FET, and the IF signal is input to the drain of the FET. Since S ₁₂ (feedback from the drain to the gate of the FET) is small, the L level of the IF signal is low.
The effect of suppressing leakage to the O port is also obtained. Therefore, separation between these ports is achieved, and the IF signal and the second harmonic of the LO signal can be more efficiently mixed without reducing the IF signal.

Further, according to the mixer circuit using the FET (field effect transistor) of the third embodiment of the present invention, as the FET used in the mixer circuit, the first source-grounded FET and the source-grounded FET are used. The second F
It has ET. Further, the transmission line includes a transmission line in which a gate of the first FET is connected to one end and a gate of the second FET is connected to the other end, and the transmission line has an LO port connected to one end. The transmission line has an electrical length corresponding to a wavelength substantially at half the frequency of the LO signal input from the LO port.

The gate of the first FET and the second
A gate bias voltage applying circuit is connected to the gate of the FET, and a drain bias voltage applying circuit is connected to the drain of the first FET and the drain of the second FET. An IF port is connected to the source of the first FET and the source of the second FET, and the electrical length from the IF port to the source of the first FET and the source of the second FET is substantially equal. I have.

Further, the drain of the first FET and the second
Is connected using a power combiner, and an RF port is provided at a position where the electrical length is substantially equal from the drain of the first FET and the drain of the second FET in the power combiner. Connected.

When the FET mixer circuit (third embodiment) is configured in this manner, similar to the FET mixer circuits of the first embodiment and the second embodiment, due to the effect of the transmission line, the second mixer is in a parallel relationship. The drain of the first FET and the second
Is a virtual short-circuit point for the LO signal, and the fundamental waves of the LO signal cancel each other out (canceled). On the other hand, the first F
A second harmonic having a frequency twice the fundamental of the LO signal generated by the ET and the second FET, respectively, is generated from the drain of the first FET and the drain of the second FET.
At the time when each is input to the power combiner, the phases are in phase, so they do not cancel each other out in phase,
It can be used as a high power, high frequency LO signal.

Further, according to the FET mixer circuit of the third embodiment, the LO port is connected to the first and second FEs.
The first and second FEs provided for the gate of T
An LO signal is input to the gate of T, and an IF port is provided for the sources of the first and second FETs, and an IF signal is input to the sources of the first and second FETs. Is provided for the drains of the first and second FETs, and the RF signal is extracted from the drains of the first and second FETs. That is, each terminal (gate, source, drain) of the three-terminal FET
Since the LO port, the IF port, and the RF port are provided for the
There is no risk of leakage to the port,
The signal can be more efficiently mixed with the second harmonic of the signal, and the isolation between the ports can be ensured.

Further, as described above, the FET mixer circuit (third
Of the present embodiment), the LO port, the IF port, and the RF port can be disposed at physically separated positions, and include other circuit elements other than the LO port and the like. In addition, the design and arrangement of the entire FET mixer circuit are improved.

The FET mixer circuit of the present invention (third
In the embodiment, it is preferable to provide a common source circuit for the source of the first FET and the source of the second FET.

As described above, when the FET mixer circuit (third embodiment) is configured by providing the common source circuits on the source side of the first FET and the source side of the second FET, these common source circuits are formed. By using a high-pass configuration or band-stop filter, the ground is open at the IF frequency, while the other frequencies are open.
Can be short-circuited.

Therefore, if the IF signal is the first and second FE
The risk of flowing from the source of T to ground (ground) is reduced, and as a result, an RF signal can be output more efficiently from the RF port.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), the power combiner is preferably a Wilkinson type power combiner. The Wilkinson-type power combiner as a power combiner can accurately cancel out (cancel) signal components of opposite phases, and has a simple configuration of these circuits themselves. This is because the area itself can be made smaller.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), the first input of the LO signal is
It is preferable that an LO signal input matching circuit is provided for each of the gate of the FET and the gate of the second FET.

As described above, when the LO signal input matching circuits are provided on the gate side of the first FET and the gate side of the second FET, respectively, the LO port, the first FET, the second FET, and Impedance matching with the transmission line is achieved, and the LO signal can be more efficiently input from the LO port to the gate of the first FET and the gate of the second FET.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), the IF port
It is preferable to provide a signal input matching circuit.

As described above, when the IF signal input matching circuit is provided for the IF port, the IF port and the first FE
T, the second FET, and the impedance matching with the transmission line are achieved, respectively, and the IF signal can be more efficiently input from the IF port to the gate of the first FET and the gate of the second FET, respectively. it can.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), it is preferable to provide an IF signal input matching circuit having a low-pass configuration for the IF port.

When the low-pass IF signal input matching circuit is provided for the IF port, the high frequency L
O signal is less likely to leak to the IF port, and the gate of the first FET and the second F
A relatively low frequency IF signal can be more efficiently input to each of the ET gates.

The FET mixer circuit of the present invention (first embodiment)
3 to 3), the RF port is
It is preferable to provide a signal output matching circuit.

As described above, the RF signal output matching circuit is
If provided for the port, impedance matching between the RF port and the first and second FETs is achieved, respectively, and the RF signal from the drains of the first and second FETs is more efficiently transmitted to the RF port. Can be output.

Further, the FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), the RF signal output matching circuit provided for the RF port preferably has a high-pass configuration.

When the RF signal output matching circuit has a high-pass configuration, the RF port, the first and second FEs
The impedance matching with T is achieved, and even if a relatively low frequency IF signal is output to the RF port, the IF signal can be cut off by the RF signal output matching circuit having the high-pass configuration. . Thus, for the RF port, the first and second F
RF signals can be output more efficiently from the drains of the ETs.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), it is preferable to provide a high-frequency cutoff circuit for applying a gate bias voltage to the circuit for applying a gate bias voltage.

As described above, the RF signal based on the second harmonic synthesized by the power combiner is input to the bias voltage applying circuit by the high frequency cutoff circuit and the gate bias voltage applying circuit. Can be efficiently prevented.

The FET mixer circuit of the present invention (first embodiment)
In the third to third embodiments), it is preferable to provide a high-frequency cutoff circuit for applying the drain bias voltage to the drain bias voltage application circuit.

By providing the high-frequency cutoff circuit for the drain bias voltage application circuit as described above, the IF
It is possible to efficiently prevent the IF signal output from the port from being input to the drain bias voltage application circuit.

[0053]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to FIGS. 1 to 5, FET mixer circuits according to first to third embodiments of the present invention will be described. However, FIGS. 1 to 5 schematically show only a part of the FET mixer circuit and its constituent circuits so that the present invention can be understood. So, needless to say,
The FET mixer circuit of the present invention is not limited to these embodiments without any reason.

FIG. 1 shows an FET mixer circuit 100 according to a first embodiment of the present invention, which comprises a signal input section, an FET section, and a signal output section. The positional relationship among the signal input unit, the FET unit, and the signal output unit is roughly represented by X, Y, and Z arrows in the figure.

The signal input section X is connected to the LO port 11
0, an IF port 112, and a transmission line 106 as a delay circuit (indicated by a dotted line on the left side in the figure). Preferably, a microstrip line, a coplanar line, or another line is used as the transmission line.

The FET section Y includes a first FET (field effect transistor) 102 and a second FET 104
have. One gate bias voltage application circuit 126 is connected to each of the gates 102a and 104a in the FETs 102 and 104. One drain bias voltage application circuit 130 is connected to each of the drains 102b and 104b in the FETs 102 and 104. The sources 102c and 104c of the first and second FETs 102 and 104 are connected to the ground 1
40.

The signal output section Z is connected to the RF port 114
And a power combiner (also referred to as an in-phase divider), such as a Wilkinson type power combiner (hereinafter referred to as a power combiner) 108 (shown enclosed by a dotted line on the right side in the figure). ing.

Here, the gate 10 of the first FET 102
2a and the gate 104a of the second FET 104 are connected in parallel by a transmission line 106. Thus, a substantially intermediate position of the transmission line 106, ie,
From one end (one end) Q <b> 1 of the transmission line 106 and the other end (the other end) Q <b> 2, starting at a point B having the same electrical length (located at an equal distance), the power is synthesized via the first FET 102. Where the electrical lengths from the drain 102b of the first FET and the drain 104b of the second FET are substantially equal, ie, the RF port 1
One circuit leading to point D at the position where 14 is connected;
Similarly, from the point B of the transmission line 106, the second FET 1
Another circuit that leads to a point D in the power combiner 108 through the circuit 04 is formed.

The transmission line 106 has an LO port 110 connected to one end thereof, and an LO signal can be supplied to the LO port 110 from an oscillator (not shown). In this example, the LO port 11
Although 0 is connected to one end of the transmission line 106 on the second FET 104 side, it may be one end of the transmission line 106 on the first FET 102 side. The LO signal is a high-output but relatively low-frequency signal generated using this oscillator (not shown). However, the frequency of the LO signal used in the FET mixer circuit 100 of the present invention corresponds to a quasi-millimeter wave (less than 30 GHz).
For example, those in the range of 20 to 30 GHz are preferable,
Corresponding to millimeter wave (30 GHz or more), for example, 35 GHz
In some cases, an LO signal having a frequency of about z is used.

The L input from the LO port 110
The O signal is input, on the one hand, to the gate 102a of the first FET 102 via the transmission line 106 and, on the other hand, to the gate 104a of the second FET 104,
The input is made without passing through the transmission line 106. That is, the LO signal is substantially equally divided into two, and the individual FET 10
2 and 104.

The LO signal input to the gate 102a of the first FET 102 is called a first LO signal for convenience, and similarly, the LO signal input to the gate 104a of the second FET 104. The signal is conveniently referred to as the second
LO signal. Hereinafter, the same applies.

The L input from the LO port 110
The O signal is substantially equally divided into two, and is divided into a first LO signal and a second LO signal as a gate 102a of the first FET 102 and a gate 104 of the second FET 104.
a so as to be stably input to each of the first FETs
102 (in this case, including the transmission line 106);
It is preferable that impedance matching with the second FET 104 is achieved. In this example, an LO signal input matching circuit 116 is provided between one end (one end) Q1 of the transmission line 106 and the gate 102a of the first FET in order to achieve the impedance matching. The LO signal input matching circuit 118 is connected to the other end (one end) Q2 of the transmission line 106,
LO port 110 and gate 10 of second FET 104
4a.

The transmission line 106 has an electrical length substantially corresponding to a half wavelength at the frequency of the LO signal input from the LO port 110. Specifically, assuming that the frequency of the LO signal is f _LO , the transmission line 106 has an electrical length equal to an effective wavelength (λ) corresponding to half the frequency (f _LO / 2). Therefore, the first LO signal among the LO signals input from the LO port 110 requires time to pass through the transmission line 106, unlike the second LO signal.

Therefore, the first LO signal is supplied to the first F
Comparing the time inputted to the gate 102a of the ET 102 with the time inputted to the gate 104a of the second FET 104 without passing through the transmission line 106, the first LO signal is substantially Is delayed by a time corresponding to 波長 wavelength. This is because the waveform of the first LO signal at the gate 102a of the first FET 102 and the second waveform of the gate 104a of the second FET 104
The waveform of the LO signal means that there is a so-called reverse phase relationship.

This point will be described in more detail with reference to FIG. The horizontal axis represents time (relative value), and the vertical axis represents amplitude (relative value). And the first FE
First LO when input to gate 102a of T102
The waveform of the signal is indicated by a dotted line, and similarly, the waveform of the second LO signal when input to the gate 104a of the second FET 104 is indicated by a solid line. The dotted line representing the waveform of the first LO signal and the solid line representing the waveform of the second LO signal have a line-symmetric relationship along the time axis, and these waveforms have an antiphase relationship as described above. You can see that there is.

In the figure, the symbol T indicates the transmission line 106
, The time corresponding to the difference between the wavelength of the first LO signal and the wavelength of the second LO signal.

Therefore, as will be described later, even if the first LO signal and the second LO signal having the opposite phase relationship are input to the Wilkinson type power combiner 108 as the power combiner, they are canceled out. To fit (cancel),
The LO signal itself does not output to the RF port.

Here, a Wilkinson type power combiner as a power combiner will be briefly described with reference to FIG. The Wilkinson power combiner 400 has a first
イ ン ピ ー ダ ン ス wavelength impedance transformer 402 of the electrical length θ
, A resistor 404, and a イ ン ピ ー ダ ン ス wavelength impedance transformer 406 having a second electrical length θ.
Two impedance transformers 4 of this power combiner 400
02 and 406 are coupled to the RF port 114 at the output and coupled to the impedance transformer 402,
The connection point with the resistor 404 is coupled to the drain 102b, and the impedance transformer 406 and the resistor 404
Is connected to the drain 104b.

The drain 102 of the first FET 102
The impedance at b is Z _L1 and the second FET 1
04 at the drain 104b, Z _L2
The impedance of the quarter-wave impedance transformer 402 of the first electrical length θ is Z _1, and the second electrical length θ
Assuming that the impedance of the 波長 wavelength impedance transformer 406 is Z ₂ , the combined characteristic impedance Z ₀ has the following relationship.

Z ₁ = (2Z ₀ ) ^3/4 Z _L1 ^1/4 (1) Z ₂ = (2Z ₀ ) ^3/4 Z _L2 ^1/4 (2) Next, returning to FIG. The input of the IF signal (intermediate frequency signal) to be mixed to the FET mixer circuit 100 will be described. The IF signal oscillated by the IF signal generator (not shown) generally has a considerably lower frequency than the LO signal, and has a frequency of about 1 to 5 GHz, for example.

Therefore, in the example of the FET mixer circuit 100, a low-pass IF signal input matching circuit 120 is provided between the IF port 112 and the transmission line 106. The IF signal that has passed through the IF signal input matching circuit 120 has the same electrical length from one end Q1 of the transmission line 106 to the other end Q2 (indicated by the symbol B in FIG. 1). Is input to

Therefore, when an IF signal generated by an IF signal generator (not shown) is input to the IF port 112, the IF signal input matching circuit 120 having such a low-pass configuration.
Through the transmission line 106. Then, the IF signal input matching circuit 120 having a low-pass configuration
Port 112, first FET 102, second FET 1
04 and the transmission line 106, impedance matching is achieved, and the harmonic component of the frequency of the IF signal is cut off. In this example, the signal is controlled to a desired frequency component in a range of about 1 to 5 GHz, for example. You. Further, the IF signal input matching circuit 120
Of the LO signals input from the LO port 110, the first LO signal that should be input to the first FET 102 is I
Leakage (leakage) to the F port 112 is prevented.

Therefore, the input IF signal is substantially equally divided into two, and the first IF signal and the second I
The F signal is input to the gate 102a of the first FET 102 and the gate 104a of the second FET 104, respectively. Then, from the point B where the IF signal is input,
The gate 102a of the first FET 102 and the second FE
Since the electrical lengths of the T104 up to the gate 104a are substantially equal to each other, as described later, such an IF signal and
The second harmonic of the LO signal can be efficiently mixed.

Next, the first FET 102 and the second F
The mixing of the second harmonic of the LO signal and the above-described IF signal in the ET 104 will be described. That is, in the case of an up-converter, the frequency of the LO signal and the I
An RF signal having a frequency equal to the sum of the frequency of the F signal is generated.

Therefore, in the first FET 102,
The first LO signal and the first IF signal are mixed to generate a first RF signal. Similarly, the second FET
At 104, the second LO signal and the second IF signal are mixed to generate a second RF signal.

In the power combiner 108, high-frequency components having opposite phases are canceled (canceled), and only high-frequency components having the same phase can be combined. Therefore, in the FET mixer circuit 100, the connection point D in the power combiner 108 shown in FIG. 1 becomes a virtual short-circuit point with respect to the fundamental wave of the LO signal.
That is, when the fundamental wave of the LO signal is input to the power combiner from the drain of the first FET and the drain of the second FET, respectively, the fundamental wave of the LO signal has passed through the transmission line, and the other has not. Since the phases are in opposite phases, they can be canceled out in terms of phase.

In the example of the FET mixer circuit 100, the connection point D is connected from this point D to the power combiner 108.
Up to one end (one end) Q3 and the other end (other end)
This is a position where the electric lengths up to Q4 are substantially equal, and as described above, the electric lengths are substantially equal from the drain 102b of the first FET 102 and the drain 104b of the second FET 104. is there.

On the other hand, the first FET 102 and the second
In the FET 104 of FIG.
When a high frequency such as a LO signal is input to the ETs 102 and 104, the reflection coefficient on the input (gate) side of the LO signal is caused by the input of the LO signal due to the nonlinear characteristics of the FETs 102 and 104. It is known that a second harmonic that is modulated and has twice the wavelength of the fundamental in the LO signal is generated.

Specifically, when two frequency components ω1 and ω2 are input to the nonlinear semiconductor element, the following equation (3) is obtained.
It is known that the second harmonic (ω _1,1 ) of the frequency according to the above is generated.

Ω _{m, n} = | mω1 + nω2 | (m, n = 0, ± 1, ± 2...) (3) Then, in these FETs 102 and 104,
The gate bias voltage and the drain bias voltage are adjusted so that the reflection coefficient on the input (gate) side of the LO signal is easily modulated. That is, these FETs 10
These bias voltages are adjusted so that the operating points 2 and 104 are located in the respective saturation regions.

Note that the saturation region of the FET is the V
_{In the DS- ID} characteristic, a certain range of the drain-source voltage when the drain current value _ID is hardly changed (flat) even when the value of the drain-source voltage _VDS is increased is set. Say.

Therefore, in the first FET 102 and the second FET 104 of the FET mixer circuit (first embodiment) 100 of this example, the first
, And similarly, a second second harmonic from the second LO signal.

Therefore, in the first FET 102,
The first second harmonic and the first IF signal form a second FE
At T104, the second second harmonic and the second IF
The signals are respectively mixed to generate first and second RF signals based on the second harmonic.

However, as described above, since the IF signal is divided into two sidebands, the frequency of the LO signal is set to LO,
If the frequency of the F signal is IF, the frequencies of the first and second RF signals based on the second harmonic are 2LO ± IF
Becomes

Since the first second harmonic and the second second harmonic each have twice the wavelength of the fundamental wave in the LO signal, the first second harmonic and the second The waveform of the harmonic and the waveform of the second second harmonic are completely matched and in phase.

Accordingly, the first and second RF signals based on these second harmonics are efficiently combined in the power combiner 108, respectively, and are converted into RF signals based on the second harmonics. It can be extracted from the RF port 114 provided at the connection point D in the synthesizer 108.

As described above, in the example of the FET mixer circuit 100, the connection point D substantially corresponds to an intermediate position of the electric length from one end Q3 of the power combiner 108 to the other end Q4. RF port 114
From the drain 102b of the first FET 102 and the second
The electrical lengths up to the drain 104b of the FET 104 become equal to each other, and there is no risk that the phases of the first and second RF signals based on the second harmonic will be shifted before being input to the RF port 114.

When the RF signal is extracted using the power combiner 108, the drain 102b of the first FET 102 and the drain 102b of the second FET 104
4b, the transmission line to the RF port 114 need not be separately provided.

In addition, in the example of the FET mixer circuit (first embodiment) 100 of the present invention, the LO signal input matching circuit 1 provided on the gate 102a side of the first FET 102
A high frequency cutoff circuit (for applying a gate bias voltage) 124 and a capacitor 138 are sequentially connected to a connection point C between the transmission line 106 and the transmission line 106, and the other end of the capacitor 138 is connected to the ground 140. It is.

Therefore, this high-frequency cutoff circuit 124
Performs a function as a choke inductance, and the first second harmonic generated by the first FET 102 and the second second harmonic generated by the second FET 104
Each is prevented from leaking to the gate bias voltage application circuit 126.

The gate bias voltage application circuit 126 is connected to the connection point C via the high frequency cutoff circuit 124.
A predetermined gate bias voltage, which is direct current (DC), is applied to the gate 102a of the first FET 102 and the gate 104a of the second FET 104,
The second harmonic in the O signal is easily generated. That is, these FETs 102 and 104 are operated in the saturation region of these FETs 102 and 104, respectively.

In this example, the gate 102a of the first FET 102 and the gate 104a of the second
Although a gate bias voltage is applied to a, two gate bias voltage applying circuits are provided if necessary, and a gate bias voltage is applied to the gate 102a of the first FET 102 and the gate 104a of the second FET 104, respectively. It is also possible to apply a gate bias voltage from another gate bias voltage application circuit.

The FET mixer circuit of the present invention (first embodiment)
Embodiment) In the example of 100, the RF signal output matching circuit 1
A high-frequency cutoff circuit (for applying a drain bias voltage) 128 and a capacitor 138 are connected to a connection point E between the node 22 and the connection point D, and the other end of the capacitor 138 is connected to the ground 140. It is. Therefore, the high-frequency cutoff circuit 128 functions as a choke inductance, and the RF signal based on the second harmonic synthesized by the power combiner 108 leaks to the drain bias voltage application circuit 130. Is prevented.

In this example, the drain bias voltage is applied to the drain 102b of the first FET 102 and the drain 104b of the second FET 104 by one drain bias voltage application circuit 130. If so, two drain bias voltage applying circuits are provided, and the drain 102b of the first FET 102 is provided.
And the drain 104b of the second FET 104
It is also possible to apply a drain bias voltage from separate drain bias voltage applying circuits.

The drain bias voltage application circuit 130 is connected to a connection point E via a high-frequency cutoff circuit (drain bias voltage application) 128 and has a predetermined bias voltage of direct current (DC). Is the first FET
The voltage is applied to the drain 102b of the second FET 102 and the drain 104b of the second FET 104, respectively, so that the second harmonic in the LO signal is easily generated together with the gate bias voltage application circuit 126 described above. That is, these FETs 102 and 104 are operated in the saturation region of these FETs 102 and 104.

Next, the FET according to the second embodiment of the present invention will be described.
The mixer circuit will be described. That is, FIG. 2 shows an FET mixer circuit 200 according to the second embodiment of the present invention. In the description of the FET mixer circuit 200 of the second embodiment, components common to the FET mixer circuit 100 of the first embodiment will be omitted as appropriate, and different components will be mainly described. In the FET mixer circuit 200 according to the second embodiment, the same components as those in the FET mixer circuit 100 according to the first embodiment are denoted by the same reference numerals.

The FET mixer circuit 200 according to the second embodiment includes the LO port 110 and the transmission line 1.
06 and the like, and a first FET
(Field Effect Transistor) 102 and Second FET
FET unit Y composed of an RF port
Output section Z composed of a power combiner 108 and the like
The basic configuration is the same as that of the FET mixer circuit 100 of the first embodiment.

Therefore, similarly to the FET mixer circuit 100 of the first embodiment, in the FET mixer circuit 200 of the second embodiment, the gate 1 of the first FET 102
02a and the gate 104a of the second FET 104
They are connected in parallel by a transmission line 106.

At one end of the transmission line 106, an LO port 110 is provided.
10 is a high power but relatively low frequency generated by an oscillator (not shown), for example 20-30 GH
z LO signal to the gate 102a of the first FET 102
In this case, the data can be input to the gate of the second FET 104 through the wiring via the transmission line 106 and the gate 104a of the second FET 104 can be divided into two substantially equally through the wiring.

Further, similarly to the FET mixer circuit 100 of the first embodiment, in the FET mixer circuit 200 of the second embodiment, the LO signal is substantially equally divided into two and the first As the LO signal and the second LO signal,
The gate 102a of the first FET 102 and the second FE
The first FET 102 (in this case,
It includes a transmission line 106 and the like. ) And the second FET 104
And impedance matching is achieved. Therefore, the LO signal input matching circuits 116 and 118 are connected to the gate 102a of the first FET 102 and the second
Is provided immediately before the gate 104a of the FET 104.

Also in this case, the transmission line 106 has an electrical length substantially corresponding to a half wavelength with respect to the frequency of the LO signal input from the LO port 110. Therefore, F of the first embodiment has already been set.
For the reason described in the description of the ET mixer circuit 100, the second
Of the second LO input to the gate 104a of the FET 104 of FIG.
The first LO signal is compared to the first FET 10
The signal is input to the second gate 102a with a delay substantially by 波長 wavelength. For this reason, the first LO signal and the second LO signal have an anti-phase relationship with each other.

Therefore, using the first LO signal based on the fundamental wave of these LO signals and the second LO signal, the first FET 102 and the second FET 104
Even if the F signal (intermediate frequency signal) is mixed, the LO signal itself is not output to the RF port because the power combiner 108 cancels out each other (cancellation).
4 cannot be taken out. That is, the connection point D in the power combiner 108 shown in FIG. 2 is a virtual short-circuit point with respect to the fundamental wave of the LO signal.

However, the FE of the second embodiment
Also in the first FET 102 and the second FET 104 of the T mixer circuit 200, similarly to the FET mixer circuit 100 of the first embodiment, these first and second FEs are used.
When a high-frequency component such as an LO signal is input to T102 and 104, the reflection coefficient on the input (gate) side of the LO signal is modulated by the input of the LO signal due to the nonlinear characteristics of the FETs 102 and 104. As a result, first and second second harmonics, each having a wavelength twice the fundamental wave in the LO signal, are generated. Therefore, also in the FET mixer circuit 200 of the second embodiment, the first second harmonic and the second
Of the second harmonic can be used.

Here, in the FET mixer circuit 200 of the second embodiment, an IF signal (intermediate frequency signal)
The method of input to the FET mixer circuit of the first embodiment is greatly different from that of the FET mixer circuit 100 of the first embodiment. That is, in the FET mixer circuit 100 of the first embodiment, instead of connecting the IF port 112 to the transmission line 106 to input an IF signal, the FET mixer circuit 200 of the second embodiment First FE
T102 drain 102b and second FET 104
Signal input matching circuit 2
An IF port 212 is provided through the interface 20 to input an IF signal.

The drain 1 of the first FET 102
02b and the drain 104b of the second FET 104
And the power combiner 108 between the connection points F and H, respectively.
And an IF signal is inputted from a connection point G which is a substantially intermediate position of the wiring between the connection points F and H.

Note that the configuration itself of the IF port 212 for inputting an IF signal and the IF signal input matching circuit 220 is basically the same as that of the FET mixer circuit 10 of the first embodiment.
Since the configuration is the same as the configuration of the IF port 112 and the IF signal input matching circuit 120 at 0, the description is omitted here.

Then, the data is input from the IF port 212,
The IF signal that has passed through the IF signal input matching circuit 220 is exactly divided into two at the connection point G, and the first IF signal and the second
Of the drain 102b of the first FET 102 and the drain 1 of the second FET 104, respectively.
04b. Therefore, the first and second IF signals and the first and second LO signals based on the second harmonic described above are efficiently mixed in the first FET 102 and the second FET 104, respectively. Thus, the first and second RF signals based on the second harmonic can be generated.

That is, also in the FET mixer circuit 200 of the second embodiment, the first and second RF signals based on the second harmonic are efficiently combined in the power combiner 108, respectively. RF based on second harmonic
The signal can be extracted from the RF port 114 provided at the connection point D of the power combiner 108.

In the FET mixer circuit 200 according to the second embodiment, the IF port 212 is connected to the drain side 102 of the first and second FETs 102 and 104.
b, 104b, the IF signal
There is no risk of leaking to port 110. Therefore, the IF signal can be used more effectively,
The signal and the second harmonic of the LO signal can be more efficiently mixed.

In addition, in the FET mixer circuit 200 according to the second embodiment, for the same reason as already described in the description of the FET mixer circuit 100 according to the first embodiment, the FET mixer circuit 200 is connected to the gate 102a side of the first FET 102. LO provided
At a connection point C between the signal input matching circuit 116 and the transmission line 106, a high frequency cutoff circuit 124, a capacitor 1
38, a ground 140 and a circuit 126 for applying a gate bias voltage are connected. A connection point E between the RF signal output matching circuit 122 and the connection point D of the power combiner 108 is Circuit 128, capacitor 1
38, a ground 140 and a circuit 130 for applying a drain bias voltage are connected.

Next, an FET according to a third embodiment of the present invention will be described.
The mixer circuit will be described. That is, FIG. 3 shows an FET mixer circuit 300 according to the third embodiment of the present invention. The FET mixer circuit 3 of the third embodiment
00, the FET mixer circuit 100 of the first embodiment and the FET mixer circuit 20 of the second embodiment
Components common to those of 0 are omitted as appropriate, and components different from these components will be mainly described. Further, in the FET mixer circuit 300 of the third embodiment, the same reference numerals are given to configurations common to the FET mixer circuit 100 of the first embodiment or the FET mixer circuit 200 of the second embodiment. .

The FET mixer circuit 300 according to the third embodiment includes the LO port 110 and the transmission line 1.
06, etc., and a first FET 1
02 and a second FET 104, and a signal output unit Z including an RF port 114 and a power combiner 108. The basic configuration is the same as that of the first embodiment. FET of the second embodiment
This is the same as the mixer circuits 100 and 200.

Therefore, the FET of the third embodiment
Also in the mixer circuit 300, the gate 102a of the first FET 102 and the gate 104a of the second FET 104
Are connected in parallel by the transmission line 106. An LO port 110 is provided at one end of the transmission line 106. From the LO port 110,
A high power but relatively low frequency LO signal generated using an oscillator (not shown) is
The gate 102a of the second FET 104 is connected to the gate 102a of the second
Can be directly divided into two and input directly through wiring.

For the same reason as described in the description of the FET mixer circuit 100 of the first embodiment, the FET mixer circuit 300 of the third embodiment also has a low level.
O signal input matching circuits 116 and 118
The gate 102a of the first FET 102 and the second FE
It is provided immediately before the gate 104a of T104.

Also in this case, the transmission line 106 has an electrical length substantially equivalent to a half wavelength of the frequency of the LO signal input from the LO port 110. Therefore, for the reason already described in the description of the FET mixer circuit 100 of the first embodiment, the second FET 10
4 is input to the gate 1 of the first FET 102 in comparison with the second LO signal input to the gate 104a of the first FET 102.
02a is delayed substantially by 波長 wavelength. Therefore, the first LO signal and the second LO signal have an anti-phase relationship with each other.

Therefore, the first FET 102 and the second FET 104 use the first LO signal based on the fundamental wave of these LO signals and the second LO signal to generate
Even if the F signal (intermediate frequency signal) is mixed, it is canceled (canceled) in the power combiner 108,
The LO signal itself does not output to the RF port,
The combined signal cannot be extracted from the RF port 114 as an RF signal. That is, the power combiner 1 shown in FIG.
The connection point D at 08 becomes a virtual short-circuit point for the fundamental wave of the LO signal.

On the other hand, F in the third embodiment
First FET 102 and second FET 102 of ET mixer circuit 300
In the FET 104 of the first embodiment, similarly to the FET mixer circuit 100 of the first embodiment, the first and second F
When a high frequency such as a LO signal is input to the ETs 102 and 104, the reflection coefficient on the input (gate) side of the LO signal is modulated by the input of the LO signal due to the non-linear characteristics of the FETs 102 and 104. , The second harmonic having a wavelength twice the fundamental wave in the LO signal (first and second second harmonics)
Occurs at 02 and 104.

Therefore, the FET of the third embodiment
Also in the mixer circuit 300, the source 102c of the first FET and the second FET are used by using the first second harmonic and the second second harmonic having the same in-phase relationship.
Can be mixed with the IF signal input to the source 104c.

Here, in the FET mixer circuit 300 of the third embodiment, an IF signal (intermediate frequency signal)
The method of input to the FET mixer circuit of the first embodiment is the same as that of the FET mixer circuit 100 of the first embodiment and the FE of the second embodiment.
This is significantly different from the T mixer circuit 200. That is, in the FET mixer circuit 100 of the first embodiment, the gate 102a of the first FET 102 and the second FET
In the FET mixer circuit 200 according to the second embodiment, a drain 102b of the first FET 102 is provided.
And an IF signal is input to the drain 104b of the second FET 104. In the FET mixer circuit 300 of the third embodiment, the first FET 10
An IF signal is input to the second source 102c and the source 104c of the second FET 104, respectively.

That is, the source 1 of the first FET 102
02c and the source 104c of the second FET 104, the IF signal input matching circuit 322 and the IF port 3
14 are connected in this order. In this example, the IF
One signal input matching circuit 322 and one IF port 314 are provided, and the first FET
An IF signal can be input to each of the source 102c of 102 and the source 104c of the second FET 104.

Then, the source 102c of the first FET 102 and the second FET 10
The electrical lengths up to the fourth source 104c are substantially equal. Therefore, I input from IF port 314
After the F signal passes through the IF signal input matching circuit 322,
The signal is divided into two equal parts at the connection point I, and the first IF signal and the second IF signal are used as the source 1 of the first FET 102, respectively.
02c and the source 104c of the second FET 104. Therefore, the first and second IF signals and the first and second LO signals based on the second harmonic described above are respectively converted into the first FET 102 and the second
, The first and second RF signals based on the second harmonic can be generated.

On the other hand, the source 102 of the first FET 102
c and the source 104c of the second FET 104 and the junctions J and K are further provided in the middle of the branch point I, respectively.
10, 320, a capacitor 138 and a ground (ground) 140 are provided.

Therefore, the first FET 10
When the grounded source circuits 310 and 320 are provided for the source 102c of the second FET 104 and the source 104c of the second FET 104, respectively, and the FET mixer circuit 300 is formed, these grounded source circuits 310 and 320 are formed in a high-pass configuration or a band rejection filter ( With this configuration, the signal can be opened (the IF signal does not leak) at the frequency of the IF signal, and the signal having that frequency can be short-circuited to the ground 140 for the other frequencies. Therefore, if the IF signal is the first and second FETs
Is less likely to flow into the ground 140 without being input to the sources 102c and 104c of the
An RF signal can be output from the RF port 114 more efficiently.

That is, as described above, also in the FET mixer circuit 300 of the third embodiment, the first and second RF signals based on the second harmonic are converted into the power combiner 1
At 08, the respective signals can be efficiently combined and extracted as an RF signal based on the second harmonic from the RF port 114 provided at the connection point D of the power combiner 108.

Further, in the FET mixer circuit 300 according to the third embodiment, the LO port 110 is connected to the gates 102a of the first and second FETs 102 and 104,
104a, the IF port 212 is connected to the source 10 of the first and second FETs 102 and 104.
2c, 104c, and the RF port 114
Is provided for the drains 102b and 104b of the first and second FETs 102 and 104. Therefore, since each port is separated by the FET, the LO
There is no possibility that the signal, the IF signal, and the RF signal are leaked. That is, an IF signal,
The second harmonic of the LO signal can be more efficiently mixed.

Further, in the configuration of the FET mixer circuit 300 of the third embodiment, the LO port 110,
IF port 314 and RF port 114 are respectively connected to gate 102a, 104a and source 102c, of first and second FETs 102 and 104, respectively.
Since the circuit is assigned to the drain 104c and the drains 102b and 104b, the degree of freedom in circuit design also increases dramatically.

In addition, in the FET mixer circuit 300 according to the third embodiment, for the same reason as already described in the description of the FET mixer circuit 100 according to the first embodiment, the FET mixer circuit 300 is connected to the gate 102a side of the first FET 102. LO provided
At a connection point C between the signal input matching circuit 116 and the transmission line 106, one high-frequency cutoff circuit 124, a capacitor 138, a ground 140, and a gate bias voltage application circuit 126 are connected. For a connection point E between the signal output matching circuit 122 and a connection point D of the power combiner 108, one high-frequency cutoff circuit 128,
The capacitor 138, the ground 140, and the drain bias voltage application circuit 130 are connected.

In the above configuration example, a transmission line is used as a delay circuit, but instead of this transmission line,
Even if a 180 ° hybrid is used, the FET mixer circuit of the present invention can be configured.

[0129]

The FET according to the first to third embodiments of the present invention
According to the (field-effect transistor) mixer circuit, the first
The gate of the FET and the gate of the second FET are connected in parallel using a transmission line as a delay circuit, etc., so that a high-output but relatively low-frequency LO signal is used to generate a high output. And a high frequency RF signal
You can now take it out of the port.

Therefore, according to the FET mixer circuits of the first to third embodiments, even if the output is a high-frequency but low-frequency LO signal, the frequency doubler is oscillated using a general millimeter-wave oscillator. Can be mixed with the IF signal without providing the
It has become possible to provide a small area FET mixer circuit.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an FET mixer circuit (first embodiment) of the present invention.

FIG. 2 is a diagram for explaining an FET mixer circuit (second embodiment) of the present invention.

FIG. 3 is a diagram for explaining an FET mixer circuit (third embodiment) of the present invention.

FIG. 4 is a diagram for explaining an LO signal in the FET mixer circuit of the present invention.

FIG. 5 is a diagram for explaining a Wilkinson power combiner.

FIG. 6 is a diagram for explaining a conventional FET mixer circuit.

[Explanation of symbols]

10, 100, 200, 300: FET mixer circuit 12, 102, 104: FET (field effect transistor) 12a, 102a, 104a: Gate 12b, 102b, 104b: Drain 12c, 102c, 104c: Source 14, 116 , 118: LO signal input matching circuit 16, 122: RF signal output matching circuit 18, 120, 220, 322: IF signal input matching circuit 20, 124: High frequency cutoff circuit (for applying gate bias voltage) 22, 126: Gate Bias voltage application circuit 26: RF blocking filter 28, 128: High frequency cutoff circuit (for drain bias voltage application) 30, 130: Drain bias voltage application circuit 32, 110: LO port 34, 112, 212, 314: IF Ports 36 and 114: RF ports 38a and 38 b, 38c, 138: Capacitors 40, 140: Ground 106: Transmission line 108: Power combiner (Wilkinson type power combiner) 310, 320: Common source circuit 400: Wilkinson type power combiner 402, 406: 1/4 wavelength Impedance transformer 404: resistance

Claims (28)

[Claims] 1. A mixer circuit using an FET (field effect transistor), comprising: a first FET whose source is grounded; and a second FET whose source is grounded, wherein the gate of the first FET has one end. And a transmission line having the gate of the second FET connected to the other end, the transmission line having an LO port connected to one end, and the transmission line being connected to the LO port. Has an electrical length substantially corresponding to a half wavelength with respect to the frequency of the LO signal input from A gate bias voltage applying circuit is connected to the gate of the first FET and the gate of the second FET; With respect to the drain of the first drain and the second FET of the FET, the drain bias voltage application circuit Yes to connect, further, the drain of said first FET, said second FET
Is connected using a power combiner, and an RF port is provided at a position where the electrical length is substantially equal from the drain of the first FET and the drain of the second FET in the power combiner. An FET mixer circuit, which is connected. 2. The FET mixer circuit according to claim 1, wherein said power combiner is a Wilkinson type power combiner. 3. The FET mixer circuit according to claim 1, wherein said first FET receives a LO signal.
And an LO signal input matching circuit provided on the gate side of the second FET and on the gate side of the second FET, respectively. 4. The F according to claim 1, wherein
In the ET mixer circuit, for the IF port, I
FE characterized by having an F signal input matching circuit
T mixer circuit. 5. The FET mixer circuit according to claim 4, wherein said IF signal input matching circuit has a low-pass configuration. 6. The F according to claim 1, wherein
In the ET mixer circuit, R
FE characterized by having an F signal output matching circuit
T mixer circuit. 7. The FET mixer circuit according to claim 6, wherein said RF signal output matching circuit has a high-pass configuration. 8. The F according to claim 1, wherein
In the ET mixer circuit, a high frequency cutoff circuit is provided for the gate bias voltage application circuit. 9. The F according to claim 1, wherein
In the ET mixer circuit, a high-frequency cutoff circuit is provided for the drain bias voltage application circuit. 10. A mixer circuit using an FET, comprising: a first FET whose source is grounded; and a second FET whose source is grounded, wherein the gate of the first FET is connected to one end, and A transmission line having a gate connected to the other end of the second FET, the transmission line having an LO port connected to one end, and the transmission line being input from the LO port; For the frequency of the LO signal, substantially 1
And a gate bias voltage application circuit is connected to the gate of the first FET and the gate of the second FET, and An IF port and a drain bias voltage application circuit are connected to the drain of the FET and the drain of the second FET, and the drain of the first FET and the drain of the second FET are connected from the IF port. The electrical lengths to the drain are substantially equal; and the drain of the first FET and the second F
The RF port is connected to the drain of the ET using a power combiner and at a position in the power combiner where the electrical lengths are substantially equal from the drain of the first FET and the drain of the second FET. A FET mixer circuit characterized in that: 11. The FET mixer circuit according to claim 10, wherein said power combiner is a Wilkinson-type power combiner. 12. The FET according to claim 10, wherein:
In the mixer circuit, an LO signal input matching circuit is provided on each of the gate side of the first FET to which the LO signal is input and the gate side of the second FET. 13. The FET mixer circuit according to claim 10, wherein an IF signal input matching circuit is provided for the IF port. 14. The FET mixer circuit according to claim 13, wherein the IF signal input matching circuit has a low-pass configuration. 15. The FET mixer circuit according to claim 10, wherein an RF signal output matching circuit is provided for the RF port. 16. The FET mixer circuit according to claim 15, wherein said RF signal output matching circuit has a high-pass configuration. 17. The FET mixer circuit according to claim 10, wherein a high-frequency cutoff circuit is provided for the gate bias voltage application circuit. . 18. The FET mixer circuit according to claim 10, wherein a high-frequency cutoff circuit is provided for the drain bias voltage application circuit. . 19. A mixer circuit using an FET, comprising: a first FET whose source is grounded; and a second FET whose source is grounded, wherein the gate of the first FET is connected to one end, and A transmission line having a gate connected to the other end of the second FET, the transmission line having an LO port connected to one end, and the transmission line being input from the LO port; For the frequency of the LO signal, substantially 1
And a gate bias voltage application circuit is connected to the gate of the first FET and the gate of the second FET, and A drain bias voltage application circuit is connected to a drain of the FET and a drain of the second FET, and an IF port is connected to a source of the first FET and a source of the second FET. The source of the first FET and the second FE from the IF port.
The electrical length of the T to the source is substantially equal; and the drain of the first FET and the second F
The RF port is connected to the drain of the ET by using a power combiner, and at a position in the power combiner where the electrical length is substantially equal from the drain of the first FET and the drain of the second FET. A FET mixer circuit characterized in that: 20. The FET mixer circuit according to claim 19, wherein a source ground circuit is provided for each of the source of the first FET and the source of the second FET. FET mixer circuit characterized by the above-mentioned. 21. An FET according to claim 19 or 20.
In the mixer circuit, the power combiner is a Wilkinson type power combiner. 22. The FET mixer circuit according to claim 19, wherein an LO signal is input to a gate side of the first FET and a gate side of the second FET, respectively. An FET mixer circuit provided with a signal input matching circuit. 23. The FET mixer circuit according to claim 19, wherein an IF signal input matching circuit is provided for the IF port. 24. The FET mixer circuit according to claim 23, wherein said IF signal input matching circuit has a low-pass configuration. 25. The FET mixer circuit according to claim 19, wherein an RF signal output matching circuit is provided for the RF port. 26. The FET mixer circuit according to claim 25, wherein said RF signal output matching circuit has a high-pass configuration. 27. The FET mixer circuit according to claim 19, wherein a high-frequency cutoff circuit is provided for the gate bias voltage application circuit. . 28. The FET mixer circuit according to claim 19, wherein a high-frequency cutoff circuit is provided for the drain bias voltage application circuit. .