JPH11121614A - Multilayer connecting method and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce variations of resistance values and realize connection in low resistance, by a method wherein a via hole is formed by providing a specified restriction to a wiring and a vertical directions. SOLUTION: A multilayer connection is made between an input and output cell 1 and a pad 2 by using two wiring layers S1, S2, and in a portion where the input and output cell 1 is overlaid on the pad 2, a via hole V is formed in an insulation film Z separating the wiring layer S1 from the wiring layer S2 and the wiring layer S1 is coupled to the wiring layer S2, and also each of wiring layers S1, S2 is brought into contact with the input and output cell 1 and the pad 2. The via hole V is formed on a straight line so as to be in parallel to a wiring direction and have an interval of 3 μm or more with respect to each other between the input and output cell 1 and the pad 2, so that the wiring layer S1 is coupled to the wiring layer S2. Accordingly, according to a multilayer connecting method, a connection between arbitrary two points by using a plurality of wiring layers can be made with variations of resistance values being reduced and low resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer connection method for connecting two points using a plurality of wiring layers, which is employed, for example, when connecting an input / output cell and a pad in a semiconductor integrated circuit. Things.

[0002]

2. Description of the Related Art Conventionally, when a wiring width cannot be made sufficiently large due to a space problem such as a case where an input / output cell is connected to a pad in a semiconductor integrated circuit, in order to secure a current capacity, A method of connecting two points by using a plurality of stacked wiring layers is adopted.

[0003] A conventional multi-layer connection method will be described by taking as an example the case of connection using two wiring layers. In a conventional multi-layer connection, a plan view seen from above in FIG.
3 (b) shows a cross-sectional view taken along the line BB 'in FIG. 3 (a). As shown in FIG. 3 (b), only the portion overlapping the input / output cell 1 and the pad 2 has the wiring layer S1 and the wiring layer S2. By forming via holes V in the insulating film Z between the wiring layers, the wiring layers S1 and S2 are respectively brought into contact with the input / output cells 1 and the pads 2, and the wiring layers S1 and S2 are coupled.

[0004] In addition, FIG. 4A shows a plan view as viewed from above, and FIG. 4B shows a C-line in FIG.
As shown in the sectional views at C ′, the input / output cell 1
As many via holes V as possible are formed in the insulating film Z between the input / output cell 1 and the pad 2 as much as possible without limitation, in addition to the portion overlapping with the pad 2 and the pad 2, and the wiring layer S1 and the wiring layer S2 are tightly coupled. I was letting it.

[0005]

Here, the via hole V
The wiring layer S1 and the wiring layer S2 are connected to each other via a line. FIG. 5 schematically shows an example of the connection state. In this example, a conductive material M2 (usually, this conductive material M2) forming the upper wiring layer S2 is formed in the via hole V.
Is different from the conductive material M1 forming the lower wiring layer S1), and the filling state, particularly, the thickness T1 of the connection portion with the conductive material M1 forming the lower wiring layer S1 is manufactured. It is not always possible to control this from the viewpoint of the process, and the resistance value in the via hole V varies. Further, since the thickness T1 is smaller than the thickness T2 of the wiring layer S2 in a flat portion other than the via hole V, the wiring thickness of the wiring layer S2 in the via hole V is reduced. That is, although the wiring layer S1 and the wiring layer S2 are connected via the via hole V, they are not effectively connected as if both wiring layers were short-circuited.
It is only a weak connection (coupled through a resistor having a relatively large resistance value).

From the above, the conventional multilayer connection method shown in FIGS. 3 and 4 has the following problems.
First, in the multilayer connection method shown in FIG. 3, since the via hole V is formed only in the portion overlapping the input / output cell 1 and the pad 2, the wiring layer S1 and the wiring layer S2 are connected only at two places. However, the resistance between the wiring layer S1 and the wiring layer S2 is high. As a result, the resistance value between the wiring connecting the input / output cell 1 and the pad 2 increases, and the via hole V
The variation becomes large depending on the resistance value in the above.

On the other hand, in the multilayer connection method shown in FIG. 4, since the wiring layer S1 and the wiring layer S2 are closely coupled, the resistance value between the wiring layer S1 and the wiring layer S2 becomes low. As a result, the resistance of the via hole V is less affected by the resistance value, and the variation in the resistance value between the wiring connecting the input / output cell 1 and the pad 2 can be suppressed. However,
Since the close coupling between the wiring layer S1 and the wiring layer S2 is realized by forming as many via holes V as possible without limitation, the portion of the wiring layer S2 where the thickness of the wiring becomes thin becomes extremely large (wiring Since the resistance of the wiring layer S2 is high, the problem that the resistance between the wiring connecting the input / output cell 1 and the pad 2 is high cannot be solved.

In summary, in the conventional multi-layer connection method, even though a plurality of planes capable of forming a low-resistance wiring layer are prepared (if the via hole is not formed, the wiring layer itself has low resistance and good conductivity). However, it has not been possible to realize a connection with a small resistance value and a low resistance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-layer connection method which realizes a low-resistance connection with a small variation in resistance value.

[0010]

In order to achieve the above object, a multi-layer connection method according to the present invention employs a plurality of wiring layers connected to each other via via holes formed between wiring layers. In the multilayer connection method for electrically connecting the via holes, the via holes are formed with a predetermined restriction in a direction perpendicular to the wiring direction.

In the above multi-layer connection method, for example, if the via holes are formed on a straight line parallel to the wiring direction and spaced from each other by 3 μm or more, a state in which a plurality of wiring layers are closely coupled to each other is obtained. In each wiring layer, a region having a width of 3 μm or more where no via hole exists can be continuously secured between two points while maintaining the above condition. And by this, while keeping the resistance value between the wiring layers low,
It is known that the increase in the resistance value of the wiring layer due to the via hole is suppressed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit adopting the multilayer connection method of the present invention will be described below. FIG. 1 is a plan view of a semiconductor integrated circuit as viewed from above, where 10 is a core portion on which a logic circuit or the like is formed, and 20 is an I / O portion. A plurality of input / output cells 1 are formed in the I / O section 20, and each input / output cell 1 is connected to a different pad 2 arranged on the outer peripheral portion 30 of the chip as shown by a broken line.

FIG. 2A is an enlarged plan view of a state where one input / output cell 1 and a pad 2 are connected as viewed from above, and FIG. 2B is a plan view of A in FIG. It is sectional drawing in -A '. In the present embodiment, the input / output cell 1 and the pad 2 are connected in multiple layers using two wiring layers S1 and S2.
A via hole V is formed in an insulating film Z separating the wiring layer S1 and the wiring layer S2 in a portion overlapping the input / output cell 1 and a portion overlapping the pad 2, as in the related art. And each of the wiring layers S1 and S2 is brought into contact with the input / output cell 1 and the pad 2. Further, between the input / output cell 1 and the pad 2,
The via hole V is formed with a predetermined restriction in the direction perpendicular to the wiring direction. Specifically, the via hole V is formed on a straight line that is parallel to the wiring direction and has an interval of 3 μm or more from each other. Thus, the wiring layer S1 and the wiring layer S2 are connected.

By connecting the input / output cell 1 and the pad 2 as described above, a region having a width of 3 μm or more where no via hole V exists in each of the wiring layers S1 and S2 is formed between the input / output cell 1 and the pad 2. Is secured continuously.

Conventionally, when a via hole V is formed between the input / output cell 1 and the pad 2, as many via holes V as possible are formed without limitation. The area in which no via was continuously formed was not substantially secured (the area having a width of at least 3 μm or more was never secured).

Here, as a result of the simulation, the width of the region where the via hole V does not exist, which is continuously secured between the input / output cell 1 and the pad 2, is set to 3 μm or more. That is, it is known that an increase in the resistance value of the wiring layer due to a reduction in the wiring width in the via hole V is suppressed.

In order to continuously secure a region where no via hole V exists between the input / output cell 1 and the pad 2, the formation of the via hole V is restricted in a direction perpendicular to the wiring direction. However, by forming as many via holes V in the direction parallel to the wiring direction as possible,
The wiring layers S1 and S2 are tightly coupled, and the resistance between the wiring layers S1 and S2 is kept low.

Therefore, in the semiconductor integrated circuit of this embodiment, the input / output cell 1 and the pad 2 are connected as if they were connected by one wiring layer having a wiring width twice as large as the wiring layers S1 and S2.
Are connected with little variation in resistance value and low resistance.

The case where two points are connected by using two wiring layers has been described as an example. However, the present invention is not limited to this case, and the case where three or more wiring layers are used. Of course, it is also effective. Further, the present invention is not limited to the connection between the input / output cells and the pads, and can be applied to various other connections such as a power supply line and a ground line.

[0020]

As described above, according to the multi-layer connection method of the present invention, a connection between any two points using a plurality of wiring layers can be formed with a low resistance value and a low resistance. It can be. That is, when the connection is made with n wiring layers, the same effect as when the connection is made with one wiring layer having n times the wiring width can be obtained by employing the multilayer connection method of the present invention. Therefore, according to the multilayer connection method of the present invention, it is possible to further reduce the wiring width,
For example, in a semiconductor integrated circuit or the like, the restriction due to the wiring width is reduced, and more input / output cells and pads can be arranged.

[Brief description of the drawings]

FIG. 1 is a plan view seen from above a semiconductor integrated circuit in which a multi-layer connection method of the present invention is used for connection between input / output cells and pads.

FIG. 2A is an enlarged plan view showing a state where one input / output cell 1 and a pad 2 are connected in FIG. 1 as viewed from above. FIG. 3B is a cross-sectional view taken along line AA ′ of FIG.

FIG. 3 is a diagram showing a conventional multilayer connection method.

FIG. 4 is a diagram showing a conventional multi-layer connection method different from that shown in FIG.

FIG. 5 shows a wiring layer S1 and a wiring layer S via a via hole V;
FIG. 2 is a diagram schematically showing a state in which No. 2 is combined.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 I / O cell 2 Pad 10 Core part 20 I / O part 30 Peripheral part of chip S1, S2 Wiring layer Z Insulating film V Via hole

Claims (3)

[Claims] 1. A multi-layer connection method for electrically connecting two points using a plurality of wiring layers connected to each other via via holes formed between respective wiring layers, wherein the via holes are perpendicular to a wiring direction. A multi-layer connection method, wherein a predetermined restriction is provided in a direction. 2. The multi-layer connection method according to claim 1, wherein the via holes are formed on straight lines that are parallel to a wiring direction and have an interval of 3 μm or more. 3. A semiconductor integrated circuit, wherein an input / output cell and a pad are connected by the multilayer connection method according to claim 1.