JPH1027951A - Wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize reduction of manufacturing cost by obtaining a wiring structure in which wiring connection between ICs or an IC and I/O terminals can be performed under an optimum condition, so that electric signal characteristics are prevented from deteriorating, the wiring area is prevented from being expanded, the wiring density is prevented from being lowered, and the number of substrate layers is reduced. SOLUTION: In this structure, a plurality of IC pads 5 which are arrayed on optional positions in optional order is connected to a plurality of electrodes (W of IC3/B pad 7) which are arrayed on a predetermined position in a given order. In this case, a thin film substrate 21 which is provided with a plurality of backside pads, which are connected to respective IC pads 5, on the back surface thereof and front side pads 27, which conduct to the backside pads and are arrayed facing the electrodes (W of IC3/ B pad 7) in an optimum condition, on the front surface thereof, is provided, and the backside pad is connected to the IC pad 5, and the thin film substrate 21 is provided to an IC 1, meanwhile, the front side pad 27 of the thin film substrate 21 is connected to the electrode (W of IC3/B pad 7).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a plurality of general-purpose ICs.
And a wiring structure for connecting the ICs or the ICs and I / O terminals of the substrate on which the IC is mounted.

[0002]

2. Description of the Related Art There are cases where a plurality of multi-pin general-purpose ICs are mounted on a multi-layer substrate to produce small, high-density functional components. A conventional wiring structure in such a case will be described with reference to FIG.
FIG. 4 is a plan view of a conventional wiring structure in which connection wiring between two ICs is represented by four wirings. Each IC
1. In IC3, the arrangement of IC pads (electrodes) 5 is different. IC pad 5 (A,
B, C, D) and the IC pad 5 of the IC 3 (A1, B1, C
1, D1), the IC pad 5 and the wire bonding (W / B) pad 7 in each of the IC 1 and IC 3 are connected by a wire 9 and the W / B pad 7 is connected to a wiring 11.
(A-A1, B-B1, C-C1,
DD). In addition, the crossing connection like B-B1 and C-C1 prevents the electrical short between the wirings 11 by changing the wiring layer by the via hole 13.

[0003]

However, in the above-described conventional wiring structure, the arrangement of the IC pads 5 is
1. Since the shortest length and the number of intersecting wirings are not minimum (hereinafter, such conditions are referred to as “optimal conditions”) with respect to the wirings 11 for connection between the ICs 3, the wirings 11 are routed and via holes are not provided. 13, the wiring layer must be changed, and the various problems described below occur. That is, there is a problem that the characteristics (delay time, reflection, loss, etc.) of the electric signal are deteriorated because the wiring length is long. In addition, the wiring area expanded due to the routing of the wiring, which hindered miniaturization. In addition, when the via hole 13 is frequently used, the via hole diameter is larger than the wiring width, so that there is a problem that the wiring density is reduced. Further, there is a problem in that the number of substrate layers is required as many as the number of intersecting wirings, thereby increasing the manufacturing cost. The present invention has been made in view of the above circumstances,
To provide a wiring structure that can perform wiring connection between under optimal conditions, to prevent deterioration of electric signal characteristics, prevent expansion of wiring area, prevent reduction of wiring density, and reduce manufacturing cost by reducing the number of substrate layers. With the goal.

[0004]

To achieve the above object, a wiring structure according to the present invention comprises a plurality of IC pads arranged in an arbitrary position and in an arbitrary order at a predetermined position and in a predetermined order. In the wiring structure connected to the plurality of electrodes arranged in the above, a plurality of backside pads connected to the respective IC pads are provided on the backside, and the front side electrically connected to the backside pads and arranged under the optimum condition with respect to the electrodes. A thin film substrate having a pad on the surface, wherein the back side pad is connected to the IC pad and the thin film substrate is provided on the IC, while a front side pad of the thin film substrate is connected to the electrode. is there.

In the wiring structure configured as described above, an IC in which IC pads are arranged at an arbitrary position and in an arbitrary order is provided.
When a thin film substrate is provided and the IC pad is connected to the back side pad of the thin film substrate, the front side pad electrically connected to the back side pad is placed at a predetermined position and in a predetermined order with respect to a plurality of electrodes, respectively. Are arranged to face each other.
That is, by providing the thin film substrate, the IC pads arranged at an arbitrary position and in an arbitrary order are rearranged under the optimum condition with respect to a plurality of electrodes arranged at a predetermined position and in an arbitrary order. It will be.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a wiring structure according to the present invention will be described below in detail with reference to the drawings. FIG.
Is a plan view showing a first embodiment of a wiring structure according to the present invention,
FIG. 2 is a sectional view taken along line XX of FIG. Note that the same members as those shown in FIG. 4 are denoted by the same reference numerals, and redundant description will be omitted. On the surface of IC1 (or IC3) (the surface on the side where IC pad 5 is formed), thin film substrates 21 having substantially the same outer shape as IC1 are provided.

As shown in FIG. 2, a plurality of back pads 23 are formed on the back surface of the thin film substrate 21 (the surface opposite to the IC pads 5), and the back pads 23 are formed of the IC 1 (or IC 3). It is formed in the same arrangement as the IC pad 5. The thin film substrate 21 is formed such that the back side pad 23 is
To electrically connect to the IC pad 5. The back pad 23 does not necessarily have to be connected to all the IC pads 5.

On the upper surface of the thin film substrate 21, the front side pads 27 arranged in an optimum condition for connecting IC1 and IC3 are connected.
The front pad 27 is connected to a predetermined rear pad 23 by a thin film wiring 29.
Therefore, the IC pad A of the IC 1 is A ′ of the thin film substrate 21,
B is connected to B 'and D is connected to D'. Also,
In the IC3, the IC pad A1 is connected to the A
1 'and C1 are respectively connected to C1'.

The front side pad 27 of the thin film substrate 21 is electrically connected to the W / B pad 7 via a wire 31.
Therefore, the front side pads 27 connected via the W / B pads 7 are arranged on the opposite sides of the adjacent ICs 1 and 3 in the same order from the lower side in FIG.
C ′, and those arranged in A1 ′, D1, B1, C1 ′. That is, by providing the thin film substrate 21, I
The arrangement of the C pads 5 is changed under optimum conditions.

In the above-mentioned wiring structure, the IC 1 and the IC 3 in which the arrangement of the IC pads 5 has been changed under the optimum condition are the shortest distance W 1.
/ B pads 7 are electrically connected to each other by a straight wiring 33 without intersecting (A'-A1 ', D'-D
1, B'-B1, C'-C1 ').

As described above, according to the above-described wiring structure, the thin-film substrate 21 for changing the arrangement of the IC pads 5 is provided on the ICs 1 and 3 so that the wirings 33 can be formed under optimum conditions. 3 can be connected with the shortest distance,
The characteristics of the electric signal can be improved. In addition, wiring routing is reduced, and wiring can be performed in a narrow wiring area. Further, since the number of via holes used can be reduced, it is possible to prevent a decrease in wiring density due to via pads. Further, since the number of intersecting wires can be reduced, the number of substrate layers can be reduced, and the manufacturing cost can be reduced.

Next, a second embodiment of the wiring structure according to the present invention will be described with reference to FIG. FIG. 3 is a plan view showing a second embodiment of the wiring structure according to the present invention. In the first embodiment described above, the ICs 1 and 3 are connected to each other. In this embodiment, the IC pad 5 of the IC 41 is connected to the I / O terminal (electrode) 4.
3 is connected. On the surface of the IC 41, this I
Thin film substrates 43 having substantially the same outer shape as C41 are provided.

A plurality of back pads 23 (see FIG. 2) are formed on the back of the thin film substrate 43.
It is formed in the same arrangement as the IC pad 5 of C41. The thin film substrate 43 electrically connects the back pad 23 to the IC pad 5 by the solder bump 25 (see FIG. 2).

On the upper surface of the thin film substrate 43, an IC 41 and an I / O
In connection with the terminals 44, front-side pads 27 are formed in an arrangement that satisfies the optimum conditions. The front-side pads 27 are connected to predetermined rear-side pads 23 by thin-film wirings 29, respectively. Therefore, the IC pad A of the IC 41 is connected to A 'of the thin film substrate 43, and the C is connected to C' of the thin film substrate 43, respectively.

The front side pad 27 of the thin film substrate 43 is electrically connected to the W / B pad 7 via a wire 31.
Therefore, the front side pad 27 connected via the W / B pad 7 is connected to the opposing I / O terminal 44 (A1, B1, C2).
1, D1), are arranged in A ', B, C', D. That is, by providing the thin film substrate 43,
The arrangement of the IC pads 5 is changed with respect to the I / O terminals 44 under optimum conditions.

In the above-described wiring structure, the IC 41 in which the arrangement of the IC pads 5 is changed under the optimum condition is electrically connected to the I / O terminal 44 by the wiring 45 at the shortest distance and without intersecting (A'-A1 '). , B-B1, C'-C1, D-
D1).

According to the wiring structure of this embodiment, the IC 41 is similar to the wiring structure of the first embodiment.
In connection between the IC 41 and the I / O terminal 44,
The connection with the terminal 44 can be made with the shortest distance, the characteristics of the electric signal can be improved, the wiring can be reduced, and the wiring can be performed in a narrow wiring area. Also, since the number of via holes used can be reduced, it is possible to prevent a decrease in wiring density,
Since the number of intersecting wires can be reduced, the number of substrate layers can be reduced, and the manufacturing cost can be reduced.

[0018]

As described above in detail, according to the wiring structure of the present invention, the backside pad connected to the IC pad is provided on the backside, and the backside pad is electrically connected to the electrode under the optimum condition. Since the thin-film substrate having the arranged front-side pads on the surface is provided, and the back-side pads are connected to the IC pads and the thin-film substrate is provided on the IC, the IC pads arranged in an arbitrary position and in an arbitrary order can be arranged in a predetermined manner. With respect to a plurality of electrodes arranged at a position and in a predetermined order, the arrangement can be changed under optimum conditions. As a result, the connection between the IC pad and the electrode can be made with the shortest distance, the characteristics of the electric signal can be improved, and the wiring can be performed in a narrow wiring area. In addition, since the number of via holes can be reduced, it is possible to prevent a decrease in wiring density due to via pads, to reduce the number of substrate layers, and to reduce manufacturing costs.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a wiring structure according to the present invention.

FIG. 2 is a sectional view taken along line XX of FIG.

FIG. 3 is a plan view showing a second embodiment of the wiring structure according to the present invention.

FIG. 4 is a plan view of a conventional wiring structure in which connection wiring between two ICs is represented by four wirings.

[Explanation of symbols]

1, 3 IC 5 IC pad (electrode) 21 Thin film substrate 23 Back pad 27 Front pad 44 I / O terminal (electrode)

Claims (3)

[Claims] 1. A wiring structure for connecting a plurality of IC pads arranged at an arbitrary position and in an arbitrary order to a plurality of electrodes arranged at a predetermined position and in an predetermined order, wherein each of the IC pads is connected to each of the IC pads. A thin film substrate having a plurality of back side pads on the back side and a front side pad on the front side, which is electrically connected to the back side pads and arranged on the surface under the optimum conditions with respect to the electrodes, wherein the back side pads are connected to the IC pads. Wherein the thin-film substrate is provided on an IC while a front-side pad of the thin-film substrate is connected to the electrode. 2. The wiring structure according to claim 1, wherein said electrodes are IC pads of different ICs. 3. The wiring structure according to claim 1, wherein said electrode is an I / O terminal.