JPH11121500A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH11121500A
JPH11121500A JP9283939A JP28393997A JPH11121500A JP H11121500 A JPH11121500 A JP H11121500A JP 9283939 A JP9283939 A JP 9283939A JP 28393997 A JP28393997 A JP 28393997A JP H11121500 A JPH11121500 A JP H11121500A
Authority
JP
Japan
Prior art keywords
wiring
semiconductor device
solder resist
substrate
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9283939A
Other languages
Japanese (ja)
Other versions
JP2993480B2 (en
Inventor
Kojiro Shibuya
幸二郎 渋谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9283939A priority Critical patent/JP2993480B2/en
Publication of JPH11121500A publication Critical patent/JPH11121500A/en
Application granted granted Critical
Publication of JP2993480B2 publication Critical patent/JP2993480B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a bonding wire from coming into contact with other wirings, by electrically connecting a wiring pattern on a board and a fixed semiconductor chip by using bonding wires and arranging high insulating layers between a GND wiring, a power source wiring, and a signal wiring of the wiring pattern. SOLUTION: A wiring pattern formed on a wiring board 21 is covered with insulating solder resist 9 except wire bonding areas of a GND wiring 5, a power source wiring 6, and a signal wiring 7. Rectangular solder resist (insulator) 22a which is the same kind of the solder resist 9 is formed between the GND wiring 5 and the power source wiring 6. Rectangular solder resist 22b (insulator) which is the same kind of the solder resist 9 is formed between the power source wiring 6 and the signal wiring 7. As a result, electric short circuit can be prevented when loop sag, deformation, etc., are generated in bonding wires 8a-8c.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に、ワイヤボンディング技術を用いて基板上の配
線パターンと該基板上に固定された半導体チップとを電
気的に接続した半導体装置に関するものである。The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a wiring pattern on a substrate is electrically connected to a semiconductor chip fixed on the substrate by using a wire bonding technique. is there.

【０００２】[0002]

【従来の技術】図５は従来のオーバーモールドタイプの
半導体装置の要部を示す平面図、図６は同半導体装置を
示す断面図であり、上面に配線パターンが配設された基
板１の中央部には、半導体チップ２が導電性ペースト３
を介して固定され、この半導体チップ２の上面に設けら
れた電極４と、基板１上に半導体チップ２を取り囲むよ
うに矩形状に配設された配線パターンのＧＮＤ（グラン
ド）配線５及び電源配線６、及び電源配線６の外側に配
設された複数本の信号配線７とは、各々ボンディングワ
イヤ８ａ〜８ｃにより電気的に接続されている。2. Description of the Related Art FIG. 5 is a plan view showing a main part of a conventional overmold type semiconductor device, and FIG. 6 is a sectional view showing the same semiconductor device. In the part, the semiconductor chip 2 is a conductive paste 3
And an electrode 4 provided on the upper surface of the semiconductor chip 2, a GND (ground) wiring 5 of a wiring pattern disposed in a rectangular shape on the substrate 1 so as to surround the semiconductor chip 2, and a power supply wiring 6 and a plurality of signal wires 7 disposed outside the power supply wire 6 are electrically connected by bonding wires 8a to 8c, respectively.

【０００３】前記基板１上に配設された配線パターン
は、ＧＮＤ配線５、電源配線６、信号配線７等のワイヤ
ボンディングエリア以外の領域は、絶縁性のソルダーレ
ジスト９により覆われている。そして、基板１上の配線
パターンは、基板１に形成されたスルーホール１０を通
して基板１の下側にある半田ボールランド１１に接続さ
れ、半田ボールランド１１には半田ボール１２が形成さ
れている。一方、基板１の上面は、半導体チップ２及び
ボンディングワイヤ８ａ〜８ｃ全体をエポキシ樹脂等の
封止樹脂１３により覆われている。In the wiring pattern provided on the substrate 1, areas other than the wire bonding area such as the GND wiring 5, the power supply wiring 6, and the signal wiring 7 are covered with an insulating solder resist 9. The wiring pattern on the substrate 1 is connected to a solder ball land 11 on the lower side of the substrate 1 through a through hole 10 formed in the substrate 1, and a solder ball 12 is formed on the solder ball land 11. On the other hand, the upper surface of the substrate 1 is covered with a sealing resin 13 such as an epoxy resin on the entire semiconductor chip 2 and the bonding wires 8a to 8c.

【０００４】また、上述したオーバーモールドタイプ以
外の半導体装置としては、例えば、キャビティーダウン
タイプの半導体装置がある。この半導体装置は、メタル
スラグ等の金属基板上に、配線パターンが配設された配
線基板と半導体チップとを固定し、該半導体チップの電
極と、配線パターンのＧＮＤ配線、電源配線及び信号配
線とを、各々ボンディングワイヤにより電気的に接続
し、半導体チップ及びボンディングワイヤ全体をエポキ
シ樹脂等の封止樹脂で覆うとともに、配線基板上に半田
ボール等を形成したものである。As a semiconductor device other than the above-mentioned overmold type, for example, there is a cavity-down type semiconductor device. In this semiconductor device, a wiring board on which a wiring pattern is provided and a semiconductor chip are fixed on a metal substrate such as a metal slug, and electrodes of the semiconductor chip, GND wiring, power supply wiring and signal wiring of the wiring pattern are formed. Are electrically connected by bonding wires, the entire semiconductor chip and the bonding wires are covered with a sealing resin such as an epoxy resin, and solder balls and the like are formed on a wiring board.

【０００５】[0005]

【発明が解決しようとする課題】従来の半導体装置の問
題点は、例えば、ボンディングワイヤ８ｃの場合、その
ループの一部がＧＮＤ配線５や電源配線６を跨いで信号
配線７にボンディングされているために、ボンディング
ワイヤ８ｃの配線パターン側のボンディング点付近のル
ープ垂れやトランスファモールドの際の注入樹脂による
変形等により、ＧＮＤ配線５や電源配線６あるいは他の
信号配線７に接触し易くなり、電気的なショートを起こ
す虞があるという点である。The problem of the conventional semiconductor device is that, for example, in the case of the bonding wire 8c, a part of the loop is bonded to the signal wiring 7 across the GND wiring 5 and the power supply wiring 6. For this reason, the loop of the bonding wire 8c near the bonding point on the wiring pattern side and the deformation due to the injected resin at the time of the transfer molding and the like are likely to make contact with the GND wiring 5, the power supply wiring 6, or other signal wirings 7, and the electric power is reduced. That is, there is a risk of causing a short circuit.

【０００６】本発明は、上記の事情に鑑みてなされたも
のであって、ボンディングワイヤが他の配線を跨いでボ
ンディングされた場合であっても、ボンディングワイヤ
が他の配線に接触する虞が無く、ボンディングワイヤの
ループ垂れや変形に起因する電気的なショートを防止す
る半導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and there is no danger that the bonding wire will come into contact with another wiring even when the bonding wire straddles another wiring. It is another object of the present invention to provide a semiconductor device that prevents an electrical short due to a loop droop or deformation of a bonding wire.

【０００７】[0007]

【課題を解決するための手段】上記課題を解決するため
に、本発明は次の様な半導体装置を提供する。すなわ
ち、基板上に配設された配線パターンと、該基板上に固
定された半導体チップとを、ボンディングワイヤにより
電気的に接続し、前記配線パターンのグランド配線、電
源配線、信号配線それぞれの間に、これらの配線より高
さが高い絶縁体を設けたものである。In order to solve the above problems, the present invention provides the following semiconductor device. That is, the wiring pattern provided on the substrate and the semiconductor chip fixed on the substrate are electrically connected by bonding wires, and the wiring pattern is provided between the ground wiring, the power supply wiring, and the signal wiring. And an insulator having a height higher than these wirings.

【０００８】前記グランド配線及び電源配線を、前記信
号配線より半導体チップ側にある構成としてもよい。ま
た、前記グランド配線を、前記電源配線及び信号配線よ
り半導体チップ側にある構成としてもよい。また、前記
絶縁体を前記半導体チップの周辺に設けた構成としても
よい。さらに、前記基板をプリント配線基板とした構成
としてもよい。The ground wiring and the power supply wiring may be arranged on the semiconductor chip side of the signal wiring. Further, the ground wiring may be located on the semiconductor chip side of the power supply wiring and the signal wiring. Further, the insulator may be provided around the semiconductor chip. Further, the substrate may be configured as a printed wiring board.

【０００９】本発明の半導体装置では、前記配線パター
ンのグランド配線、電源配線、信号配線それぞれの間
に、これらの配線より高さが高い絶縁体を設けたことに
より、半導体チップと配線パターンの所望の配線とを電
気的に接続したボンディングワイヤがループ垂れや変形
を起こしても、このボンディングワイヤが他の配線に接
触する前に絶縁体に接触し、他の配線に接触するのを防
止する。これにより、ボンディングワイヤのループ垂れ
や変形に起因する電気的なショートを防止することが可
能になる。In the semiconductor device according to the present invention, an insulator having a height higher than these wirings is provided between the ground wiring, the power supply wiring, and the signal wiring of the wiring pattern. Even if the bonding wire electrically connected to the wiring has a loop droop or deformation, the bonding wire contacts the insulator before contacting another wiring, thereby preventing the bonding wire from contacting another wiring. As a result, it is possible to prevent an electrical short due to the loop drooping or deformation of the bonding wire.

【００１０】[0010]

【発明の実施の形態】本発明の半導体装置の各実施形態
について図面に基づき説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of the semiconductor device of the present invention will be described with reference to the drawings.

【００１１】［第１の実施形態］図１は本発明の第１の
実施形態のオーバーモールドタイプの半導体装置の要部
を示す平面図、図２は同断面図であり、上面に配線パタ
ーンが配設されたガラスエポキシ基板（プリント配線基
板：以下、単に基板と略称する）２１の中央部には、半
導体チップ２が導電性ペースト３を介して固定され、こ
の半導体チップ２の上面に設けられた電極４と、ガラス
エポキシ基板２１上に半導体チップ２を取り囲むように
矩形状に配設された配線パターンのＧＮＤ配線５及び電
源配線６、及び電源配線６の外側に配設された複数本の
信号配線７とは、各々ボンディングワイヤ８ａ〜８ｃに
より電気的に接続されている。[First Embodiment] FIG. 1 is a plan view showing a main part of an overmold type semiconductor device according to a first embodiment of the present invention, and FIG. A semiconductor chip 2 is fixed via a conductive paste 3 to a central portion of a glass epoxy board (printed wiring board: hereinafter simply abbreviated to “substrate”) 21 provided on the upper surface of the semiconductor chip 2. Electrode 4, GND wiring 5 and power supply wiring 6 of a wiring pattern arranged in a rectangular shape so as to surround semiconductor chip 2 on glass epoxy substrate 21, and a plurality of wirings arranged outside power supply wiring 6. The signal wiring 7 is electrically connected to each of the bonding wires 8a to 8c.

【００１２】前記基板２１上に配設された配線パターン
は、ＧＮＤ配線５、電源配線６、信号配線７のワイヤボ
ンディングエリア以外の領域は、絶縁性のソルダーレジ
スト９により覆われている。そして、ＧＮＤ配線５と電
源配線６との間には前記ソルダーレジスト９と同種の矩
形状のソルダーレジスト（絶縁体）２２ａが、また、電
源配線６と信号配線７との間には前記ソルダーレジスト
９と同種の矩形状のソルダーレジスト（絶縁体）２２ｂ
が、それぞれ形成されている。In the wiring pattern provided on the substrate 21, areas other than the wire bonding area of the GND wiring 5, the power supply wiring 6, and the signal wiring 7 are covered with an insulating solder resist 9. A rectangular solder resist (insulator) 22a of the same kind as the solder resist 9 is provided between the GND wiring 5 and the power supply wiring 6, and the solder resist 22a is provided between the power supply wiring 6 and the signal wiring 7. Rectangular solder resist (insulator) 22b of the same kind as 9
Are formed respectively.

【００１３】これらのソルダーレジスト２２ａ、２２ｂ
は、近傍にある配線のボンディング点にボンディングツ
ールでボンディングした時、ボンディングツールとボン
ディングワイヤ８ａ〜８ｃが、ソルダーレジスト２２
ａ、２２ｂに干渉しない程度に位置している。また、こ
れらのソルダーレジスト２２ａ、２２ｂの上面の高さ
は、配線パターンを覆っているソルダーレジスト９の上
面と同一の高さになっている。These solder resists 22a, 22b
Means that the bonding tool and the bonding wires 8a to 8c are connected to the solder resist 22
a, 22b. The height of the upper surfaces of the solder resists 22a and 22b is the same as the upper surface of the solder resist 9 covering the wiring pattern.

【００１４】通常、ソルダーレジスト２２ａ、２２ｂの
上面の高さは、ＧＮＤ配線５、電源配線６及び信号配線
７の配線パターンより３０〜５０μｍ程度高い。これら
のソルダーレジスト２２ａ、２２ｂは、露光現象を用い
た技術により簡単に形成することができる。Normally, the height of the upper surfaces of the solder resists 22a and 22b is higher than the wiring patterns of the GND wiring 5, the power supply wiring 6 and the signal wiring 7 by about 30 to 50 μm. These solder resists 22a and 22b can be easily formed by a technique using an exposure phenomenon.

【００１５】そして、基板２１上の配線パターンは、基
板２１に形成されたスルーホール１０を通して基板２１
の下側にある半田ボールランド１１に接続され、半田ボ
ールランド１１には半田ボール１２が形成されている。
一方、基板２１の上面は、半導体チップ２及びボンディ
ングワイヤ８ａ〜８ｃ全体をエポキシ樹脂等の封止樹脂
１３により覆われている。The wiring pattern on the substrate 21 passes through the through hole 10 formed in the substrate 21.
The solder ball land 11 is connected to a solder ball land 11 below the solder ball land 11, and a solder ball 12 is formed on the solder ball land 11.
On the other hand, the entire upper surface of the substrate 21 is covered with a sealing resin 13 such as an epoxy resin on the entire semiconductor chip 2 and the bonding wires 8a to 8c.

【００１６】本実施形態の半導体装置によれば、ＧＮＤ
配線５と電源配線６との間に矩形状のソルダーレジスト
（絶縁体）２２ａを、また、電源配線６と信号配線７と
の間に矩形状のソルダーレジスト（絶縁体）２２ｂを、
それぞれ形成したので、ボンディングワイヤ８ａ〜８ｃ
にループ垂れや変形等が発生した場合であっても、ボン
ディングワイヤ８ａ〜８ｃが他の配線に接触する前にソ
ルダレジスト２２ａ、２２ｂに接触するため、電気的な
ショート不良を防止することができ、半導体装置として
の信頼性を向上させることができる。これらのソルダレ
ジスト２２ａ、２２ｂは、特にループ垂れ及び変形が生
じ易い長ワイヤボンディング時に効果的である。According to the semiconductor device of this embodiment, GND
A rectangular solder resist (insulator) 22a between the wiring 5 and the power supply wiring 6, and a rectangular solder resist (insulator) 22b between the power supply wiring 6 and the signal wiring 7;
Since each was formed, the bonding wires 8a to 8c
Even if loop drooping or deformation occurs, the bonding wires 8a to 8c come into contact with the solder resists 22a and 22b before coming into contact with other wiring, so that an electrical short circuit can be prevented. As a result, the reliability of the semiconductor device can be improved. These solder resists 22a and 22b are particularly effective at the time of long wire bonding where loop drooping and deformation tend to occur.

【００１７】なお、本実施形態の半導体装置では、ＧＮ
Ｄ配線５と電源配線６との間に矩形状のソルダーレジス
ト２２ａを、また、電源配線６と信号配線７との間に矩
形状のソルダーレジスト２２ｂを、それぞれ形成した構
成としたが、これらのソルダレジスト２２ａ、２２ｂ
は、ボンディングワイヤ８ａ〜８ｃが他の配線に接触す
る前に接触するような構成であればよく、上述した矩形
状に限定されることなく様々な形状、例えば、島状に配
列する等断続的に設ける構成とすることも可能である。In the semiconductor device of this embodiment, GN
Although a rectangular solder resist 22a is formed between the D wiring 5 and the power wiring 6, and a rectangular solder resist 22b is formed between the power wiring 6 and the signal wiring 7, respectively. Solder resists 22a, 22b
Any structure may be used as long as the bonding wires 8a to 8c come into contact with each other before they come into contact with other wiring, and are not limited to the rectangular shape described above, but may be variously shaped, for example, intermittently arranged in an island shape. May be provided.

【００１８】［第２の実施形態］図３は本発明の第２の
実施形態のキャビティーダウンタイプの半導体装置の要
部を示す平面図、図４は同断面図であり、銅等からなる
メタル基板３１上には半導体チップ２が導電性ペースト
３を介して固定され、この半導体チップ２の周囲には、
配線パターンが形成された基板３２が導電性の接着剤３
３を介してメタル基板３１上に固定されている。[Second Embodiment] FIG. 3 is a plan view showing a main part of a cavity-down type semiconductor device according to a second embodiment of the present invention, and FIG. 4 is a sectional view of the same, which is made of copper or the like. The semiconductor chip 2 is fixed on the metal substrate 31 via the conductive paste 3, and around the semiconductor chip 2,
The substrate 32 on which the wiring pattern is formed is a conductive adhesive 3
3 and is fixed on the metal substrate 31.

【００１９】この基板３２の最内周には、メタル基板３
１と電気的に接続されるＧＮＤ配線３４が形成され、Ｇ
ＮＤ配線３４を取り囲むように、信号配線３５と電源配
線３６がそれぞれ複数本配設されている。そして、ＧＮ
Ｄ配線３４と、信号配線３５及び電源配線３６との間に
は、これらの配線３４〜３６の高さより高い短冊状のソ
ルダーレジスト（絶縁体）３７が形成されている。On the innermost periphery of the substrate 32, a metal substrate 3
1 is formed, and a GND wiring 34 electrically connected to
A plurality of signal wirings 35 and a plurality of power supply wirings 36 are provided so as to surround the ND wiring 34. And GN
A strip-shaped solder resist (insulator) 37 that is higher than the heights of these wirings 34 to 36 is formed between the D wiring 34, the signal wiring 35, and the power wiring 36.

【００２０】本実施形態のパッケージとなる半導体チッ
プ２及び基板３２上の封止樹脂１３の高さは、図示しな
いマザーボードに実装する関係上、基板３２の外周部に
取り付けられた半田ボール１２よりも約０．２５ｍｍ以
上低くする必要がある。そこで、封止樹脂１３の流動を
阻止するダム樹脂３８の高さを半田ボール１２よりも約
０．２５ｍｍ以上低くしている。また、ボンディングワ
イヤ８ａ、８ｂのループ高さも低く抑え、かつ、ボンデ
ィングワイヤ８ａ、８ｂと配線パターンのＧＮＤ配線３
４との距離を確実に保つ必要がある。The height of the sealing resin 13 on the semiconductor chip 2 and the substrate 32 to be the package of the present embodiment is larger than that of the solder balls 12 attached to the outer peripheral portion of the substrate 32 because of mounting on a motherboard (not shown). It needs to be lower by about 0.25 mm or more. Therefore, the height of the dam resin 38 for preventing the flow of the sealing resin 13 is set to be lower than the solder ball 12 by about 0.25 mm or more. Further, the loop height of the bonding wires 8a, 8b is also kept low, and the bonding wires 8a, 8b and the GND wiring 3 of the wiring pattern are formed.
It is necessary to keep the distance to 4 securely.

【００２１】本実施形態の半導体装置によれば、ＧＮＤ
配線３４と、信号配線３５及び電源配線３６との間に、
これらの配線３４〜３６の高さより高い短冊状のソルダ
ーレジスト３７を形成したので、上記第１の実施形態の
半導体装置と同様の効果を奏することができる。しか
も、低ループボンディングが必要なパッケージに対して
非常に効果的である。According to the semiconductor device of this embodiment, GND
Between the wiring 34, the signal wiring 35 and the power supply wiring 36,
Since the strip-shaped solder resist 37 that is higher than the heights of these wirings 34 to 36 is formed, the same effect as the semiconductor device of the first embodiment can be obtained. Moreover, it is very effective for packages requiring low loop bonding.

【００２２】[0022]

【発明の効果】以上説明した様に、本発明の半導体装置
によれば、配線パターンのグランド配線、電源配線、信
号配線それぞれの間に、これらの配線より高さが高い絶
縁体を設けたので、半導体チップと配線パターンの所望
の配線とを電気的に接続したボンディングワイヤがルー
プ垂れや変形を起こしても、このボンディングワイヤが
他の配線に接触する前に絶縁体に接触し、他の配線に接
触するのを防止することができる。したがって、ボンデ
ィングワイヤのループ垂れや変形に起因する電気的なシ
ョートを防止することができ、半導体装置の信頼性を向
上させることができる。As described above, according to the semiconductor device of the present invention, the insulator having a height higher than these wirings is provided between the ground wiring, the power supply wiring, and the signal wiring of the wiring pattern. Even if a bonding wire that electrically connects a semiconductor chip and a desired wiring of a wiring pattern causes loop drooping or deformation, the bonding wire comes into contact with an insulator before coming into contact with another wiring, thereby causing another wiring. Can be prevented. Therefore, it is possible to prevent an electrical short due to the loop drooping or deformation of the bonding wire, and it is possible to improve the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の第１の実施形態のオーバーモールド
タイプの半導体装置の要部を示す平面図である。FIG. 1 is a plan view showing a main part of an overmold type semiconductor device according to a first embodiment of the present invention.

【図２】 本発明の第１の実施形態のオーバーモールド
タイプの半導体装置の要部を示す断面図である。FIG. 2 is a cross-sectional view illustrating a main part of the overmold type semiconductor device according to the first embodiment of the present invention.

【図３】 本発明の第２の実施形態のキャビティーダウ
ンタイプの半導体装置の要部を示す平面図である。FIG. 3 is a plan view illustrating a main part of a cavity-down type semiconductor device according to a second embodiment of the present invention.

【図４】 本発明の第２の実施形態のキャビティーダウ
ンタイプの半導体装置の要部を示す断面図である。FIG. 4 is a sectional view showing a main part of a cavity-down type semiconductor device according to a second embodiment of the present invention.

【図５】 従来のオーバーモールドタイプの半導体装置
の要部を示す平面図である。FIG. 5 is a plan view showing a main part of a conventional overmold type semiconductor device.

【図６】 従来のオーバーモールドタイプの半導体装置
を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional overmold type semiconductor device.

【符号の説明】[Explanation of symbols]

１ 基板 ２ 半導体チップ ３ 導電性ペースト ４ 電極 ５ ＧＮＤ（グランド）配線 ６ 電源配線 ７ 信号配線 ８ａ〜８ｃ ボンディングワイヤ ９ ソルダーレジスト １０ スルーホール １１ 半田ボールランド １２ 半田ボール １３ 封止樹脂 ２１ ガラスエポキシ基板（プリント配線基板） ２２ａ、２２ｂ ソルダーレジスト（絶縁体） ３１ メタル基板 ３２ 基板 ３３ 導電性の接着剤 ３４ ＧＮＤ配線 ３５ 信号配線 ３６ 電源配線 ３７ ソルダーレジスト（絶縁体） ３８ ダム樹脂 Reference Signs List 1 substrate 2 semiconductor chip 3 conductive paste 4 electrode 5 GND (ground) wiring 6 power supply wiring 7 signal wiring 8a to 8c bonding wire 9 solder resist 10 through hole 11 solder ball land 12 solder ball 13 sealing resin 21 glass epoxy substrate ( Printed circuit board) 22a, 22b Solder resist (insulator) 31 Metal substrate 32 Substrate 33 Conductive adhesive 34 GND wiring 35 Signal wiring 36 Power supply wiring 37 Solder resist (insulator) 38 Dam resin

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 基板上に配設された配線パターンと、該
基板上に固定された半導体チップとを、ボンディングワ
イヤにより電気的に接続してなる半導体装置において、 前記配線パターンのグランド配線、電源配線、信号配線
それぞれの間に、これらの配線より高さが高い絶縁体を
設けたことを特徴とする半導体装置。1. A semiconductor device in which a wiring pattern provided on a substrate and a semiconductor chip fixed on the substrate are electrically connected by bonding wires, wherein a ground wiring of the wiring pattern and a power supply are provided. A semiconductor device, wherein an insulator having a height higher than the wiring is provided between the wiring and the signal wiring. 【請求項２】 前記グランド配線及び電源配線は、前記
信号配線より半導体チップ側にあることを特徴とする請
求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the ground wiring and the power supply wiring are closer to the semiconductor chip than the signal wiring. 【請求項３】 前記グランド配線は、前記電源配線及び
信号配線より半導体チップ側にあることを特徴とする請
求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the ground wiring is closer to the semiconductor chip than the power supply wiring and the signal wiring. 【請求項４】 前記絶縁体は、前記半導体チップの周辺
に設けられていることを特徴とする請求項１、２または
３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the insulator is provided around the semiconductor chip. 【請求項５】 前記基板は、プリント配線基板であるこ
とを特徴とする請求項１、２、３または４記載の半導体
装置。5. The semiconductor device according to claim 1, wherein said substrate is a printed wiring board.
JP9283939A 1997-10-16 1997-10-16 Semiconductor device Expired - Fee Related JP2993480B2 (en)

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Application Number Priority Date Filing Date Title
JP9283939A JP2993480B2 (en) 1997-10-16 1997-10-16 Semiconductor device

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JPH11121500A true JPH11121500A (en) 1999-04-30
JP2993480B2 JP2993480B2 (en) 1999-12-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056966A (en) * 2012-09-13 2014-03-27 Renesas Electronics Corp Semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056966A (en) * 2012-09-13 2014-03-27 Renesas Electronics Corp Semiconductor device manufacturing method

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