JPH11121469A - Manufacture of field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of FET(Field Effect Transistor) with good uniformity and repeatability that comprises a double-stepped recess structure having a low parasitic source drain resistance and high gate breakdown voltage. SOLUTION: A buffer layer 12, the first active layer 13a, an etching stop layer 14 and the second active layer 13b are formed on a semi-insulating GaAs substrate 11 sequentially. Then, a source electrode 15 and a drain electrode 16 are formed. The second active layer 13b is etched isotropically with a mask of a resist film 17, using mixed gas with SiCl4 and SF6 , applying no high frequency power to substrate electrodes, and an upper recess 18 is formed. Next, the second layer 13b is etched anisotrpically with a mask of the same resist film 17, using mixed gas with SiCl4 , SF6 and N2 , applying the high frequency power to the substrate electrodes, and formed is a lower recess 19 in the upper recess 18. Finally, a gate electrode 20 is formed on a bottom surface of the lower recess 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field-effect transistor, and more particularly to a method for manufacturing a field-effect transistor for a high-speed compound semiconductor IC used in communication equipment and computers.

[0002]

2. Description of the Related Art Conventionally, in a field-effect transistor (hereinafter referred to as an FET) using a compound semiconductor such as GaAs, a parasitic source-drain resistance between a gate and a source and between a gate and a drain are reduced, and the gate-source is reduced. In order to increase the breakdown voltage between the gate and the drain, a two-stage recess structure is used in which the active layer in the gate electrode formation portion above the channel layer (n-layer) is etched in two stages.

Hereinafter, the manufacturing method will be described with reference to FIG.

First, in a step shown in FIG. 7A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and a 5 × Si layer are formed on a semi-insulating GaAs substrate 11.
N with a thickness of about 500 nm doped about 10 ¹⁷ cm ^-3
After successively epitaxially growing an active layer 13 made of a type GaAs layer, a source electrode 15 and a drain electrode 16 made of AuGe / Ni / Au are formed at positions separated from each other on the active layer 13.

Next, in a step shown in FIG. 7B, after a resist film 41 is formed on the substrate, an H ₃ PO ₄ / H ₂ O ₂ / H ₂ O system is used by using the resist film 41 as a mask. Performing isotropic etching of the active layer 13 with an etchant,
The upper recessed portion 18 wider than the opening 41 a of the first resist film 41 is formed in the active layer 13.

Next, after removing the resist film 41, a second resist film 42 having an opening 42a which is partially open at the bottom surface of the upper recess portion 18, that is, has an opening 42a narrower than the bottom surface of the upper recess portion 18, is formed. Form.

[0007] Next, in the step shown in FIG. 7 (c), using the second resist film 42 as a _{mask, H 3 PO 4 / H 2} O 2
A lower recess 19 is formed in the upper recess 18 by performing isotropic etching of the active layer 13 with a / H ₂ O-based etchant.

Next, in a step shown in FIG. 7D, a gate electrode 20 made of Al is formed on the lower recessed portion 19.

According to this manufacturing method, the active layer 13 has the largest thickness at the contact portion immediately below the source electrode 15 and the drain electrode 16, the second largest thickness at the bottom of the upper recess 18, and the thickness of the gate electrode 20. Immediately below, ie, the lower recess 1
9, the parasitic source-drain resistance between the gate and the source and between the gate and the drain is reduced, and between the gate and the source and between the gate and the source.
The breakdown voltage between the drains can be increased.

However, in this manufacturing method, two photolithography steps are required to form a two-step recess structure, and the number of steps is large, so that the manufacturing cost is high. In addition, since the position of the lower recess 19 in the upper recess 18 is determined by photolithography alignment, the distance between the gate and the source and the distance between the gate and the drain are varied and formed. There is a problem that the in-plane uniformity and reproducibility of the gate breakdown voltage and the mutual conductance in the FET are low.

Therefore, as a method of forming a two-step recess structure with a small number of steps without photolithography alignment, the following manufacturing method is used. (Documents Jpn. J. Appl. Phys., Vol. 31 (1
992) pp. 2374-2381) Hereinafter, the manufacturing method will be described with reference to FIGS.

First, in a step shown in FIG. 8 (a), a buffer layer 12 made of an undoped GaAs layer and an n-doped n-type silicon layer of about 1.2 × 10 ¹⁷ cm ^-3 are formed on a semi-insulating GaAs substrate 11. After successively epitaxially growing a 600 nm-thick active layer 13 composed of a GaAs type
An insulating film 21 made of a film is deposited, and then a source electrode 15 and a drain electrode 16 are formed on the active layer 13 at positions separated from each other.

Next, in a step shown in FIG. 8B, an opening 51a is formed on the substrate in a region where a gate electrode is to be formed.
Forming a resist film 51 having
After the opening 21a of the insulating film 21 is formed by performing dry etching of the insulating film 21 using
The lower layer recess 19 is formed by performing isotropic etching of the active layer 13 using the mask 1 and the insulating film 21 as a mask.

Next, in the step shown in FIG. 8C, wet etching (side etching) of the insulating film 21 is performed using the resist film 51 as a mask, and the opening 2 of the insulating film 21 is formed.
1a is expanded laterally.

Next, in the step shown in FIG. 8D, isotropic etching of the active layer 13 is performed using the resist film 51 and the insulating film 21 as a mask. At this time, the lower recessed portion 19 is enlarged and spreads laterally and downward, and the region immediately below the insulating film 21 is greatly enlarged laterally and the lower recessed portion 1 is enlarged.
An upper recess 18 having the upper surface of the lower surface 9 as a bottom surface is formed.

Next, in the step shown in FIG. 8E, the gate electrode 2 made of Ti / Mo is formed on the bottom of the lower recessed portion 19.
0 is formed.

According to this manufacturing method, since only one photolithography step is used in the recess step, a two-step recess structure can be formed with a small number of steps without photolithographic alignment.

[0018]

However, in the manufacturing method described in the above-mentioned document, when the second isotropic etching of the active layer 13 is performed, the lower recessed portion 19 formed first is not only located at the lower part but also at the lower part. Because it is expanded to the side,
Only the lower recess 19 having a width larger than the width of the opening 51a of the resist film 51 can be formed.
In other words, the width of the lower recess 19 is determined by the resolution of the photolithography.
This is considerably larger than the minimum dimension of a. Also,
The size and shape of each recessed portion are determined by the total of two isotropic etchings of the active layer 13, so that there is a problem that the controllability of the size and shape is poor.

The present invention has been made in view of such a point, and an object of the present invention is to provide a means for forming a two-step recess structure with uniformity and controllability in a recess step with as few photolithography steps as possible. Accordingly, it is an object of the present invention to provide a method for manufacturing an FET which can form an FET having a low parasitic source / drain resistance and a high gate breakdown voltage at low cost.

[0020]

Means for Solving the Problems To achieve the above object, means relating to a method for manufacturing a field effect transistor according to claims 1 to 15 are taken.

According to the first method of manufacturing a field effect transistor of the present invention, a resist film having an opening in a gate electrode formation region is formed on a semiconductor region on a substrate. And a second step of performing isotropic etching of the semiconductor region using the resist film as a mask to form an upper recess portion wider than the opening of the resist film in the semiconductor region. A third step of performing anisotropic etching of the semiconductor region using the resist film as a mask to form a lower recess in a region below the opening of the resist film in the semiconductor region. I have.

According to this method, the resist film used for forming the upper recess by isotropic etching in the second step is used as it is, and the lower recess is formed by anisotropic etching in the third step. As a result, the position of the lower recessed portion within the upper recessed portion is determined in a self-aligned manner. In addition, since the anisotropic etching is performed in the third step, the dimension of the upper recess formed first does not substantially change in this step, and the shape and width of the entire recess are controlled. Good nature. Further, since the width of the lower recess is substantially equal to the width of the resist film, a fine structure can be realized. Therefore, an FET having a low parasitic source / drain resistance and a high gate breakdown voltage with a small number of photolithography steps can be manufactured with good uniformity and reproducibility.

According to a second aspect, in the first aspect, an insulating film is formed on the semiconductor region before the first step, and the insulating film is formed in the first step. The resist film is formed on the film, and before the second step, isotropic etching of the insulating film is performed using the resist film as a mask, so that the insulating film has a thickness higher than that of the opening of the resist film. A wide insulating film opening may be formed, and in the second step, the upper recess may be formed to be wider than the insulating film opening.

According to this method, in addition to the function of the first aspect, only the width of the upper recessed portion can be increased while keeping the width of the lower recessed portion small, so that it is higher than that of the first embodiment. It becomes possible to manufacture an FET having a gate breakdown voltage.

According to a second aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: a first step of forming an insulating film on a semiconductor region on a substrate; Forming a first resist film having an opening in a gate electrode formation region thereon, and etching the insulating film using the first resist film as a mask to form an opening in the insulating film. A third step of forming
A fourth step of forming a second resist film having an opening overlapping with the opening of the insulating film on the substrate after removing the resist film, and removing the insulating film and the second resist film. A fifth step of performing isotropic etching of the semiconductor region as a mask to form an upper recess portion wider than the overlapping region of the opening of the second resist film and the opening of the insulating film in the semiconductor region; And a sixth step of removing the second resist film; and performing anisotropic etching of the semiconductor region using the insulating film as a mask to form a lower recessed portion below the opening of the insulating film. And a seventh step of forming

According to this method, by performing two recess etchings in one photolithography step,
Since the two-stage recess structure including the upper recess portion and the lower recess portion is formed, the same operation as the first aspect is obtained. In addition, since the upper recess portion offset to the source side or the drain side is formed, a recess portion having a large recess width and depth on the source side or the drain side is formed. In other words, since the gate withstand voltage on the source side and the drain side can be controlled independently, when the gate withstand voltage required on the source side and the drain side is different, the gate withstand voltage on the source side and the drain on Adjustment with the gate breakdown voltage becomes possible.

According to a fourth aspect, in the third aspect, between the sixth step and the seventh step, isotropic etching of the semiconductor region is performed using the insulating film as a mask. By doing so, the upper recessed portion can be expanded downward and laterally.

According to this method, since a recess portion having a larger recess width and depth on the source side or the drain side than that of the third aspect is formed, the effect of the third aspect is more remarkably obtained. .

According to a third aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: a first step of forming an insulating film on a semiconductor region on a substrate; Forming a first resist film having an opening in a gate electrode formation region thereon, and etching the insulating film using the first resist film as a mask to form an opening in the insulating film. A third step of forming, and a fourth step of performing isotropic etching of the semiconductor region using at least the insulating film as a mask to form an upper recess portion wider than the opening of the insulating film in the semiconductor region. A step of forming a second resist film having an opening overlapping with the opening of the insulating film on the substrate after removing the first resist film; Second resist film The semiconductor region is isotropically etched as a mask, and a part of the upper recessed portion is enlarged so as to be wider than the overlapping region of the opening of the second resist film and the opening of the insulating film. Sixth
And a seventh step of removing the second resist film; and performing anisotropic etching of the semiconductor region using the insulating film as a mask to form an anisotropic etching of the semiconductor region below the opening of the insulating film. Forming the lower recess in the region
Steps.

According to this method, by performing two recess etchings in one photolithography step,
Since the two-stage recess structure including the upper recess portion and the lower recess portion is formed, the same operation as the first aspect is obtained. In addition, since the upper recessed portion is enlarged by the side etching so as to be offset to the source side or the drain side, a recessed portion having a large recess width and depth on the source side or the drain side is formed. In other words, since the gate withstand voltage on the source side and the drain side can be controlled independently, when the gate withstand voltage required on the source side and the drain side is different, the gate withstand voltage on the source side and the drain on Adjustment with the gate breakdown voltage becomes possible.

According to a sixth aspect of the present invention, in any one of the third to fifth aspects, a drain side edge of the opening of the insulating film is included in the opening of the second resist film. It is preferable that the opening of the second resist film and the opening of the insulating film overlap each other.

According to this method, a recess portion having a large recess width and depth is formed on the drain side. Therefore, an FET having a structure in which the gate withstand voltage on the source side and the drain side can be independently controlled and a gate withstand voltage on the drain side, which often requires a higher gate withstand voltage than the source side, is generally formed.

As described in claim 7, in any one of claims 1 to 6, it is preferable that the anisotropic etching of the semiconductor region is performed by dry etching.

As described in claim 8, in claim 7, the dry etching is preferably performed using a gas containing SiCl ₄ .

[0035] As described in claim 9, in claim 8, and more preferably gas containing the SiCl ₄ is a mixed gas of SiCl ₄ and N _2.

[0036] As described in claim 10, in claim 8 or 9, the gas containing SiCl ₄ is:
Further, it preferably contains SF ₆ .

According to the method of the eighth, ninth or tenth aspect, the anisotropic etching for forming the lower recess portion can be performed without changing the shape of the recess portion formed so far by the high anisotropy. Done. Therefore,
A manufacturing method suitable for manufacturing a field-effect transistor requiring high precision can be obtained.

As set forth in claim 11, in any one of claims 7 to 10, the anisotropic etching and the isotropic etching are performed using a common plasma dry etching apparatus. When performing isotropic etching, high-frequency power is applied to perform plasma etching, while when performing the anisotropic etching, high-frequency power is applied to the electrode on which the substrate is installed, and plasma etching is performed. When performing the isotropic etching, it is preferable to stop the high-frequency power and to use a gas containing a common gas for the isotropic etching and the anisotropic etching.

According to this method, it is possible to continuously perform isotropic etching and anisotropic etching only by changing the etching conditions using the same etching apparatus.
In addition, since the etching condition is changed only by changing a part of the etching gas and controlling on / off of the high-frequency power, a complicated operation is not required and the control can be performed by a simple control.

According to a twelfth aspect of the present invention, in any one of the first to tenth aspects, at least one etching stop layer is provided in the semiconductor region, and the at least one recess portion is provided. Can be formed until the surface of the etching stopper layer is exposed.

According to this method, the depth of the recessed portion on the etching stop layer is controlled with high precision, so that an FET having stable characteristics is formed.

According to a thirteenth aspect, in the twelfth aspect, the at least one etching stop layer is provided immediately below a portion serving as a bottom surface of the lower recess portion, and the lower recess portion is formed. In this case, anisotropic etching can be performed until the surface of the etching stop layer is exposed.

According to this method, the depth of the lower recessed portion is accurately controlled, so that the thickness of the channel region of the semiconductor region below the lower recessed portion becomes substantially constant, and the characteristics such as the threshold value are reduced. An FET with less variation is formed.

According to a fourteenth aspect, in any one of the first to tenth aspects, an upper etching stop layer and a lower etching stop layer which are separated from each other are provided in the semiconductor region. When forming the upper recess, isotropic etching is performed on the bottom surface of the upper recess until the surface of the upper etching layer is exposed, and when forming the lower recess, Anisotropic etching can be performed until the surface of the lower etching stop layer is exposed.

According to this method, not only the depth of the lower recess but also the depth of the upper recess can be controlled with high accuracy.
T will be formed.

According to a fifteenth aspect, in any one of the twelfth to fourteenth aspects, the etching stop layer may be made of a compound semiconductor containing Al.

By utilizing the fact that a compound semiconductor containing Al is hardly etched by this method,
A field-effect transistor using a compound semiconductor having high performance and small variation in characteristics will be manufactured.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described. 1A to 1D are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the first embodiment.

First, in the step shown in FIG. 1A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and a 5 × 10 ¹⁷
a first active layer 13a made of an n-type GaAs layer having a thickness of about 100 nm doped with Si of about cm ^-3, an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and 5 × 10 ¹⁷ A second active layer 13b made of an n-type GaAs layer having a thickness of about 400 nm and doped with Si of about cm ⁻³ is sequentially epitaxially grown, and then, at a position separated from each other on the second active layer 13b. A source electrode 15 and a drain electrode 16 made of an AuGe / Ni / Au film are formed.

Next, in the step shown in FIG. 1B, an opening 17a is formed in the region where the gate electrode is to be formed on the substrate.
After forming the resist film 17 having the
Is used as a mask to perform isotropic etching of the second active layer 13b to form an upper recess 18 wider than the opening 17a of the resist film 17. At this time, although an illustration of a plasma device used for etching is omitted, an inductively coupled dry etching device (hereinafter referred to as ICP) is used, a mixed gas of SiCl ₄ / SF ₆ is introduced into the reaction chamber, and high frequency power is applied to the substrate electrode. The isotropic etching is performed under the condition not to perform.

Next, in the step shown in FIG. 1C, anisotropic etching of the second active layer 13b is performed using the resist film 17 as a mask, and an opening of the resist film 17 is formed in the upper recessed portion 18. A lower recess 19 having a width substantially equal to the width of the portion 17a is formed. At this time, the same ICP was used as the plasma apparatus, and SiCl ₄ / SF ₆ /
Anisotropic etching is performed under the condition of introducing a N ₂ mixed gas and applying high frequency power to the substrate electrode.

Next, in the step shown in FIG. 1D, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

According to the FET manufacturing method of the present embodiment,
Second etching (anisotropic etching) using the resist film 17 used in the first etching (isotropic etching) for forming the upper recess 18 as it is
Is performed to form the lower recess 19, so that the position of the lower recess 19 in the upper recess 18 is determined in a self-aligned manner. In addition, in the second etching step, since the anisotropic etching is performed, the dimension of the upper recessed portion 18 formed first hardly changes, and the controllability of the shape and width of the entire recessed portion is good. Further, since the width of the lower recessed portion 19 is substantially equal to the width of the resist film 17, a fine structure can be realized. Therefore, an FET having a low parasitic source / drain resistance and a high gate breakdown voltage can be manufactured with high uniformity and reproducibility while reducing the number of photolithography steps.

Further, in the manufacturing process of this embodiment, in the first etching and the second etching, the same etching apparatus (plasma apparatus) is used, and only the etching conditions are changed. It is easy to switch to the reactive etching. That is,
In the step shown in FIG. 1B, SiCl ₄ / S
When the GaAs layer is etched under the condition that the F ₆ mixed gas is introduced and the high frequency power is not applied to the substrate electrode, the etching becomes strongly isotropic. Therefore, the opening 17a of the resist film 17 is formed in the second active layer 13b. The upper recessed portion 18 having a width larger than the width of the upper portion is formed. Further, in the step shown in FIG. 1C, when a mixed gas of SiCl ₄ / SF ₆ / N ₂ is introduced into the reaction chamber and the GaAs layer is etched under the condition of applying high-frequency power to the substrate electrode, a very different situation occurs. It is possible to form the lower recessed portion 19 having strong anisotropy and having a width substantially equal to the width of the opening 17a of the resist film 17.
Moreover, during that time, the shape of the upper recessed portion 18 hardly changes.

In addition, by providing an AlGaAs layer (etching stop layer 14) in the semiconductor region and utilizing the fact that the AlGaAs layer is etched little by little by this etching gas, the depth is reduced at the position of the etching stop layer 14. It is possible to form the lower recessed portion 19 having the specified dimensional accuracy. Since the depth of the lower recessed portion 19 is accurately controlled, the thickness of the first active layer 13a which is a channel region below the lower recessed portion 19 becomes substantially constant, and characteristics such as threshold voltage and the like are reduced. Thus, an FET having a small variation in is formed.

(Second Embodiment) Next, a second embodiment of the present invention will be described. 2A to 2E are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the second embodiment.

First, in the step shown in FIG.
On a GaAs substrate 11, an AND having a thickness of about 300 nm is formed.
Buffer layer 12 made of a transparent GaAs layer and 5 × 10¹⁷
cm ^-3About 100 nm thick doped with Si
A first active layer 13a made of an n-type GaAs layer
Consisting of an AlGaAs layer having a thickness of about 10 to 20 nm
Stopping layer 14 and 5 × 10¹⁷cm^-3About Si
From a n-type GaAs layer having a thickness of about 400 nm.
The second active layer 13b is sequentially epitaxially grown.
Let Then, a Si film having a thickness of about 100 nm is formed on the substrate.
O_Two An insulating film 21 made of a film is formed, and this insulating film 21 is
A source made of AuGe / Ni / Au film
The source electrode 15 and the drain electrode 16 are formed.

Next, in the step shown in FIG. 2B, an opening 23a is formed on the substrate in a region where a gate electrode is to be formed.
After forming a resist film 23 having
Is used as a mask, wet etching (side etching) of the insulating film 21 using hydrofluoric acid is performed.
Opening 21 wider than opening 23a of resist film 23
a is formed.

Next, in the step shown in FIG. 2C, the second active layer 13 is formed using the resist film 23 and the insulating film 21 as a mask.
b isotropically etched to form an opening 2 in the insulating film 21.
An upper recessed portion 18 wider than 1a is formed. At this time, although a plasma apparatus used for the etching is not shown, isotropic etching is performed by using ICP, introducing a mixed gas of SiCl ₄ / SF ₆ into the reaction chamber, and applying no high-frequency power to the substrate electrode. .

Next, in the step shown in FIG. 2D, anisotropic etching of the second active layer 13b is performed using the resist film 23 as a mask, and an opening of the resist film 23 is formed in the upper recessed portion 18. A lower recess 19 having a width substantially equal to the width of the portion 23a is formed. At this time, the same ICP was used as the plasma apparatus, and SiCl ₄ / SF ₆ /
Anisotropic etching is performed under the condition of introducing a N ₂ mixed gas and applying high frequency power to the substrate electrode.

Next, in the step shown in FIG. 2E, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

In this embodiment, as in the first embodiment, two recess etchings are performed in one photolithography process under different etching conditions using the same etching apparatus, thereby forming a two-step recess structure. Is formed, the same effect as in the first embodiment can be exerted.

Further, as shown in FIGS. 2B and 2C, an opening 21a wider than the opening 23a of the resist film 23 is formed in the insulating film 21 deposited on the substrate. Using the film 23 and the insulating film 21 as a mask, highly isotropic dry etching is performed to form the upper recess 18.
Is formed, the recess width of the upper recessed portion 18 can be made wider than in the first embodiment. That is, since only the width of the upper recessed portion 18 can be increased while keeping the width of the lower recessed portion 19 small, the FET having a higher gate breakdown voltage as compared with the first embodiment without breaking the fine structure. Can be manufactured.

(Third Embodiment) Next, a third embodiment of the present invention will be described. 3A to 3E are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the third embodiment.

First, in a step shown in FIG. 3A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and a 5 × 10 ¹⁷ layer were formed on a semi-insulating GaAs substrate 11.
a first active layer 13a made of an n-type GaAs layer having a thickness of about 100 nm doped with Si of about cm ^-3, an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and 5 × 10 ¹⁷ A second active layer 13b made of an n-type GaAs layer having a thickness of about 400 nm and doped with Si of about cm ^-3 is sequentially epitaxially grown. Then, a Si film having a thickness of about 100 nm is formed on the substrate.
An insulating film 21 made of an O ₂ film is formed, a part of the insulating film 21 is opened, and a source electrode 1 made of an AuGe / Ni / Au film is located on the second active layer 13b at a position apart from each other.
5 and a drain electrode 16 are formed.

Next, in a step shown in FIG. 3B, an opening 31a is formed on the substrate in a region where a gate electrode is to be formed.
After forming a first resist film 31 having the following characteristics, the first resist film 31 is used as a mask to form an insulating film 2 using CF ₄ gas.
By performing dry etching 1, an opening 21 a having a width substantially equal to that of the opening 31 a of the first resist film 31 is formed. Subsequently, isotropic etching of the second active layer 13b is performed using the first resist film 31 and the insulating film 21 as a mask, thereby forming an upper recess 18 wider than the opening 21a of the insulating film 21. At this time, although a plasma apparatus used for the etching is not shown, isotropic etching is performed by using ICP, introducing a mixed gas of SiCl ₄ / SF ₆ into the reaction chamber, and applying no high-frequency power to the substrate electrode. .

Next, in a step shown in FIG. 3C, after the first resist film 31 is removed, an opening 21a of the insulating film 21 is formed over a region extending from the insulating film 21 to the upper recessed portion 18. A second resist film 32 having an overlapping opening 32a is formed. However, since the width of the opening 32a of the second resist film 32 is substantially the same as the width of the opening 31a of the first resist film 31 and is offset to the drain side, the opening 32a of the second resist film 32 is formed. Inside, the edge of the opening 21a of the insulating film 21 on the drain side is exposed. Then, isotropic etching of the second active layer 13b is performed using the second resist film 32 and the insulating film 21 as a mask, and only the drain-side portion of the upper recessed portion 18 is exposed to the opening of the second resist film 32. It is expanded laterally and downward so as to be wider than the overlap region of the opening 32a and the opening 21a of the insulating film 21. That is, the drain side side etching portion 33 is formed. At this time, although illustration of a plasma device used for etching is omitted,
Using an ICP, a mixed gas of SiCl ₄ / SF ₆ is introduced into the reaction chamber, and isotropic etching is performed under the condition that no high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 3D, after the second resist film 32 is removed, anisotropic etching of the second active layer 13b is performed using the insulating film 21 as a mask, thereby forming the upper recess. A lower recess 19 having a width substantially equal to the width of the opening 21 a of the insulating film 21 is formed in the portion 18. At this time, the same ICP is used as the plasma apparatus, an SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber, and anisotropic etching is performed under the condition that high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 3E, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

In the present embodiment, as in the first embodiment, two recess etchings are performed in a single photolithography process under different etching conditions using the same etching apparatus, so that the upper recess portion is formed. Since a two-step recess structure including the lower part 18 and the lower recess part 19 is formed, the same effect as in the first embodiment can be exerted.

In addition, the upper recessed portion 18 is enlarged in the depth direction and the drain direction by the drain side side etching portion 33 to have a shape offset to the drain side. The shape of the recessed portion is larger in the recess width and the depth on the drain side than the shape of the recessed portion of the first embodiment. As a result, the formed FET has a structure capable of independently controlling the gate breakdown voltage on the source side and the drain side,
In addition, there is an advantage that the gate breakdown voltage on the drain side, which often requires a higher gate breakdown voltage than the source side, is higher than that of the FET of the first embodiment.

In the step shown in FIG. 3B, when forming the opening 21a of the insulating film 21, isotropic etching may be performed instead of anisotropic etching. In that case, the above-described effect is obtained in addition to the effect of the second embodiment.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. 4A to 4E are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the fourth embodiment.

First, in the step shown in FIG. 4A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and a 5 × 10 ¹⁷
a first active layer 13a made of an n-type GaAs layer having a thickness of about 100 nm doped with Si of about cm ^-3, an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and 5 × 10 ¹⁷ A second active layer 13b made of an n-type GaAs layer having a thickness of about 400 nm and doped with Si of about cm ^-3 is sequentially epitaxially grown. Then, a Si film having a thickness of about 100 nm is formed on the substrate.
An insulating film 21 made of an O ₂ film is formed, and a source electrode 15 and a drain electrode 16 made of an AuGe / Ni / Au film are formed in connection holes penetrating the insulating film 21.

Next, in the step shown in FIG. 4B, after forming a first resist film 31 on the substrate, the insulating film 21 is dried using CF ₄ gas using the first resist film 31 as a mask. Etching is performed to form an opening 21a substantially equal in width to the opening 31a of the first resist film 31.

Next, in the step shown in FIG. 4C, after the first resist film 31 is removed, the opening 21 is removed from above the insulating film 21.
A second resist film 32 having an opening 32a overlapping with the opening 21a of the insulating film 21 is formed on a region extending over the area a. However, since the width of the opening 32a of the second resist film 32 is substantially the same as the width of the opening 31a of the first resist film 31 and is offset to the drain side, the opening 32a of the second resist film 32 is formed. Inside, the edge of the opening 21a of the insulating film 21 on the drain side is exposed. Then, isotropic etching of the second active layer 13b is performed using the second resist film 32 and the insulating film 21 as a mask, and the opening 32a of the second resist film 32 is formed.
Then, the upper recessed portion 18 wider than the overlap region of the opening 21a of the insulating film 21 is formed. At this time, although illustration of a plasma device used for etching is omitted,
Using an ICP, a mixed gas of SiCl ₄ / SF ₆ is introduced into the reaction chamber, and isotropic etching is performed under the condition that no high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 4D, after the second resist film 32 is removed, anisotropic etching of the second active layer 13b is performed using the insulating film 21 as a mask to form an upper recess. A lower recess 19 having a width substantially equal to the width of the opening 21 a of the insulating film 21 is formed below the portion 18. The source side surface of the lower recessed portion 19 is formed closer to the source side than the original side surface of the upper recessed portion 18. As a result, in the final finished shape, the source side surface of the upper recessed portion 18 is formed. And the side surface on the source side of the lower recessed portion 19 is in a common plane. At this time, the same ICP was used as the plasma device, and SiC was placed in the reaction chamber.
An anisotropic etching is performed by introducing a mixed gas of l ₄ / SF ₆ / N ₂ and applying high frequency power to the substrate electrode.

Next, in the step shown in FIG. 4E, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

In this embodiment, as in the first embodiment, two recess etchings are performed in a single photolithography process under different etching conditions using the same etching apparatus, so that the upper recess portion is formed. Since a two-step recess structure including the lower part 18 and the lower recess part 19 is formed, the same effect as in the first embodiment can be exerted.

In addition, when comparing the entire recessed portion,
Since the upper recessed portion 18 offset to the drain side is formed, a recessed portion having a larger recess width and depth is formed on the drain side as compared with the shape of the recessed portion of the first embodiment. As a result, the formed FET has a structure in which the gate withstand voltage on the source side and the drain side can be independently controlled, and the gate withstand voltage on the drain side, which often requires a higher gate withstand voltage than the source side, is generally the second. There is an advantage that it is even higher than the FET of the first embodiment.

In the step shown in FIG. 4D, the entire recess portion has a two-step recess structure only on the drain side. However, in the step shown in FIG. Depending on the position of 32a and the amount of etching, the upper recessed portion 18 may extend to the left of the opening 21a of the insulating film 21. However, even in that case, the above-described effects can be exhibited.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. 5A to 5E are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the fifth embodiment.

First, in the step shown in FIG. 5A, the steps shown in FIGS. 4A to 4C in the fourth embodiment have been completed. Then, after the first resist film 31 shown in FIG. 4C is removed, the upper recessed portion 1 is removed from the insulating film 21.
8, a second resist film 3 having an opening 32a overlapping with the opening 21a of the insulating film 21
Form 2 However, the opening 3 of the second resist film 32
The width of the opening 2a of the insulating film 21 is within the opening 32a of the second resist film 32 because the width of the opening 2a is about the same as the width of the opening 31a of the first resist film 31 and offset to the drain side. 21a, the edge on the drain side is exposed. Then, isotropic etching of the second active layer 13b is performed using the second resist film 32 and the insulating film 21 as a mask, and the opening 32a of the second resist film 32 is formed.
Then, the upper recessed portion 18 wider than the overlap region of the opening 21a of the insulating film 21 is formed. At this time, although illustration of a plasma device used for etching is omitted,
Using an ICP, a mixed gas of SiCl ₄ / SF ₆ is introduced into the reaction chamber, and isotropic etching is performed under the condition that no high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 5B, after removing the second resist film 32, a second isotropic etching of the second active layer 13b is performed using the insulating film 21 as a mask. By the second isotropic etching, the upper recessed portion 18 is expanded downward and to the side, and a region of the second active layer 13b immediately below the source side edge of the opening 21a of the insulating film 21. Is side-etched. At this time, although illustration of a plasma device used for etching is omitted, ICP is used and SiCl ₄ / SF ₆ is used in a reaction chamber.
Isotropic etching is performed under the condition that a mixed gas is introduced and no high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG.
Anisotropic etching of the second active layer 13b is performed using 1 as a mask to form a lower recess 19 having a width substantially equal to the width of the opening 21a of the insulating film 21 in the upper recess 18. . At this time, the same I
Anisotropic etching is performed using a CP by introducing a mixed gas of SiCl ₄ / SF ₆ / N ₂ into the reaction chamber and applying high-frequency power to the substrate electrode. As a result, a recess having basically the same shape as the recess in the third embodiment is formed.

Next, in the step shown in FIG. 5D, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

In this embodiment, as in the first embodiment, two recess etchings are performed in one photolithography process under different etching conditions using the same etching apparatus, so that the upper recess portion is formed. Since a two-step recess structure including the lower part 18 and the lower recess part 19 is formed, the same effect as in the first embodiment can be exerted.

In addition, since the upper recessed portion 18 offset to the drain side is first formed and then expanded downward and to the side, the recess width and the recess width at the drain side are further larger than in the fourth embodiment. A recess having a large depth is formed. As a result, the formed FET has a structure in which the gate breakdown voltage on the source side and the drain side can be controlled independently, and the gate breakdown voltage on the drain side, which requires a higher gate breakdown voltage than that on the source side, according to the fourth embodiment. There is an advantage that it is even higher than that.

In the step shown in FIG. 5A, when forming the opening 21a of the insulating film 21, isotropic etching may be performed instead of anisotropic etching. In this case, there is an advantage that the size of the upper recessed portion 18 can be more finely adjusted.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described. 6A to 6D are cross-sectional views illustrating a structure in a manufacturing process of the FET according to the sixth embodiment.

First, in a step shown in FIG. 6A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and a 5 × 10 ¹⁷
a first active layer 13a made of an n-type GaAs layer having a thickness of about 100 nm doped with Si of about cm ^{-3, a} first etching stop layer 14a made of an AlGaAs layer having a thickness of about 10 to 20 nm, and 5. × 10 ¹⁷ cm ^-3 S
n-type GaAs doped with i and having a thickness of about 200 nm
A second active layer 13b composed of a layer and a thickness of 5 to 10 nm
The second etching stop layer 14b made of an AlGaAs layer having a thickness of about 5 nm and the third active layer 13c made of an n-type GaAs layer having a thickness of about 200 nm doped with about 5 × 10 ¹⁷ cm ⁻³ of Si are sequentially epitaxially grown. After that, the AuGe /
A source electrode 15 and a drain electrode 16 made of a Ni / Au film are formed.

Next, in a step shown in FIG. 6B, an opening 17a is formed on the substrate in a region where a gate electrode is to be formed.
After forming the resist film 17 having the
The third active layer 13c is isotropically etched using the mask as a mask to form an upper recess 18 wider than the opening 17a of the resist film 17. At this time, although an illustration of a plasma device used for etching is omitted, an inductively coupled dry etching device (hereinafter referred to as ICP) is used, a mixed gas of SiCl ₄ / SF ₆ is introduced into the reaction chamber, and high frequency power is applied to the substrate electrode The isotropic etching is performed under the condition not to perform.

Next, in the step shown in FIG. 6C, the second etching stop layer 14b and the second active layer 13b are subjected to anisotropic etching using the resist film 17 as a mask to form an upper recess 18. In the opening 17a of the resist film 17,
Is formed in the lower recessed portion 19 having a width substantially equal to the width of. At this time, the same ICP is used as the plasma apparatus, an SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber, and anisotropic etching is performed under the condition that high-frequency power is applied to the substrate electrode. The second etching stop layer 14b is etched little by little by this etching gas, but can be removed by increasing the etching time because the thickness is smaller than that of the first etching stop layer 14a. As a result, a recess having substantially the same shape as that of the recess in the first embodiment is formed.

Next, in the step shown in FIG. 6D, a gate electrode 20 made of Al is formed on the bottom surface of the lower recessed portion 19.

According to the FET manufacturing method of this embodiment,
As in the first embodiment, by performing two recess etchings under different etching conditions using the same etching apparatus in one photolithography process,
Since the two-step recess structure is formed, the same effects as in the first embodiment can be exhibited.

In addition, in the present embodiment, two AlGaAs layers (first and second etching stop layers 14a and 14b) are provided in the semiconductor region, so that not only the lower recess 19 but also the second It is possible to form the upper recessed portion 18 with high dimensional accuracy reaching the etching layer. Therefore, not only the depth of the lower recessed portion 19 but also the depth of the upper recessed portion 18 are accurately controlled, so that an FET having less variation in threshold value and gate breakdown voltage characteristics is formed.

In this embodiment, the example in which two etching stop layers 14a and 14b are provided in the active layer in the manufacturing method of the first embodiment has been described. In embodiments, two or more etch stop layers may be provided.

In the second to fifth embodiments, the entire upper recessed portion is offset to the drain side. However, the present invention is not limited to such an embodiment. It may be offset to the source side.

[0099]

As described above, according to the present invention, the following effects can be obtained.

According to the first aspect, isotropic etching for forming the upper recess and anisotropic etching for forming the lower recess are performed using the common resist film as a mask. Therefore, in one photolithography process, a two-stage recess structure in which the lower recess portion is self-aligned with the upper recess portion can be formed, thereby reducing the number of processes. FET with low parasitic source / drain resistance and high gate breakdown voltage
Can be manufactured with good uniformity and reproducibility.

According to the second aspect, in the first aspect, the upper recessed portion is formed by isotropic etching using the insulating film having an opening wider than the opening of the resist film as a mask. An FET having a withstand voltage can be manufactured.

According to the third aspect, the upper recessed portion is formed by isotropic etching using the resist film and the insulating film whose openings overlap each other as a mask, and then the lower recessed portion is formed using the insulating film as a mask. Since a two-step recessed shape having a different width and a different depth is obtained on the source side and the drain side, even if different gate withstand voltage characteristics are required on the source side and the drain side, it is desirable to form the recess. FET having the characteristics described above can be manufactured.

According to the fourth aspect, in the third aspect, the upper recessed portion is expanded laterally and downwardly, and then the lower recessed portion is formed. By obtaining a two-step recessed shape having a different depth and a particularly large width and one depth, the effect of claim 3 can be more remarkably obtained.

According to the fifth aspect, after forming the upper recessed portion by isotropic etching using the insulating film as a mask,
Using the resist film and the insulating film whose openings overlap each other as a mask, isotropic etching is performed to expand the upper recessed portion downward and to the side by isotropic etching, and then the lower recessed portion is formed by the insulating film. Since it is formed by anisotropic etching using a mask, the width and the depth are different between the source side and the drain side, and one width and the depth are particularly large. The effect of item 3 can be more remarkably obtained.

According to the sixth aspect, in any one of the third to fifth aspects, a recess portion having a large recess width and a large depth is formed on the drain side. An FET having a high drain-side gate withstand voltage, which often requires a high gate withstand voltage, can be manufactured.

According to the seventh aspect, in any one of the first to sixth aspects, the anisotropic etching of the semiconductor region is performed by dry etching. Since reproducibility is good, uniformity and reproducibility of parasitic source / drain resistance and gate withstand voltage can be improved.

According to the eighth, ninth or tenth aspect of the present invention, the anisotropic etching is performed without substantially changing the shape of the recess formed by the selection of the gas in the anisotropic etching. Therefore, a highly accurate field effect transistor can be manufactured.

According to the eleventh aspect, in any one of the seventh to tenth aspects, isotropic etching and anisotropic etching can be continuously performed only by changing the etching conditions using the same etching apparatus. Since the etching is performed, the FET of each claim can be manufactured by simple control without complicated operation.

According to the twelfth, thirteenth, fourteenth, or fifteenth aspect of the present invention, in any one of the first to tenth aspects, an etching stop layer is provided in a semiconductor region to form a recess portion. Etching is performed until the surface of the stop layer is exposed, so that the depth of the recessed portion on the etch stop layer has a small variation in the depth of the F layer.
ET can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a structure in each manufacturing step of a field-effect transistor according to a fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process in a conventional method for manufacturing a field-effect transistor.

FIG. 8 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a field-effect transistor.

[Explanation of symbols]

 Reference Signs List 11 substrate (semi-insulating GaAs substrate) 12 buffer layer (undoped GaAs layer) 13 active layer (n-type GaAs layer) 14 etching stop layer (AlGaAs layer) 15 source electrode 16 drain electrode 17 resist film 17a opening 18 upper recess Unit 19 Lower recess 20 Gate electrode 21 Insulating film 21a Opening 23 Resist film 31 First resist film 31a Opening 32 Second resist film 32a Opening 33 Drain side etch

Claims (15)

[Claims] A first step of forming a resist film having an opening in a gate electrode formation region on a semiconductor region on a substrate; and performing isotropic etching of the semiconductor region using the resist film as a mask. A second step of forming an upper recess wider than the opening of the resist film in the semiconductor region; and performing anisotropic etching of the semiconductor region using the resist film as a mask, A third step of forming a lower recess in a region below the opening of the resist film. 2. The method for manufacturing a field-effect transistor according to claim 1, wherein an insulating film is formed on the semiconductor region before the first step, and the insulating film is formed in the first step. Before the second step, isotropic etching of the insulating film is performed using the resist film as a mask, so that the insulating film is wider than the opening of the resist film. A method of manufacturing a field effect transistor, comprising: forming an opening in an insulating film; and, in the second step, forming the upper recess so as to be wider than the opening in the insulating film. 3. A first step of forming an insulating film on a semiconductor region on a substrate, and a second step of forming a first resist film having an opening in a gate electrode forming region on the insulating film. A step of forming an opening in the insulating film by etching the insulating film using the first resist film as a mask; and removing the first resist film, and A second opening having an opening overlapping with the opening of the insulating film.
A fourth step of forming a resist film, and performing isotropic etching of the semiconductor region using the insulating film and the second resist film as a mask, and forming an opening of the second resist film in the semiconductor region. A fifth step of forming an upper recess portion wider than the overlap region of the opening of the insulating film, a sixth step of removing the second resist film, and the semiconductor region using the insulating film as a mask And forming a lower recessed portion below the opening of the insulating film by performing the anisotropic etching of the above (7). 4. The method according to claim 3, wherein the semiconductor region is isotropically etched using the insulating film as a mask between the sixth step and the seventh step. Wherein the upper recess is enlarged downward and to the side. 5. A first step of forming an insulating film on a semiconductor region on a substrate, and a second step of forming a first resist film having an opening in a gate electrode forming region on the insulating film. A third step of etching the insulating film using the first resist film as a mask to form an opening in the insulating film; and isotropically etching the semiconductor region using at least the insulating film as a mask. Performing a fourth step of forming an upper recessed portion wider than the opening of the insulating film in the semiconductor region. After removing the first resist film, the opening of the insulating film is formed on the substrate. Second portion having an opening overlapping the portion
A fifth step of forming a resist film, and performing isotropic etching of the semiconductor region using the insulating film and the second resist film as a mask, thereby forming a part of the upper recessed portion into the second resist. A sixth step of enlarging the film so as to be wider than an overlapping region of the opening of the film and the opening of the insulating film, a seventh step of removing the second resist film, and using the insulating film as a mask. An eighth step of performing anisotropic etching of the semiconductor region to form a lower recess in a region below the opening of the insulating film in the semiconductor region. Method. 6. The method for manufacturing a field-effect transistor according to claim 3, wherein a drain side edge of the opening of the insulating film is included in the opening of the second resist film. The opening of the second resist film and the opening of the insulating film overlap each other. 7. The method for manufacturing a field effect transistor according to claim 1, wherein the anisotropic etching of the semiconductor region is dry etching. Production method. 8. The method for manufacturing a field effect transistor according to claim 7, wherein said dry etching is performed using a gas containing SiCl ₄ . 9. The method for manufacturing a field effect transistor according to claim 8, wherein the gas containing SiCl ₄ is a mixed gas of SiCl ₄ and N ₂ . 10. The method for manufacturing a field-effect transistor according to claim 8, wherein the gas containing SiCl ₄ further contains SF ₆ . 11. The method for manufacturing a field effect transistor according to claim 7, wherein the anisotropic etching and the isotropic etching are performed using a common plasma dry etching apparatus. When performing the anisotropic etching, high-frequency power is applied to the electrode on which the substrate is installed to perform plasma etching, while when performing the isotropic etching, the high-frequency power is stopped and the isotropic etching is performed. A method for manufacturing a field-effect transistor, wherein a gas containing a common gas is used for the reactive etching and the anisotropic etching. 12. The method for manufacturing a field-effect transistor according to claim 1, wherein at least one etching stop layer is provided in the semiconductor region. A method of manufacturing a field-effect transistor, comprising: performing etching until the surface of the etching stop layer is exposed when forming two recessed portions. 13. The method for manufacturing a field-effect transistor according to claim 12, wherein the at least one etching stop layer is provided immediately below a portion serving as a bottom surface of the lower recess. A method of manufacturing a field-effect transistor, comprising: performing anisotropic etching until the surface of the etching stop layer is exposed when forming. 14. The method for manufacturing a field effect transistor according to claim 1, wherein an upper etching stop layer and a lower etching stop layer that are separated from each other are provided in the semiconductor region. When forming the upper recess, isotropic etching is performed on the bottom surface of the upper recess until the surface of the upper etching layer is exposed, and when forming the lower recess, A step of performing anisotropic etching until the surface of the lower etching stop layer is exposed. 15. The field effect transistor according to claim 12, wherein the etching stop layer is made of a compound semiconductor containing Al. Production method.